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This commit has been processed because it contains a "Fixes:" tag,
fixing commit: cd70f3d6e3fa drm/amd/powerplay: PP/DAL interface changes for
dynamic clock switch.
The bot has tested the following trees: v4.20.5, v4.19.18, v4.14.96.
v4.20.5: Build OK!
v4.19.18
From: Marek Olšák
Normal syncobjs signal when an IB finishes. Start syncobjs signal when
an IB starts.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 18 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++
On 1/28/19 10:19 AM, Alex Deucher wrote:
> On Fri, Jan 25, 2019 at 5:31 PM Gustavo A. R. Silva
> wrote:
>>
>> Add missing break statement in order to prevent the code from falling
>> through to the default case.
>>
>> The resoning for this is that pclk_vol_table is an automatic variable.
>> So,
Am 22.01.19 um 22:45 schrieb Marek Olšák:
From: Marek Olšák
- move all adjustments into one place
- specify GDS/GWS/OA alignment in basic units of the heaps
- it looks like GDS alignment was 1 instead of 4
Signed-off-by: Marek Olšák
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/
From: Michel Dänzer
And only clear it if it matches the framebuffer of the completed flip
being processed.
Fixes
(WW) RADEON(0): flip queue failed: Device or resource busy
(WW) RADEON(0): Page flip failed: Device or resource busy
(EE) RADEON(0): present flip failed
due to clobbering drmmode
From: Michel Dänzer
To make sure the client can't use the shared pixmap storage for direct
rendering first, which could produce garbage.
Bugzilla: https://bugs.freedesktop.org/109235
(Ported from amdgpu commit d168532ee739f7e33a2798051e64ba445dd3859f)
Signed-off-by: Michel Dänzer
---
src/rade
From: Michel Dänzer
drmHandleEvent can be interrupted by a signal in read(), in which case
it doesn't process any events but returns -1, which
drm_handle_event propagated to its callers. This could cause the
following failure cascade:
1. drm_wait_pending_flip stopped waiting for a pending flip.
From: Michel Dänzer
drm_wait_pending_flip stopped waiting if drm_handle_event returned 0,
but that might have processed only some unrelated DRM events. As long as
the flip is pending, we have to keep waiting for its completion event.
Noticed while working on the previous fix.
(Ported from amdgp
From: Michel Dänzer
We were using a relative target of 0, meaning "complete the flip ASAP".
This could result in the flip sometimes, but not always completing in
the same vertical blank period where the corresponding drawing occurred,
potentially causing judder artifacts with applications updatin
From: Michel Dänzer
To make sure the client can't use the shared pixmap storage for direct
rendering first, which could produce garbage.
Bugzilla: https://bugs.freedesktop.org/109235
(Ported from amdgpu commit ebd32b1c07208f8dbe853e089f5e4b7c6a7a658a)
Signed-off-by: Michel Dänzer
---
src/rade
From: Michel Dänzer
If the compositing manager uses direct rendering (as is usually the case
these days), the storage of a pixmap allocated by glamor_create_pixmap
needs to be reallocated for sharing it with the compositing manager.
Instead, allocate pixmap storage which can be shared directly.
Ping
On Tue, Jan 22, 2019 at 4:45 PM Marek Olšák wrote:
> From: Marek Olšák
>
> - move all adjustments into one place
> - specify GDS/GWS/OA alignment in basic units of the heaps
> - it looks like GDS alignment was 1 instead of 4
>
> Signed-off-by: Marek Olšák
> ---
> drivers/gpu/drm/amd/amdg
Ping
On Tue, Jan 22, 2019 at 3:05 PM Marek Olšák wrote:
> From: Marek Olšák
>
> I'm not increasing the DRM version because GDS isn't totally without bugs
> yet.
>
> v2: update emit_ib_size
>
> Signed-off-by: Marek Olšák
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 2 ++
> drivers/gpu/dr
On Mon, Jan 28, 2019 at 12:02 PM Liu, Shaoyun wrote:
>
> Reduce the unnecessary repeat node and hive information during XGMI
> initialization
>
> Change-Id: I1c1e4dadf9d771cde53225666b9a10ceca9167c0
> Signed-off-by: shaoyunl
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_xg
Reduce the unnecessary repeat node and hive information during XGMI
initialization
Change-Id: I1c1e4dadf9d771cde53225666b9a10ceca9167c0
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
On 2019-01-28 9:00 a.m., Nicholas Kazlauskas wrote:
> [Why]
> The flip and full structures were allocated but never freed.
>
> [How]
> Free them at the end of the function. There's a small behavioral
> change here with the function returning early if the allocation fails
> but we wouldn't should b
On Fri, Jan 25, 2019 at 5:31 PM Gustavo A. R. Silva
wrote:
>
> Add missing break statement in order to prevent the code from falling
> through to the default case.
>
> The resoning for this is that pclk_vol_table is an automatic variable.
> So, it makes no sense to update it just before falling th
From: Wenjing Liu
[ Upstream commit 99b922f9ed6a6313c0d2247cde8aa1e4a0bd67e4 ]
[why]
Some dongle doesn't have a valid extended dongle caps,
but we still set the extended dongle caps to be valid.
This causes validation fails for all timing.
[how]
If no dp_hdmi_max_pixel_clk is provided,
don't us
From: Eric Yang
[ Upstream commit 12750d1647f118496f1da727146f255f5e44d500 ]
[Why]
YCbCr420 packing format uses two chanels for luma, and 1
channel for both chroma component. Our previous implementation
did not account for this and results in every other pixel having
very high luma value, showin
From: Paul Hsieh
[ Upstream commit bd4905a9583c760da31ded7256dca6f71483c3dc ]
[WHY]
On customer board, there is one pluse (1v , < 1ms) on
DDC_CLK pin when plug / unplug DP cable. Driver will read
it and config DP to HDMI/DVI dongle.
[HOW]
If there is a real dongle, DDC_CLK should be always pull
From: Alex Deucher
[ Upstream commit de4aaab5cc9770a8c4dc13d9bfb6a83b06bba57e ]
Adjust limits for newer polaris variants.
v2: fix polaris11 kicker (Jerry)
Reviewed-by: Junwei Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c |
From: Murton Liu
[ Upstream commit 8ce504b9389be846bcdf512ed5be8f661b3bf097 ]
[why]
Gamma was always being set as identity on SDR monitor,
leading to no changes in gamma. This caused nightlight to
not apply correctly.
[how]
Added a default gamma structure to compare against
in the sdr case.
Si
From: Yogesh Mohan Marimuthu
[ Upstream commit 08e1c28dd521c7b08d1b0af0bae9fb22ccc012a4 ]
[why]
phy_pix_clk is one of the variable used to check if one PLL can be shared
with displays having common mode set configuration. As of now
phy_pix_clock varialbe is calculated in function dc_validate_str
From: Wenjing Liu
[ Upstream commit 99b922f9ed6a6313c0d2247cde8aa1e4a0bd67e4 ]
[why]
Some dongle doesn't have a valid extended dongle caps,
but we still set the extended dongle caps to be valid.
This causes validation fails for all timing.
[how]
If no dp_hdmi_max_pixel_clk is provided,
don't us
From: Eric Yang
[ Upstream commit 12750d1647f118496f1da727146f255f5e44d500 ]
[Why]
YCbCr420 packing format uses two chanels for luma, and 1
channel for both chroma component. Our previous implementation
did not account for this and results in every other pixel having
very high luma value, showin
From: Paul Hsieh
[ Upstream commit bd4905a9583c760da31ded7256dca6f71483c3dc ]
[WHY]
On customer board, there is one pluse (1v , < 1ms) on
DDC_CLK pin when plug / unplug DP cable. Driver will read
it and config DP to HDMI/DVI dongle.
[HOW]
If there is a real dongle, DDC_CLK should be always pull
From: Dale Zhao
[ Upstream commit 0a6414e75d231ee1bb7ffb2f5eb246b682a884cd ]
[Why]
In 99% user case, edp will be post by vbios.
In 1% / current case: Lenovo don't light up edp panel in vbios
post stage, vbios won't be lit up. Thus in dal when we init DCN
10 hw, we power up edp, then we start det
From: Alex Deucher
[ Upstream commit de4aaab5cc9770a8c4dc13d9bfb6a83b06bba57e ]
Adjust limits for newer polaris variants.
v2: fix polaris11 kicker (Jerry)
Reviewed-by: Junwei Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c |
From: Yogesh Mohan Marimuthu
[ Upstream commit 08e1c28dd521c7b08d1b0af0bae9fb22ccc012a4 ]
[why]
phy_pix_clk is one of the variable used to check if one PLL can be shared
with displays having common mode set configuration. As of now
phy_pix_clock varialbe is calculated in function dc_validate_str
From: Murton Liu
[ Upstream commit 8ce504b9389be846bcdf512ed5be8f661b3bf097 ]
[why]
Gamma was always being set as identity on SDR monitor,
leading to no changes in gamma. This caused nightlight to
not apply correctly.
[how]
Added a default gamma structure to compare against
in the sdr case.
Si
From: Bhawanpreet Lakha
[ Upstream commit 4f7129112c2a30331f3045a42026fad82e6cb72b ]
[Why]
Fix surface/plane potential nullptr
[How]
add null check
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Aric Cyr
Acked-by: Leo Li
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/g
On 2019-01-28 3:00 p.m., Nicholas Kazlauskas wrote:
> [Why]
> The flip and full structures were allocated but never freed.
>
> [How]
> Free them at the end of the function. There's a small behavioral
> change here with the function returning early if the allocation fails
> but we wouldn't should b
Reviewed-by: Chunming Zhou
send from my phone
原始邮件
主题：[PATCH 2/2] drm/amdgpu: cleanup setting bulk_movable
发件人：Christian König
收件人：amd-gfx@lists.freedesktop.org
抄送：
We only need to set this to false now when BOs are removed from the LRU.
Signed-off-by: Christian König
---
On 2019-01-28 9:00 a.m., Nicholas Kazlauskas wrote:
> [Why]
> The flip and full structures were allocated but never freed.
>
> [How]
> Free them at the end of the function. There's a small behavioral
> change here with the function returning early if the allocation fails
> but we wouldn't should
[Why]
The flip and full structures were allocated but never freed.
[How]
Free them at the end of the function. There's a small behavioral
change here with the function returning early if the allocation fails
but we wouldn't should be doing anything in that case anyway.
Fixes: c00e0cc0fdc0 ("drm/a
On 1/28/19 6:59 AM, Michel Dänzer wrote:
> On 2019-01-22 7:28 p.m., sunpeng...@amd.com wrote:
>> From: David Francis
>>
>> [Why]
>> amdgpu_dm_commit_planes was performing multi-plane
>> flips incorrectly:
>>
>> It waited for vblank once per flipped plane
>>
>> It prepared flip ISR and acquired the
kptr is not used any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0bc6f553dc08..a404ac17e5ae 100644
--- a/drivers/g
We only need to set this to false now when BOs are removed from the LRU.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a404a
On 2019-01-22 7:28 p.m., sunpeng...@amd.com wrote:
> From: David Francis
>
> [Why]
> amdgpu_dm_commit_planes was performing multi-plane
> flips incorrectly:
>
> It waited for vblank once per flipped plane
>
> It prepared flip ISR and acquired the corresponding vblank ref
> once per plane, altho
Am 24.01.19 um 04:38 schrieb wentalou:
sriov need to restrict max_pfn below AMDGPU_GMC_HOLE.
access the hole results in a range fault interrupt IIRC.
Change-Id: I0add197a24a54388a128a545056e9a9f0330abfb
Signed-off-by: Wentao Lou
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu
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