Am 25.02.19 um 19:47 schrieb Liu, Shaoyun:
On 2019-02-25 10:50 a.m., Christian König wrote:
Am 22.02.19 um 22:28 schrieb Liu, Shaoyun:
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699
OK, thanks for the advice. I will try to put pp_feature in the struct amdgpu_pm
and send out the changed patch latter.
Regards,
Likun
-Original Message-
From: amd-gfx On Behalf Of Huang, Ray
Sent: Tuesday, February 26, 2019 2:02 PM
To: Alex Deucher
Cc: Gao, Likun ; Wang, Kevin(Yang) ;
> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, February 26, 2019 12:08 PM
> To: Huang, Ray
> Cc: amd-gfx list ; Gao, Likun
> ; Wang, Kevin(Yang) ; Gui,
> Jack
> Subject: Re: [PATCH 13/26] drm/amd/powerplay: add limit of pp_feature for
> smu
>
>
> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, February 26, 2019 11:59 AM
> To: Huang, Ray
> Cc: amd-gfx list ; Gao, Likun
> ; Wang, Kevin(Yang) ; Gui,
> Jack
> Subject: Re: [PATCH 07/26] drm/amd/powerplay: implement pwm1_enable
> hwmon interface
On Mon, Feb 25, 2019 at 11:25 PM Kuehling, Felix wrote:
>
> On 2/25/2019 2:58 PM, Thomas Hellstrom wrote:
> > On Mon, 2019-02-25 at 14:20 +, Koenig, Christian wrote:
> >> Am 23.02.19 um 00:19 schrieb Kuehling, Felix:
> >>> Don't account for them in other zones such as dma32. The kernel
> >>> p
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/si_dpm.c: In function 'si_program_response_times':
drivers/gpu/drm/amd/amdgpu/si_dpm.c:4101:29: warning:
variable 'backbias_response_time' set but not used [-Wunused-but-set-variable]
It's never used since introduction in
On 2/25/2019 2:58 PM, Thomas Hellstrom wrote:
> On Mon, 2019-02-25 at 14:20 +, Koenig, Christian wrote:
>> Am 23.02.19 um 00:19 schrieb Kuehling, Felix:
>>> Don't account for them in other zones such as dma32. The kernel
>>> page
>>> allocator has its own heuristics to avoid exhausting special
On Mon, Feb 25, 2019 at 7:14 AM Huang Rui wrote:
>
> This patch uses REG32_PCIE wrapper instead of writting pci_index2 and reading
> pci_data2. This sequence should be protected by pcie_idx_lock.
>
> Signed-off-by: Huang Rui
> Reviewed-by: Hawking Zhang
I left comments on a few patches. The re
On Mon, Feb 25, 2019 at 7:13 AM Huang Rui wrote:
>
> From: Likun Gao
>
> Move pp_feature from the struct of amd_powerplay to amdgpu_device.
I think we can probably drop this change. If you do want to move it
out of powerplay, maybe put it in struct amdgpu_pm? I don't like
adding random stuff t
On Mon, Feb 25, 2019 at 7:13 AM Huang Rui wrote:
>
> From: Chengming Gui
>
> set the fan1_enable hwmon interface to call
> smu_get_fan_control_mode and smu_set_fan_control_mode.
>
> v2: fix print value.
>
> Signed-off-by: Chengming Gui
> Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgp
On Mon, Feb 25, 2019 at 7:13 AM Huang Rui wrote:
>
> From: Chengming Gui
>
> 1, set get_pwm1_enable and set_pwm1_enable functions to call
> smu_get_fan_control_mode and smu_set_fan_control_mode for SMU11
> 2, implement set_fan_control_mode function
>
> v2: add return value in set_fan_control_mode
On Mon, Feb 25, 2019 at 7:13 AM Huang Rui wrote:
>
> From: Chengming Gui
>
> add get_power_limit and set_power_limit functions
> to support hwmon for SMU11.
>
> Signed-off-by: Chengming Gui
> Reviewed-by: Huang Rui
> Reviewed-by: Kevin Wang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
Or is the idea that we should never see a PDE fault unless something goes
wrong, and that we would set up an entry corresponding to an unmapped subtree
as an invalid PTE for a very large page rather than an invalid PDE?
Thanks,
John
Original Message
From: Bridgman, John
Sent: Monday, February
Don't we want PDE faults to be treated the same way as page faults? Or am I
misinterpreting the commit message?
Thanks,
John
Original Message
From: Alex Deucher
Sent: Monday, February 25, 2019 21:53
To: Zhao, Yong
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL
On Mon, Feb 25, 2019 at 6:03 PM Zhao, Yong wrote:
>
> This is recommended by HW designers. Previously when it was set to 1,
> the PDE walk error in VM fault will be treated as
> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
> As a result, the retry control in VM_CONTEX
This is recommended by HW designers. Previously when it was set to 1,
the PDE walk error in VM fault will be treated as
PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
The above behavior is kind
From: Anthony Koo
[Why]
AUX transaction returns success, but data has invalid lane count and rate
which when passed to VBIOS command table causes it to soft hang
[How]
Do some sanity checking and fail if the DPCD caps are invalid.
Change-Id: I846615c12223f75d100067ce76792f19b64beab3
Signed-off-
From: Charlene Liu
res_pool->pp_smu may be NULL. Check before use
Change-Id: Ib038334b2374b10012fc374a3aeb5c417655c7c9
Signed-off-by: Charlene Liu
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 --
drivers/gpu/drm/am
From: Aric Cyr
Change-Id: Id4e302521b6e1f8a0f48cefdec5d1018c1af3a09
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/driv
From: Murton Liu
Check if we get any values equal to 0, and set to 1 if so.
Change-Id: I0c52d35fb9564c7a4c8a2c4f3af9c17c1077e7ea
Signed-off-by: Murton Liu
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Sivapiriyan Kumarasamy
---
.../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2
From: Nicholas Kazlauskas
[Why]
Tiling and DCC attributes can change when swapping framebuffers but
these will only ever get updated on full commits where
state->allow_modeset is true. But for the page-flip IOCTL
state->allow_modeset = false so these aren't updated and DCC changes
aren't being pr
From: Anthony Koo
[Why]
UEFI boot usually uses a boot profile that uses higher clocks
and watermark settings.
UEFI boot surface is less optimal, for example it uses linear surface
[How]
Before we finish our seamless boot sequence, keep the clock and
watermark settings from boot.
Update to optima
From: Tyler DiBattista
[Why]
Implemented for future use
Change-Id: Ia05b8c133aa16126f15c91a6516a94b1c4bccad4
Signed-off-by: Tyler DiBattista
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 5 +
drivers/gpu/drm/amd/display/i
From: David Francis
[Why]
The dc_gamma_type CUSTOM_GAMMA is used to represent degamma
mappings passed in by drm. This type of gamma must be interpolated
into a transfer function by apply_1d_lut. The line in
mod_color_calculate_degamma_params that handled this case
was erroneously removed.
[How]
All the gmc_*_set_pde_pte functions are the same across different ASICs,
so we can eliminate the set_pde_pte function pointer and instead use a
generic function.
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 59
drivers/gpu/drm/amd/amdgpu/amdgpu_
From: Nicholas Kazlauskas
[Why]
The current dc_caps doesn't provide the information needed to
determine the count and type of each plane to be exposed to userspace.
There are three types of DRM planes that are exposed to userspace:
1. Primary planes (can be used for modesetting)
2. Overlay plan
Summary of Changes
* Fix Null Pointers
* Update plane tiling attributes
* Overlay and Underlay work
Anthony Koo (2):
drm/amd/display: Keep clocks high before seamless boot done
drm/amd/display: Fix soft hang issue when some DPCD data invalid
Aric Cyr (1):
drm/amd/display: 3.2.20
Charlene L
From: Nicholas Kazlauskas
[Why]
The kms_plane@plane-position-covered-pipe-*-planes subtests can produce
a sequence of atomic commits such that neither active_changed nor
mode_changed but connectors_changed.
When this happens we remove the old stream from the context and add
a new stream but the
From: Martin Leung
[Why]
used to be unable to run 4:2:0 if using a dongle because 4k60 bandwidth
exceeded dongle caps
[How]
half pixel clock during comparison to dongle cap. *Could get stuck on black
screen on monitor that don't support 420 but will be selecting 420 as
preferred mode*
Change-Id
From: Nicholas Kazlauskas
[Why]
Raven has support for combining pipes for DRM_PLANE_TYPE_OVERLAY use
but no overlays are exposed to userspace.
[How]
Expose overlay planes based on DC plane caps.
If all the pipes are in use then the atomic commits can fail, but this
is expected behavior for user
From: Charlene Liu
This reverts commit 39f8d3f6214c1677522de58af02a7cb83205df69
[Description]
Revert since this will be checked at CP side.
Change-Id: I8c54613dde174ffa90cc8a1ba03fe360e25a1d85
Signed-off-by: Charlene Liu
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/dr
From: Thomas Lim
[Why]
The new aux implementation was not up to spec. This caused us to fail DP
compliance as well as introduced serious delays during system resume.
[How]
Make dce_aux_transfer_raw return the operation result
Make dce_aux_transfer_with_retries delay with udelay instead
of mslee
From: David Francis
[Why]
commit_planes is indented quite far
[How]
Move the pageflip code from an if statement to after a
continue
Change-Id: I36ebab704cc7acd0a18e70826c1bf2e55242238f
Signed-off-by: David Francis
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/
From: Nicholas Kazlauskas
[Why]
Primary and underlay planes were previously exposed to DRM by using
max_planes and max_slave_planes.
The value for max_planes was always pipe_count + has_underlay.
If there was an underlay pipe, then max_slave_planes = 1.
Raven has pipe_count = 4, max_planes = 4,
From: David Francis
[Why]
IGT expects that pageflips can be triggered with the same
framebuffer before and after the commit
[How]
Expand the definition of pageflip to include any change
with an old framebuffer and a new framebuffer, even if they're
the same
Change-Id: I66399124224d23b225039da99
From: Jun Lei
In some cases we might need to do a full update. Add a commit_hints
struct for future use
Change-Id: I243c02fa1d1f55b1320d54f8d130b0d7b2b69749
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 2 ++
On Mon, 2019-02-25 at 14:20 +, Koenig, Christian wrote:
> Am 23.02.19 um 00:19 schrieb Kuehling, Felix:
> > Don't account for them in other zones such as dma32. The kernel
> > page
> > allocator has its own heuristics to avoid exhausting special zones
> > for regular kernel allocations.
> >
>
> -Original Message-
> From: amd-gfx On Behalf Of Emil
> Velikov
> Sent: Monday, February 25, 2019 8:09 AM
> To: Alex Deucher
> Cc: Deng, Emily ; Maling list - DRI developers de...@lists.freedesktop.org>; amd-gfx list
> Subject: Re: [PATCH libdrm] libdrm: Fix issue about differrent doma
Some shaders are stuck at "s_load_dwordx4 s[32:35], s[36:37], 0x0", but
that might mean all sorts of things.
Do you also have the dmesg log?
Marek
On Sat, Feb 9, 2019 at 12:20 PM Mikhail Gavrilov <
mikhail.v.gavri...@gmail.com> wrote:
> On Sat, 9 Feb 2019 at 22:01, Marek Olšák wrote:
> >
> > I
On Thu, Feb 21, 2019 at 03:20:01PM -0500, David Francis wrote:
> The DP 1.4 spec defines the SDP header and SDP contents for
> a Picture Parameter Set (PPS) that must be sent in advance
> of DSC transmission to define the encoding characteristics.
>
> This was done in one struct, drm_dsc_pps_infof
On 2019-02-25 10:50 a.m., Christian König wrote:
> Am 22.02.19 um 22:28 schrieb Liu, Shaoyun:
>> Adjust vram base offset for XGMI mapping when update the PT entry so
>> the address will fall into correct XGMI aperture for peer device
>>
>> Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
>> Si
Agree. That's much better actually.
Yong
From: Christian K?nig
Sent: Monday, February 25, 2019 10:44 AM
To: Zhao, Yong; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Differentiate two set_pte_pde function pointers
Am 21.02.19 um 23:58 schrieb Zha
Am 22.02.19 um 22:28 schrieb Liu, Shaoyun:
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_v
Am 21.02.19 um 23:58 schrieb Zhao, Yong:
There were two set_pte_pde function pointers in amdgpu_gmc_funcs and
amdgpu_vm_pte_funcs respectively. Because they are so similar, sometimes
it is confusing. So Rename the one in amdgpu_vm_pte_funcs to
write_pte_pde.
NAK, we also already have a write_pt
On Thu, 21 Feb 2019, David Francis wrote:
> Native 420 and 422 transfer modes are new in DSC1.2
>
> In these modes, each two pixels of a slice are treated as one
> pixel, so the slice width is half as large (round down) for
> the purposes of calucating the groups per line and chunk size
> in bytes
Am 21.02.19 um 21:19 schrieb David Francis:
drm_dsc could use some work so that drm drivers other than
i915 can make use of it their own DSC implementations
Move rc compute, a function that forms part of the DSC spec,
into drm. Update it to DSC 1.2. Also split the PPS packing and
SDP header init
Series is:
Reviewed-by: Alex Deucher
> -Original Message-
> From: amd-gfx On Behalf Of
> Huang Rui
> Sent: Monday, February 25, 2019 2:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Zhang, Hawking
>
> Subject: [PATCH 2/2] drm/amdgpu: use REG32_PCIE wrapper instead for psp
Acked-by: Alex Deucher
> -Original Message-
> From: amd-gfx On Behalf Of Evan
> Quan
> Sent: Monday, February 25, 2019 2:07 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH] drm/amd/powerplay: set max fan target temperature as
> 105C
>
> A workaround to overrid
Am 23.02.19 um 00:19 schrieb Kuehling, Felix:
> Don't account for them in other zones such as dma32. The kernel page
> allocator has its own heuristics to avoid exhausting special zones
> for regular kernel allocations.
>
> Signed-off-by: Felix Kuehling
> CC: thellst...@vmware.com
> CC: christian.
Hi all,
This patch causes unnecessary round trip by openning the nodes. As
mentioned previously this could be trivially fixed [1].
Even Emily acknowledged that [1], yet the sub-par fix was merged. Can
we revert+fixup this properly?
Thanks
Emil
[1] https://lists.freedesktop.org/archives/amd-gfx/
The vega20_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/driver
From: Likun Gao
Functional the function of smu suspend and resume.
Modified the function of smu_smc_table_hw_init to make it useful for smu
resume.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 156 -
drivers/gp
From: Likun Gao
PCIE parameters should be override to fix the conflict between the ASIC
capabilities and the system capabilities.
Signed-off-by: Likun Gao
Reviewed-by: Gui Chengming
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 46 ++
1 f
From: Likun Gao
Move pp_feature from the struct of amd_powerplay to amdgpu_device.
Add pp_feature limit for overdrive interface.
Signed-off-by: Likun Gao
Reviewed-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
The smu_11_0_powerplay_table, smu_11_0_power_saving_clock_table, and
smu_11_0_overdrive_table need byte alignment. So we must add packed attribute
in the definitions.
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Reviewed-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptab
This patch uses REG32_PCIE wrapper instead of writting pci_index2 and reading
pci_data2. This sequence should be protected by pcie_idx_lock.
Signed-off-by: Huang Rui
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++
1 file changed, 3 insertions(+), 4 deletion
We actually want to know the index of PPSMC_MSG.
Signed-off-by: Huang Rui
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powe
From: Chengming Gui
add smu_late_init to complete smu init sequence for SMU11.
Signed-off-by: Chengming Gui
Reviewed-by: Likun Gao
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/a
From: Likun Gao
Add sys interface to get socclk, fclk and dcefclk for smu.
Signed-off-by: Likun Gao
Reviewed-by: Gui Chengming
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 +--
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 56 ++
2 files changed, 65 inser
From: Likun Gao
Set default dpm table fo vclk, dclk and eclk.
Open clk adjust rules for vclk, dclk.
v2: Open clk adjust rules for eclk.
Signed-off-by: Likun Gao
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 18 ++
1 file changed, 6 insertions(+), 12
From: Likun Gao
Add sys interface to set and get pcie info for smu.
Signed-off-by: Likun Gao
Reviewed-by: Gui Chengming
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
From: Likun Gao
Add condition to judge whether overdrive is enabled and correct power
limit value for overdrive used by power limit interface.
Signed-off-by: Likun Gao
Reviewed-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
From: Likun Gao
Smc table hw init should be skipped for suspend/resume when dpm running.
Unified feature enable and disable function into smu_system_features_control.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 +++--
drivers/
This patch moves setting allowed mask and feature enabling together to refine
the programming sequence.
Signed-off-by: Huang Rui
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/
From: Chengming Gui
added main functions:
get_fan_speed_percent
set_fan_speed_percent.
added dependent functions:
smc_fan_control
set_fan_static_mode
get_fan_speed_percent
Signed-off-by: Chengming Gui
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgp
From: Likun Gao
Add sys interface to set socclk, fclk and dcefclk for smu.
Add feature_mask parameter for smu_upload_dpm_level as socclk, fclk and
dcefclk have dependency, without feature_mask to point out specific clk
will make it fail to set some clk.
Fix the function of smu_unforce_dpm_levels.
From: Chengming Gui
add AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK and
AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK to support
read sensor for SMU11.
Signed-off-by: Chengming Gui
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8
1 file changed, 8 ins
From: Chengming Gui
add is_dpm_running function to support smu s3 case.
Signed-off-by: Chengming Gui
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12
2 files changed, 16 insertions(+)
diff -
From: Chengming Gui
1, set get_pwm1_enable and set_pwm1_enable functions to call
smu_get_fan_control_mode and smu_set_fan_control_mode for SMU11
2, implement set_fan_control_mode function
v2: add return value in set_fan_control_mode function
Signed-off-by: Chengming Gui
Reviewed-by: Huang Rui
From: Likun Gao
Add fan1_target set interface to set fan speed for hwmon.
Signed-off-by: Likun Gao
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 --
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/p
From: Likun Gao
Get eclk, vclk and dclk info from vbios when hw init for smu11.
Signed-off-by: Likun Gao
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 42 ++
2 files changed, 45 inser
From: Chengming Gui
set the fan1_enable hwmon interface to call
smu_get_fan_control_mode and smu_set_fan_control_mode.
v2: fix print value.
Signed-off-by: Chengming Gui
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 23 +++
drivers/gpu/drm/amd/powe
From: Chengming Gui
add get_power_limit and set_power_limit functions
to support hwmon for SMU11.
Signed-off-by: Chengming Gui
Reviewed-by: Huang Rui
Reviewed-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 15 --
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |
From: Likun Gao
Add fan1_min and fan2_max function for hwmon.
Signed-off-by: Likun Gao
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/dri
From: Kevin Wang
when sw smu is enabled, the powerplay interface isn't implemented.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers
Hi all,
These series are the updates for SW SMU driver. It adds more interfaces for
sysfs and hwmon and fix some coding errors. And add suspend/resume function, for
now, it already passed S3 test with SW SMU.
Thanks,
Ray
Chengming Gui (7):
drm/amd/powerplay: implement power1_cap and power1_cap
From: Likun Gao
Add fan1_input and fan1_target interface to get fan speed info for hwmon.
Signed-off-by: Likun Gao
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
dri
Add amd-gfx. Thanks Candice. Please check your code alignment before committed
the patch.
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Li, Candice
Sent: 2019年2月25日 11:09
To: Zhang, Hawking ; Xu, Feifei
Cc: brahma_sw_dev
Subject: [PATCH] Revert "drm/amdgpu: use BACO reset on vega20 if pl
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan
Quan
Sent: Monday, February 25, 2019 3:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: set max fan target temperature a
79 matches
Mail list logo
