RE: [PATCH] drm/amdgpu/powerplay: silence a warning in smu_v11_0_setup_pptable

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Thursday, August 22, 2019 11:25 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/powerplay: silence a warning in > smu_v11_0_setup_pptable > > I

RE: [PATCH v4 1/4] drm/amdgpu: Add RAS EEPROM table.

> -Original Message- > From: Andrey Grodzovsky > Sent: 2019年8月22日 4:02 > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Pan, Xinhui > ; Zhang, Hawking ; > Tuikov, Luben ; Lazar, Lijo ; > Quan, Evan ; Panariti, David > ; Russell, Kent ; Zhou1, > Tao ; Grodzovsky, Andrey >

[PATCH] drm/amdgpu/powerplay: silence a warning in smu_v11_0_setup_pptable

I think gcc is confused as I don't see how size could be used unitialized, but go ahead and silence the warning. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH] drm/amdgpu: add dummy read for some GCVM status registers

The GRBM register interface is now capable of bursting 1 cycle per register wr->wr, wr->rd much faster than previous muticycle per transaction done interface. This has caused a problem where status registers requiring HW to update have a 1 cycle delay, due to the register update having to go

Re: [PATCH] drm/amdkfd: remove set but not used variable 'pdd'

Applied. thanks! Alex On Fri, Jul 26, 2019 at 11:58 AM YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c: In function > restore_process_worker: > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:949:29: warning: >

Re: [PATCH] drm/amd/display: remove duplicated include from dc_link.c

Applied. thanks! Alex On Fri, Jul 26, 2019 at 5:42 AM YueHaibing wrote: > > Remove duplicated include. > > Reported-by: Hulk Robot > Signed-off-by: YueHaibing > --- > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 > 1 file changed, 4 deletions(-) > > diff --git

Re: [PATCH -next] drm/amdgpu: remove duplicated include from gfx_v9_0.c

Applied. thanks! Alex On Tue, Jul 9, 2019 at 11:03 PM YueHaibing wrote: > > Remove duplicated include. > > Signed-off-by: YueHaibing > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >

Re: [PATCH -next] drm/amdgpu: remove set but not used variable 'psp_enabled'

Applied. thanks! Alex On Thu, Jun 27, 2019 at 10:29 AM YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init': > drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning: > variable 'psp_enabled' set but not used

Re: [PATCH v4 2/4] drm/amd: Import smuio_11_0 headres for EEPROM access on Vega20

On Wed, Aug 21, 2019 at 4:02 PM Andrey Grodzovsky wrote: > > v3: Merge CKSVII2C_IC regs into exsisting headers. > > Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher > --- > .../include/asic_reg/smuio/smuio_11_0_0_offset.h | 92 >

RE: [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir

Reviewed-by: Prike Liang Thanks, Prike > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Thursday, August 22, 2019 6:24 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Liu, Leo > ; Thai, Thong > Subject: [PATCH 37/37] drm/amdgpu: enable VCN DPG

Re: [PATCH v4 4/4] drm/amdgpu: Vega20 SMU I2C HW engine controller.

On Wed, Aug 21, 2019 at 4:02 PM Andrey Grodzovsky wrote: > > Implement HW I2C enigne controller to be used by the RAS EEPROM > table manager. This is based on code from ATITOOLs. > > v2: > Rename the file and all function prefixes to smu_v11_0_i2c > > By Luben's observation always fill the TX

Re: [PATCH v4 3/4] drm/amd/powerplay: Add interface to lock SMU HW I2C.

On Wed, Aug 21, 2019 at 4:02 PM Andrey Grodzovsky wrote: > > v2: > PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict > over I2C bus and engine disable thermal control access to > force SMU stop using the I2C bus until the issue is reslolved. > > Expose and call

Re: [PATCH] drm/amd/display: Fix 32-bit divide error in wait_for_alt_mode

Applied. thanks! Alex On Wed, Aug 21, 2019 at 12:40 PM Harry Wentland wrote: > > On 2019-08-20 7:57 p.m., Nathan Chancellor wrote: > > When building arm32 allyesconfig: > > > > ld.lld: error: undefined symbol: __aeabi_uldivmod > referenced by dc_link.c >

[pull] amdgpu drm-fixes-5.3

Hi Dave, Daniel, A few fixes for 5.3. Nothing major. The following changes since commit 2f62c5d6ed0abae8e70bd83f4d41b9d63acde45a: Merge tag 'drm-fixes-5.3-2019-08-14' of git://people.freedesktop.org/~agd5f/linux into drm-fixes (2019-08-15 13:29:18 +1000) are available in the Git

[PATCH 34/37] drm/amdgpu: update gc/sdma goldensetting for rn

From: Aaron Liu This patch updates gc/sdma goldensetting for renoir Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- 2 files changed, 5 insertions(+), 6

[PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir

From: Thong Thai This will enable indirect SRAM loading for VCN DPG mode initialization. Signed-off-by: Thong Thai Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH 32/37] drm/amd/powerplay: enable renoir dpm feature

From: Prike Liang enable the dpm feature for the renoir. Signed-off-by: Prike Liang Reviewed-by: Aaron Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

[PATCH 36/37] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"

From: Thong Thai This reverts commit 444a0fea5107e9ad7e3cbbafed78678489e31713. We are ready to enable it now. Signed-off-by: Thong Thai Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9

[PATCH 21/37] drm/amdgpu: enable sdma clock gating for rn

From: Prike Liang Enable sdma middle grain and light sleep clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH 31/37] drm/amdgpu: enable SDMA power gating for rn

From: Prike Liang Enable SDMA PG flag during device ip early init. Reviewed-by: Alex Deucher Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 19/37] drm/amdgpu: enable gfx clock gating for rn

From: Prike Liang Enable gfx cg/mg/cp etc clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 27/37] drm/amdgpu: enable athub clock gating for rn

From: Prike Liang Enable athub MG and LS clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 35/37] Revert "drm/amdgpu: disable gfxoff for the moment on renoir"

From: Aaron Liu This reverts commit dfb2c6ee8bec5914d47a4b75f73eff731bb937ae. Signed-off-by: Aaron Liu Acked-by: changzhu Acked-by: Chen Gong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 14/37] drm/amd/powerplay: using valid mapping check for rn

From: Aaron Liu Check whether the message mapping is valid Signed-off-by: Aaron Liu Reviewed-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 5 + drivers/gpu/drm/amd/powerplay/renoir_ppt.c

[PATCH 11/37] drm/amdgpu: add set_gfx_cgpg implement (v2)

From: Aaron Liu add set_gfx_cgpg implement v2: check if using sw_smu (Alex) Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 + drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3

[PATCH 18/37] drm/amdgpu: disable gfxoff for the moment on renoir

From: Huang Rui We still encouter the CP hang while gfxoff is enabled under X start. So disable it for the moment till this issue is addressed. Signed-off-by: Huang Rui Reviewed-by: Aaron Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed,

[PATCH 22/37] drm/amdgpu: enable BIF clock gating for rn

From: Prike Liang Enable BIF light sleep clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 15/37] drm/amd/powerplay: add smu tables for rn

From: Aaron Liu add and map smu tables for renoir Signed-off-by: Aaron Liu Reviewed-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 ++ drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27

[PATCH 28/37] drm/amdgpu: enable DF clock gating for rn

From: Prike Liang Enable DF clock gating during DF IP early init. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 13/37] drm/amd/powerplay: fix checking gfxoff status for rn

From: Aaron Liu For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check gfxoff status. For the first time to enter gfxoff status, it maybe takes about one second more. So just set the max timeout to 5s. GFXOFF_STATUS(bits 2:1)'s description is below: 0=GFXOFF(default). 1=Transition out of GFX

[PATCH 25/37] drm/amdgpu: enable vcn clock gating for rn

From: Prike Liang Enable VCN middle grain clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 24/37] drm/amdgpu: enable rom clock gating for rn

From: Prike Liang Enable rom light sleep clock gating. Reviewed-by: Alex Deucher Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 33/37] drm/amd/powerplay: Disable renoir smu feature retrive for the moment

From: Prike Liang To avoid the dpm frequence range get failed when DPM enabled and it will be enabled later once handle well the feature bit map struct. Signed-off-by: Prike Liang Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 1

[PATCH 16/37] drm/amd/powerplay: init smu tables for rn

From: Aaron Liu Initialize smu tables for renoir: WATERMARKS/DPMCLOCKS/SMU_METRICS Signed-off-by: Aaron Liu Reviewed-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 16 +++

[PATCH 17/37] drm/amd/powerplay: add DPMCLOCKS table implementation

From: Aaron Liu This patch adds add DPMCLOCKS table implementation Rename smu_populate_smc_pptable to smu_populate_smc_tables Signed-off-by: Aaron Liu Reviewed-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher ---

[PATCH 29/37] drm/amdgpu/mmhub1: set mmhub clock gating for rn

From: Prike Liang Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index

[PATCH 26/37] drm/amdgpu: enable IH clock gating for rn

From: Prike Liang Enable IH clock gating during IH block initialized. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[PATCH 10/37] drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2)

From: Aaron Liu This interface support SMU_MSG_GetDriverIfVersion and SMU_MSG_GetSmuVersion checking. v2: squash in driver_if changes (Alex) Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c |

[PATCH 30/37] drm/amdgpu/sdma4: set sdma clock gating for rn

From: Prike Liang Add support for SDMA clockgating on RN. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

[PATCH 23/37] drm/amdgpu: enable HDP clock gating for rn

From: Prike Liang Enable HDP light sleep clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 20/37] drm/amdgpu: enable mmhub clock gating for rn

From: Prike Liang Enable mmhub midle grain and light sleep clock gating. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH 09/37] drm/amd/powerplay: powerup sdma/vcn for all apu series

From: Huang Rui All apu series need powerup sdma and vcn via smu messages. Signed-off-by: Huang Rui Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 06/37] drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir

From: Aaron Liu 1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx ip block Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c| 4 +--

[PATCH 01/37] drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2)

This is the SMU v12 driver message interface. v2: squash in updates Signed-off-by: Alex Deucher --- .../drm/amd/powerplay/inc/smu_v12_0_ppsmc.h | 106 ++ 1 file changed, 106 insertions(+) create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h diff --git

[PATCH 04/37] drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir

From: Aaron Liu add smu_v12_0.c & smu_v12_0.h for renoir Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 37 drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 170 ++ 2 files changed, 207

[PATCH 12/37] drm/amdgpu: add and enable gfxoff feature

From: Aaron Liu This patch updates gfxoff feature. Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Reviewed-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 -

[PATCH 05/37] drm/amdgpu/powerplay: add smu ip block for renoir (v2)

From: Aaron Liu add swSMU [smu_v12_0] for renoir v2: whitespace fixes (Alex) Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c| 2 ++ drivers/gpu/drm/amd/powerplay/Makefile| 2 +-

[PATCH 02/37] drm/amd/powerplay: add smu12_driver_if.h (v3)

From: Aaron Liu This patch adds smu12_driver_if.h v2: squash in updates (Alex) v3: more updates (Alex) Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- .../drm/amd/powerplay/inc/smu12_driver_if.h | 217 ++ 1 file

[PATCH 00/37] Enable power features for Renoir

This patch set adds initial power management support for renoir. Aaron Liu (15): drm/amd/powerplay: add smu12_driver_if.h (v3) drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3) drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir drm/amdgpu/powerplay: add smu ip

[PATCH 03/37] drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3)

From: Aaron Liu Add renoir_ppt and map ppsmc to amdgpu_smu.h v2: squash in ppsmc updates (Alex) v3: squash in driver_if updates (Alex) Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 44 +++

[PATCH 07/37] drm/amdgpu: skip dpm init for renoir

From: Huang Rui Renoir DPM is not functional so far, we skip it for the comment. Will revert this patch once SMU 12 is functional. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 + 1 file changed, 9

[PATCH 08/37] drm/amdgpu/powerplay: add Renoir VCN power management

From: Leo Liu Thus VCN can be powered up for normal operations Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: Evan Quan Reviewed-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++--

Re: [PATCH 2/2] drm/radeon: use WAIT_REG_MEM special op for CP HDP flush

Ignore those. wrong directory. Alex From: Alex Deucher Sent: Wednesday, August 21, 2019 6:20 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 2/2] drm/radeon: use WAIT_REG_MEM special op for CP HDP flush Flush via the ring works

[PATCH] XXX: hack: use atpx rather than HG for runpm v2

force power control even if ATPX claims to not support it. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

[PATCH] drm/amdgpu: add atpx quirk handling

Add quirks for handling PX/HG systems. In this case, add a quirk for a weston dGPU that only seems to properly power down using ATPX power control rather than HG (_PR3). Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 56 +--- 1 file

[PATCH 2/2] drm/radeon: use WAIT_REG_MEM special op for CP HDP flush

Flush via the ring works differently on CIK and requires a special sequence. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 73 +++- 1 file changed, 45 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c

[PATCH 1/2] drm/radeon: use POLL_REG_MEM special op for sDMA HDP flush

Flush via the ring works differently on CIK and requires a special sequence. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik_sdma.c | 36 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik_sdma.c

[PATCH] XXX: hack: disable HG and use PX

Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index c13c51af0b68..9d9004afc81b 100644

Re: [PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

What branch does this patch series actually apply to? I've been trying to apply this locally, but it doesn't appear to apply against drm-tip/drm-tip, amdgpu-next/drm-next, or origin (e.g. kernel.org) /master. Is there any chance we could have this go against drm-tip instead (and even better, split

Re: [PATCH v3 10/16] drm/dp-mst: Add MST support to DP DPCD R/W functions

On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote: > Instead of having drm_dp_dpcd_read/write and > drm_dp_mst_dpcd_read/write as entry points into the > aux code, have drm_dp_dpcd_read/write handle both. > > This means that DRM drivers can make MST DPCD read/writes. > > Cc: Leo Li > Cc:

Re: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

On Wed, 2019-08-21 at 20:02 +, Francis, David wrote: > I know this looks like it could be a DRM helper, but > - That would require a DRM-generic way of knowing if a >connector supports DSC, and current precedent is that >DSC functionality is stored on a driver-specific basis Don't

Re: [PATCH v3 06/16] drm/dp-mst: Add PBN calculation for DSC modes

Reviewed-by: Lyude Paul Thanks! On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote: > With DSC, bpp can be a multiple of 1/16, so > drm_dp_calc_pbn_mode is insufficient. > > Add drm_dp_calc_pbn_mode_dsc, a function which is > the same as drm_dp_calc_pbn_mode, but the bpp is > in units of

Re: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

I know this looks like it could be a DRM helper, but - That would require a DRM-generic way of knowing if a connector supports DSC, and current precedent is that DSC functionality is stored on a driver-specific basis - This function, by necessity, locks global state. Other hardware may

[PATCH v4 4/4] drm/amdgpu: Vega20 SMU I2C HW engine controller.

Implement HW I2C enigne controller to be used by the RAS EEPROM table manager. This is based on code from ATITOOLs. v2: Rename the file and all function prefixes to smu_v11_0_i2c By Luben's observation always fill the TX fifo to full so we don't have garbadge interpreted by the slave as valid

[PATCH v4 1/4] drm/amdgpu: Add RAS EEPROM table.

Add RAS EEPROM table manager to eanble RAS errors to be stored upon appearance and retrived on driver load. v2: Fix some prints. v3: Fix checksum calculation. Make table record and header structs packed to do correct byte value sum. Fix record crossing EEPROM page boundry. v4: Fix byte sum val

[PATCH v4 3/4] drm/amd/powerplay: Add interface to lock SMU HW I2C.

v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the

[PATCH v4 2/4] drm/amd: Import smuio_11_0 headres for EEPROM access on Vega20

v3: Merge CKSVII2C_IC regs into exsisting headers. Signed-off-by: Andrey Grodzovsky --- .../include/asic_reg/smuio/smuio_11_0_0_offset.h | 92 .../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h | 231 + 2 files changed, 323 insertions(+) diff --git

[PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

Whenever a connector on an MST network is attached, detached, or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not

[PATCH v4 0/4] Add RAS EEPROM table and I2C driver implementation.

This patch set introduces EEPROM table to store RAS errors which rise during run time so on next driver load those errors can be retrieved and action taken on them (e.g. Reserve bad memory pages to disallow their usage by the GPU). First patch is HW independent EEPROM table manager while the next

[PATCH v3 15/16] drm/amd/display: MST DSC compute fair share

If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network Implement an algorithm to determine the correct DSC config for each stream The algorithm: This [ ] ( ) represents the range of bandwidths possible

[PATCH v3 10/16] drm/dp-mst: Add MST support to DP DPCD R/W functions

Instead of having drm_dp_dpcd_read/write and drm_dp_mst_dpcd_read/write as entry points into the aux code, have drm_dp_dpcd_read/write handle both. This means that DRM drivers can make MST DPCD read/writes. Cc: Leo Li Cc: Lyude Paul Signed-off-by: David Francis ---

[PATCH v3 12/16] drm/dp-mst: Add helpers for querying and enabling MST DSC

Add drm_dp_mst_dsc_caps_for_port and drm_dp_mst_dsc_enable, two helper functions for MST DSC The former, given a port, returns the raw DPCD DSC caps off that port. The latter, given a port, enables or disables DSC on that port. In both cases, the port given as input should be a leaf of the MST

[PATCH v3 14/16] drm/amd/display: Write DSC enable to MST DPCD

Rework the dm_helpers_write_dsc_enable callback to handle the MST case. Use the drm_dp_mst_dsc_enable helper. Cc: Wenjing Liu Cc: Nikola Cornij Signed-off-by: David Francis --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c| 16 +++- 1 file changed, 15 insertions(+), 1

[PATCH v3 09/16] drm/dp-mst: Parse FEC capability on MST ports

As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating if FEC can be supported up to that point in the MST network. The bit is the first byte of the ENUM_PATH_RESOURCES ack reply, bottom-most bit (refer to section 2.11.9.4 of DP standard, v1.4) That value is needed for FEC and DSC support

[PATCH v3 13/16] drm/amd/display: Validate DSC caps on MST endpoints

During MST mode enumeration, if a new dc_sink is created, populate it with dsc caps as appropriate. Use drm_dp_mst_dsc_caps_for_port to get the raw caps, then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd. Cc: Wenjing Liu Cc: Nikola Cornij Signed-off-by: David Francis ---

[PATCH v3 11/16] drm/dp-mst: Fill branch->num_ports

This field on drm_dp_mst_branch was never filled Initialize it to zero when the list of ports is created. When a port is added to the list, increment num_ports, and when a port is removed from the list, decrement num_ports. v2: remember to decrement on port removal Signed-off-by: David Francis

[PATCH v3 03/16] Revert "drm/amd/display: add global master update lock for DCN2"

This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05. This commit was accidentally promoted twice Signed-off-by: David Francis Reviewed-by: Roman Li Reviewed-by: Harry Wentland Reviewed-by: Nicholas Kazlauskas --- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 --

[PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

This patchset enables Display Stream Compression (DSC) on DP connectors on Navi ASICs, both SST and DSC. 8k60 and 4k144 support requires ODM combine, an AMD internal feature that may be a bit buggy right now. Patches 1 through 5 enable DSC for SST. Most of the work was already done in the Navi

[PATCH v3 05/16] drm/amd/display: Enable SST DSC in DM

In create_stream_for_sink, check for SST DP connectors Parse DSC caps to DC format, then, if DSC is supported, compute the config DSC hardware will be programmed by dc_commit_state Tested-by: Mikita Lipski Signed-off-by: David Francis Reviewed-by: Nicholas Kazlauskas ---

[PATCH v3 06/16] drm/dp-mst: Add PBN calculation for DSC modes

With DSC, bpp can be a multiple of 1/16, so drm_dp_calc_pbn_mode is insufficient. Add drm_dp_calc_pbn_mode_dsc, a function which is the same as drm_dp_calc_pbn_mode, but the bpp is in units of 1/16. Cc: Lyude Paul Cc: Nicholas Kazlauskas Signed-off-by: David Francis ---

[PATCH v3 01/16] Revert "drm/amd/display: skip dsc config for navi10 bring up"

This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256. optc dsc config was causing warnings due to missing register definitions. With the registers restored, the function can be re-enabled The reverted commit also disabled sanity checks and dsc power gating. The sanity check warnings are

[PATCH v3 08/16] drm/amd/display: Initialize DSC PPS variables to 0

For DSC MST, sometimes monitors would break out in full-screen static. The issue traced back to the PPS generation code, where these variables were being used uninitialized and were picking up garbage. memset to 0 to avoid this Signed-off-by: David Francis Reviewed-by: Nicholas Kazlauskas ---

[PATCH v3 04/16] Revert "drm/amd/display: Fix underscan not using proper scaling"

This reverts commit 80e80ec817f161560b4159608fb41bd289abede3. This commit fixed an issue with underscan commits not updating all needed timing values, but through various refactors it is no longer necessary. It causes corruption on odm combine by overwriting the halved h_active in the stream

[PATCH v3 07/16] drm/amd/display: Use correct helpers to compute timeslots

We were using drm helpers to convert a timing into its bandwidth, its bandwidth into pbn, and its pbn into timeslots These helpers -Did not take DSC timings into account -Used the link rate and lane count of the link's aux device, which are not the same as the link's current cap -Did not take FEC

[PATCH v3 02/16] Revert "drm/amd/display: navi10 bring up skip dsc encoder config"

This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c. Re-enable enc2_dp_set_dsc_config. This function caused warnings due to missing register definitions. With the registers added, this now works Signed-off-by: David Francis Reviewed-by: Roman Li Reviewed-by: Harry Wentland

Recall: [PATCH v2 11/14] drm/amd/display: Validate DSC caps on MST endpoints

Liu, Wenjing would like to recall the message, "[PATCH v2 11/14] drm/amd/display: Validate DSC caps on MST endpoints". ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v3 hmm 00/11] Add mmu_notifier_get/put for managing mmu notifier registrations

On Tue, Aug 06, 2019 at 08:15:37PM -0300, Jason Gunthorpe wrote: > This series is already entangled with patches in the hmm & RDMA tree and > will require some git topic branches for the RDMA ODP stuff. I intend for > it to go through the hmm tree. The RDMA related patches have been applied to

Re: [PATCH v2 06/14] drm/dp-mst: Use dc and drm helpers to compute timeslots

On Wed, 2019-08-21 at 12:27 +, Kazlauskas, Nicholas wrote: > On 8/20/19 4:43 PM, Lyude Paul wrote: > > Some nitpicks below > > > > On Tue, 2019-08-20 at 15:11 -0400, David Francis wrote: > > > We were using drm helpers to convert a timing into its > > > bandwidth, its bandwidth into pbn, and

Re: [PATCH] drm/amd/display: Calculate bpc based on max_requested_bpc

Reviewed-by: Leo Li Thanks! On 2019-08-21 12:57 p.m., Nicholas Kazlauskas wrote: > [Why] > The only place where state->max_bpc is updated on the connector is > at the start of atomic check during drm_atomic_connector_check. It > isn't updated when adding the connectors to the atomic state after

Re: [PATCH v2 11/14] drm/amd/display: Validate DSC caps on MST endpoints

On 8/20/19 3:12 PM, David Francis wrote: > The first step in MST DSC is checking MST endpoints > to see how DSC can be enabled > > Case 1: DP-to-DP peer device > if the branch immediately upstream has > - PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2) > - DPCD rev. >= DP 1.4 > - Exactly one

Re: [PATCH] drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x

Reviewed-by: Alex Deucher From: amd-gfx on behalf of Yuan, Xiaojie Sent: Wednesday, August 21, 2019 9:52 AM To: amd-gfx@lists.freedesktop.org Cc: alexdeuc...@gmail.com ; Xiao, Jack ; Yuan, Xiaojie ; Zhang, Hawking Subject: [PATCH] drm/amdgpu/sdma5: fix

[PATCH] drm/amd/display: Calculate bpc based on max_requested_bpc

[Why] The only place where state->max_bpc is updated on the connector is at the start of atomic check during drm_atomic_connector_check. It isn't updated when adding the connectors to the atomic state after the fact. It also doesn't necessarily reflect the right value when called in amdgpu during

Re: [PATCH] drm/amd/display: Fix 32-bit divide error in wait_for_alt_mode

On 2019-08-20 7:57 p.m., Nathan Chancellor wrote: > When building arm32 allyesconfig: > > ld.lld: error: undefined symbol: __aeabi_uldivmod referenced by dc_link.c gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a referenced by dc_link.c

Re: linux-next: Tree for Aug 19 (amdgpu)

On Wed, Aug 21, 2019 at 03:34:12PM +, Kuehling, Felix wrote: > > On 2019-08-20 8:36 a.m., Jason Gunthorpe wrote: > > On Tue, Aug 20, 2019 at 11:45:54AM +1000, Stephen Rothwell wrote: > >> Hi all, > >> > >> On Mon, 19 Aug 2019 18:34:41 -0700 Randy Dunlap > >> wrote: > >>> On 8/19/19 2:18 AM,

Re: linux-next: Tree for Aug 19 (amdgpu)

On 2019-08-20 8:36 a.m., Jason Gunthorpe wrote: > On Tue, Aug 20, 2019 at 11:45:54AM +1000, Stephen Rothwell wrote: >> Hi all, >> >> On Mon, 19 Aug 2019 18:34:41 -0700 Randy Dunlap >> wrote: >>> On 8/19/19 2:18 AM, Stephen Rothwell wrote: Hi all, Changes since 20190816:

Re: [PATCH] drm/amd/amdgpu: Modify sdma instance number

Am 21.08.19 um 16:32 schrieb Gang Ba: To upgrade performance in small bar mode, set sdma buffer function ring and pte function ring to use different instance. NAK, we intentionally reserved the first paging queue here. I wanted to revert that as well, but in this case you would need to

Re: [PATCH] drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctl

Am 21.08.19 um 16:29 schrieb Haehnle, Nicolai: Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the allocated array as well as the reference counts of sync objects are leaked. Signed-off-by: Nicolai

[PATCH] drm/amd/amdgpu: Modify sdma instance number

To upgrade performance in small bar mode, set sdma buffer function ring and pte function ring to use different instance. Change-Id: Ida6377914eb68a188f745e63409f344f0ce1a8c4 Signed-off-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctl

Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the allocated array as well as the reference counts of sync objects are leaked. Signed-off-by: Nicolai Hähnle --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Re: [PATCH 2/2] drm/amdgpu: disable agp for sriov

Am 21.08.19 um 12:00 schrieb Frank.Min: Since agp is not used for sriov, just disable it Change-Id: I3aa9753499e2e74d982bb611214f94bd57bd Missing Signed-of-by line in the commit message. With that fixed Reviewed-by: Christian König for the series. cd9e ---

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