This is pretty ugly. See a suggestion inline.
On 2019-09-10 4:12 a.m., Huang, Ray wrote:
>> -Original Message-
>> From: S, Shirish
>> Sent: Tuesday, September 10, 2019 3:54 PM
>> To: Deucher, Alexander ; Koenig, Christian
>> ; Huang, Ray
>> Cc: amd-gfx@lists.freedesktop.org; S, Shirish
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chen, Guchun
Sent: 2019年9月11日 11:21
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li,
Dennis ; Zhou1, Tao ; Deucher, Alexander
Cc: Li, Candice ; Chen, Guchun ;
Zhou1, Tao
Subject: [PATCH 4/4]
Call pcie bif ras query/inject in amdgpu ras.
Change-Id: Idf5021edf21e704314338aa2e8b0671e4d622d1d
Signed-off-by: Tao Zhou
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
These registers will be accessed for querying ras errors.
Change-Id: If263879c43b2a5a6136a2fb04990daddd860567d
Signed-off-by: Tao Zhou
Signed-off-by: Guchun Chen
---
.../include/asic_reg/nbio/nbio_7_4_0_smn.h| 12 ++
.../include/asic_reg/nbio/nbio_7_4_sh_mask.h | 43
ras error query funtionality implementation
Change-Id: Id7d8c35621960685a2a7507e4e95939f5a05bdc6
Signed-off-by: Tao Zhou
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
Add the interface query_ras_error_count for nbio.
Change-Id: I32a9d8102068bd8eb53961d290eac1d1a7137a99
Signed-off-by: Tao Zhou
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 ++
2 files changed, 8 insertions(+)
These patches are implemented for ras inject/query error in PCIE BIF
block.
Guchun Chen (4):
drm/amdgpu: add ras error query count interface for nbio
drm/amdgpu: support pcie bif ras query and inject
drm/amdgpu: add pcie bif ras related registers
drm/amdgpu: implement ras query function
amdgpu_ras_reserve_bad_pages is only used by umc block, so another approach is
to move it into amdgpu_umc_process_ras_data_cb.
Anyway, either way is OK and the patch is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Andrey Grodzovsky
> Sent: 2019年9月11日 3:41
> To:
Reviewed-by: Feifei Xu
-Original Message-
From: Zhang, Jack (Jian)
Sent: Wednesday, September 11, 2019 10:56 AM
To: amd-gfx@lists.freedesktop.org; Xu, Feifei
Cc: Zhang, Jack (Jian)
Subject: RE: [PATCH] drm/amdgpu/sriov: add ring_stop before ring_create in psp
v11 code
ping
ping
-Original Message-
From: amd-gfx On Behalf Of Jack Zhang
Sent: Tuesday, September 10, 2019 4:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian)
Subject: [PATCH] drm/amdgpu/sriov: add ring_stop before ring_create in psp v11
code
psp v11 code missed ring stop in ring
Thanks Tao!
From: Zhou1, Tao
Sent: Tuesday, September 10, 2019 18:24
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Long, Gang
Subject: RE: [Patch] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA10
Reviewed-by: Tao
On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote:
> On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding
> wrote:
> >
> > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> > > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> > > >
> > > > Hi,
> > > >
> > > > > > Changing
This reverts commit e01f2d41895102d824c6b8f5e011dd5e286d5e8b.
VG20 did not require this workaround, as the fix is in the VBIOS.
Leave VG10/12 workaround as some older shipped cards do not have the
VBIOS fix in place, and the kernel workaround is required in those
situations
Change-Id:
RHEL adds an extra LeaveVT calls to xf86CrtcCloseScreen when they build X server
for the purpose to drop drm master.
Signed-off-by: Slava Grigorev
---
src/amdgpu_kms.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index
Problem:
amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu
because writing to EEPROM during ASIC reset was unstable.
But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called
directly from ISR context and so locking is not allowed. Also it's
irrelevant for this partilcular
DTM is the display topology manager. This is needed to communicate with
psp about the display configurations.
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry
From: Ramalingam C
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on
[Why]
HDCP is not fully finished, so we need to be able to
build and run the driver without it.
[How]
Add a Kconfig to toggle it
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git
[Why]
We need to read and write specific i2c and dpcd messages.
[How]
Created static functions for packing the dpcd and i2c messages for hdcp.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 40 ++-
1 file
[Why]
We need to update the hdcp display parameter whenever the link is
updated, so the next time there is an update to hdcp we have the
latest display info
[How]
Create a callback, and use this anytime there is a change in the link. This will
be used later by the dm.
Signed-off-by: Bhawanpreet
[Why]
This is needed for DP as DP can send us info using irq.
[How]
Check if irq bit is set on short pulse and call the
function that handles cpirq in amdgpu_dm_hdcp
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15
[Why]
All the HDCP transactions should be verified using PSP.
[How]
This patch calls psp with the correct inputs to verify the steps
of authentication.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 328 ++
[Why]
We need to manage the content protection property changes for
different usecase, once cp is DESIRED we need to maintain the
ENABLED/DESIRED status for different cases.
[How]
1. Attach the content_protection property
2. HDCP enable (UNDESIRED -> DESIRED)
call into the module with
From: Ramalingam C
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Pekka have completed the Weston DRM-backend review in
https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
and the UAPI for HDCP
[Why]
We need to interact with the hdcp module from the DM, the module
has to be interacted with in terms of events
[How]
Create the files needed for linux hdcp. These files manage the events
needed for the dm to interact with the hdcp module.
We use the kernel work queue to process the events
[Why]
We need to use HW state to set content protection to ENABLED.
This way we know that the link is encrypted from the HW side
[How]
Create a workqueue that queries the HW every ~2seconds, and sets it to
ENABLED or DESIRED based on the result from the hardware
Signed-off-by: Bhawanpreet Lakha
This patch set introduces HDCP 1.4 capability to Asics starting with Raven(DCN
1.0).
This only introduces the ability to authenticate and encrypt the link. These
patches by themselves don't constitute a complete and compliant
HDCP content protection solution but are a requirement for such a
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 189 +-
[Why]
We don't support HDCP for pre RAVEN asics
[How]
Check if we are RAVEN+. Use this to attach the content_protection
property, this way usermode can't try to enable HDCP on pre DCN asics.
Also we need to update the module on hpd so guard it aswell
Signed-off-by: Bhawanpreet Lakha
[Why]
We need this to enable HDCP on linux, as we need events to interact
with the hdcp module
[How]
Add work queue to display manager and handle the creation and destruction
of the queue
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
From: Ramalingam C
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Pekka have completed the Weston DRM-backend review in
From: Ramalingam C
Considering the significant size of hdcp related code in drm, all
hdcp related codes are moved into separate file called drm_hdcp.c.
v2:
Rebased.
v2:
Rebased.
Signed-off-by: Ramalingam C
Suggested-by: Daniel Vetter
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
From: Ramalingam C
Content protection property is created once and stored in
drm_mode_config. And attached to all HDCP capable connectors.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
Signed-off-by: Daniel Vetter
Link:
From: Ramalingam C
Existing functions for converting a 3bytes(be24) of big endian value
into u32 of little endian and vice versa are renamed as
s/drm_hdcp2_seq_num_to_u32/drm_hdcp_be24_to_cpu
s/drm_hdcp2_u32_to_seq_num/drm_hdcp_cpu_to_be24
Signed-off-by: Ramalingam C
Suggested-by: Daniel
From: Ramalingam C
On every hdcp revocation check request SRM is read from fw file
/lib/firmware/display_hdcp_srm.bin
SRM table is parsed and stored at drm_hdcp.c, with functions exported
for the services for revocation check from drivers (which
implements the HDCP authentication)
This patch
[Why]
We need to manage the content protection property changes for
different usecase, once cp is DESIRED we need to maintain the
ENABLED/DESIRED status for different cases.
[How]
1. Attach the content_protection property
2. HDCP enable (UNDESIRED -> DESIRED)
call into the module with
DTM is the display topology manager. This is needed to communicate with
psp about the display configurations.
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry
[Why]
HDCP is not fully finished, so we need to be able to
build and run the driver without it.
[How]
Add a Kconfig to toggle it
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git
[Why]
We need to read and write specific i2c and dpcd messages.
[How]
Created static functions for packing the dpcd and i2c messages for hdcp.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 40 ++-
1 file
[Why]
We need to use HW state to set content protection to ENABLED.
This way we know that the link is encrypted from the HW side
[How]
Create a workqueue that queries the HW every ~2seconds, and sets it to
ENABLED or DESIRED based on the result from the hardware
Signed-off-by: Bhawanpreet Lakha
From: Ramalingam C
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Pekka have completed the Weston DRM-backend review in
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 189 +-
[Why]
This is needed for DP as DP can send us info using irq.
[How]
Check if irq bit is set on short pulse and call the
function that handles cpirq in amdgpu_dm_hdcp
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15
This patch set introduces HDCP 1.4 capability to Asics starting with Raven(DCN
1.0).
This only introduces the ability to authenticate and encrypt the link. These
patches by themselves don't constitute a complete and compliant
HDCP content protection solution but are a requirement for such a
[Why]
We need this to enable HDCP on linux, as we need events to interact
with the hdcp module
[How]
Add work queue to display manager and handle the creation and destruction
of the queue
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
From: Ramalingam C
On every hdcp revocation check request SRM is read from fw file
/lib/firmware/display_hdcp_srm.bin
SRM table is parsed and stored at drm_hdcp.c, with functions exported
for the services for revocation check from drivers (which
implements the HDCP authentication)
This patch
From: Ramalingam C
Content protection property is created once and stored in
drm_mode_config. And attached to all HDCP capable connectors.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
Signed-off-by: Daniel Vetter
Link:
[Why]
We need to update the hdcp display parameter whenever the link is
updated, so the next time there is an update to hdcp we have the
latest display info
[How]
Create a callback, and use this anytime there is a change in the link. This will
be used later by the dm.
Signed-off-by: Bhawanpreet
[Why]
We don't support HDCP for pre RAVEN asics
[How]
Check if we are RAVEN+. Use this to attach the content_protection
property, this way usermode can't try to enable HDCP on pre DCN asics.
Also we need to update the module on hpd so guard it aswell
Signed-off-by: Bhawanpreet Lakha
From: Ramalingam C
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Pekka have completed the Weston DRM-backend review in
https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
and the UAPI for HDCP
[Why]
All the HDCP transactions should be verified using PSP.
[How]
This patch calls psp with the correct inputs to verify the steps
of authentication.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 328 ++
From: Ramalingam C
Considering the significant size of hdcp related code in drm, all
hdcp related codes are moved into separate file called drm_hdcp.c.
v2:
Rebased.
v2:
Rebased.
Signed-off-by: Ramalingam C
Suggested-by: Daniel Vetter
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
From: Ramalingam C
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on
[Why]
We need to interact with the hdcp module from the DM, the module
has to be interacted with in terms of events
[How]
Create the files needed for linux hdcp. These files manage the events
needed for the dm to interact with the hdcp module.
We use the kernel work queue to process the events
From: Ramalingam C
Existing functions for converting a 3bytes(be24) of big endian value
into u32 of little endian and vice versa are renamed as
s/drm_hdcp2_seq_num_to_u32/drm_hdcp_be24_to_cpu
s/drm_hdcp2_u32_to_seq_num/drm_hdcp_cpu_to_be24
Signed-off-by: Ramalingam C
Suggested-by: Daniel
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 189 +-
On Tue 10-09-19 09:03:29, Tejun Heo wrote:
> Hello, Michal.
>
> On Tue, Sep 10, 2019 at 01:54:48PM +0200, Michal Hocko wrote:
> > > So, while it'd great to have shrinkers in the longer term, it's not a
> > > strict requirement to be accounted in memcg. It already accounts a
> > > lot of memory
Hello, Michal.
On Tue, Sep 10, 2019 at 01:54:48PM +0200, Michal Hocko wrote:
> > So, while it'd great to have shrinkers in the longer term, it's not a
> > strict requirement to be accounted in memcg. It already accounts a
> > lot of memory which isn't reclaimable (a lot of slabs and socket
> >
From: Leo Li
Summary of change:
* Fix pipe split with DSC on high bandwidth timings (8k@60, 4k@144)
* Improve freesync low frame rate compensation (frame doubling) behavior
* Update ABM parameters, limit minimum adjustment
* Misc. refactors and fixes
Anthony Koo (1):
drm/amd/display: set
From: Dmytro Laktyushkin
Global sync update was missing vtg update resulting in underflow if
vstartup decreased a significant amount.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Jaehyun Chung
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 +-
1 file
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c65f34aa2523..7c19ac71b424 100644
---
From: Dmytro Laktyushkin
Detile buffer size affects dcc caps and therefore needs to be
corrected for each ip.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 7 ---
From: Wesley Chalmers
[WHY]
A function to adjust DPP clocks with DTO already exists; function code
is identical to the code replaced here
Signed-off-by: Wesley Chalmers
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 25 ++-
1
From: Aric Cyr
[Why]
There can be some unsynchronized frames when entering/exiting
LFC. This may cause tearing or stuttering at such transitions.
[How]
Add a enter/exit margin to algorithm to smoothly transition into
and out of LFC without desynchronizing frames.
Signed-off-by: Aric Cyr
From: Martin Leung
[why]
seamless boot didn't work for non edp's before
[how]
removed edp-specific code, made dp read uefi-set link settings. Also fixed
a hubbub code line to be consistent with usage of function.
Signed-off-by: Martin Leung
Reviewed-by: Jun Lei
Acked-by: Anthony Koo
From: Dmytro Laktyushkin
Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to
From: Wesley Chalmers
[WHY]
Presently, there is no way for clocks to be lowered, only raised.
[HOW]
Compare clock status against previous known clock status, and optimize
if different.
This requires re-ordering the layout of the dc_clocks structure, as the
current ordering allows identical
From: Zhan Liu
[Why]
When more than 2 displays are connected to the graphics card,
only the minimum memory clock is needed. However, when more
displays are connected, the minimum memory clock is not
sufficient enough to support the overwhelming bandwidth.
System will hang under this
From: Martin Leung
tg_inst may be used uninitialized, so initialize it to 0.
Signed-off-by: Martin Leung
Reviewed-by: Jaehyun Chung
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
2 files changed, 2
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7c19ac71b424..3ecc42987b05 100644
---
From: Julian Parkin
[Why]
Separating the hardware initialization from the creation of the
dc structures gives greater flexibility to the dm to override
options for debugging.
[How]
Move the hardware initialization call to a new function,
dc_hardware_init. No functional change is intended.
From: Wesley Chalmers
[WHY]
This change was made because DTO programming was double-buffered, which
is itself an issue. After deactivating the DTO double buffer, this
change becomes unnecessary.
This reverts commit 79a0feda4306a2e46872fffd1e5507b8e1785244
Signed-off-by: Wesley Chalmers
From: Anthony Koo
[Why]
A lot of the time, the backlight characteristic curve maps min backlight
to a non-zero value.
But there are cases where we want the curve to intersect at 0.
In this scenario even if OS never asks to set 0% backlight, the ABM
reduction can result in backlight being lowered
From: Ilya Bakoulin
[Why]
Secondary viewport dimension/position registers are not programmed,
which can cause issues in some stereo configurations.
[How]
Add register definitions and register programming.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
From: Martin Tsai
[Why]
The new implementation changed the behavior to allow process setMode
to DAL when DAL returns empty mode query for unplugged display.
This will trigger additional disable_link().
When unplug HDMI from MST dock, driver will update stream->signal to
"Virtual". disable_link()
From: Lewis Huang
[Why]
I2C write command always send mot = true will cause sink state incorrect.
[How]
1. Remove default i2c write mot = true.
2. Deciding mot flag by is_end_of_payload flag.
Signed-off-by: Lewis Huang
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
From: Wesley Chalmers
[WHY]
When changing DPP global ref clock, DTO adjustments must take effect
immediately, or else underflow may occur.
It appears the original decision to double-buffer DTO adjustments was made to
prevent underflows that occur when raising DPP ref clock (which is not
From: Stylon Wang
[Why]
Even if YUV420 is available for video mode, YUV444 is still
automatically selected. This poses a problem for compliance tests.
[How]
Add a per-connector debugfs entry "force_yuv420_output" to force
selection of YUV420 mode.
Signed-off-by: Stylon Wang
Reviewed-by:
From: Nikola Cornij
[why]
Some ODM-related register settings are inconsistently updated by VBIOS, causing
the state in DC to be invalid, which would then end up crashing in certain
use-cases (such as disable/enable device).
[how]
Check the enabled status of the second pipe when determining the
From: Dmytro Laktyushkin
dcn20_calculate_dlg_params was incorrectly indexing pipe src and
dst structs when extracting global sync params.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Jaehyun Chung
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
1 file
From: Mikita Lipski
[why]
The issue is specific for linux, as on timings such as 8K@60
or 4K@144 DSC should be working in combination with ODM Combine
in order to ensure that we can run those timings. The validation
for those timings was passing, but when pipe split was happening
second pipe
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3b848d4aca8c..d21e8fc0179e 100644
---
From: Josip Pavic
[Why]
Current configuration 0 is just a placeholder, and final parameters needed.
Also, configuration 1 is expected to emulate ABM 2.1 but is too aggressive.
[How]
Redefine configuration 0 with the finalized parameters, and increase the
contrast gain of configuration 1 so that
From: Dmytro Laktyushkin
Surface dchub/dpp update would not trigger if a stream update was the
only cause. This change now allows stream flags to trigger this update.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file
Regards,
Oak
-Original Message-
From: Koenig, Christian
Sent: Monday, September 9, 2019 1:14 PM
To: Zeng, Oak ; Kuehling, Felix ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 9/9] drm/amdgpu: add graceful VM fault handling v2
> Well first of all we are not in interrupt context
Reviewed-by: Chunming Zhou
在 2019/9/10 16:56, Christian König 写道:
> Ping!
>
> Am 09.09.19 um 13:59 schrieb Christian König:
>> Need to make sure that we actually dropping the right fence.
>> Could be done with RCU as well, but to complicated for a fix.
>>
>> Signed-off-by: Christian König
>>
On Fri 06-09-19 08:45:39, Tejun Heo wrote:
> Hello, Daniel.
>
> On Fri, Sep 06, 2019 at 05:34:16PM +0200, Daniel Vetter wrote:
> > > Hmm... what'd be the fundamental difference from slab or socket memory
> > > which are handled through memcg? Is system memory used by GPUs have
> > > further
Reviewed & Tested-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: Huang, Ray
> Sent: Tuesday, September 10, 2019 7:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix ; Liu, Aaron
> ; Huang, Ray
> Subject: [PATCH] drm/amdkfd: fix the missed asic name while inited
This patch fixes null pointer issue below, I missed to init the asic renior name
while I rebase the patches.
[ 106.004250] BUG: kernel NULL pointer dereference, address:
[ 106.004254] #PF: supervisor read access in kernel mode
[ 106.004256] #PF: error_code(0x) -
Reviewed-by: Tao Zhou mailto:tao.zh...@amd.com>>
From: Yin, Tianci (Rico)
Sent: 2019年9月10日 16:59
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Xu,
Feifei ; Long, Gang
Subject: [Patch] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA10
Next step towards HMM support. For now just silence the retry fault and
optionally redirect the request to the dummy page.
v2: make sure the VM is not destroyed while we handle the fault.
v3: fix VM destroy check, cleanup comments
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
For handling PD/PT clears directly in the fault handler.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
Free the pasid only while the root PD is reserved. This prevents use after
free in the page fault handling.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff
Setting the no_gpu_wait flag means that the allocate BO must be available
immediately and we can't wait for any GPU operation to finish.
Signed-off-by: Christian König
Acked-by: Felix Kuehling
---
drivers/gpu/drm/ttm/ttm_bo.c | 43 +---
1 file changed, 25
For handling PDE updates directly in the fault handler.
v2: fix typo in comment
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
For handling PTE updates directly in the fault handler.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
This allows us to update page tables directly while in a page fault.
v2: use direct/delayed entities and still wait for moves
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 16
While handling a page fault we can't wait for other ongoing GPU
operations or we can potentially run into deadlocks.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
For page fault handling we need to use a direct update which can't be
blocked by ongoing user CS.
Signed-off-by: Christian König
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +++--
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chen, Guchun
> Sent: 2019年9月10日 16:44
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao ;
> Grodzovsky, Andrey
> Cc: Chen, Guchun
> Subject: [PATCH] drm/amdgpu: remove duplicated header file include
>
> amdgpu_ras.h
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