When compute fence did not signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is
These registers are used in GFX9 NGG and the addresses are managed by KMD;
GFX10 has changed the design; UMD does not need to care about these values any
more.
I can confirm UMD does not read these values from KMD.
Alex
-Original Message-
From: Zhou, David(ChunMing)
Sent: Friday, Sept
+Alex Yan to confirm which doesn't affect us.
-Original Message-
From: amd-gfx On Behalf Of Marek Olšák
Sent: Friday, September 20, 2019 10:16 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: remove gfx9 NGG
From: Marek Olšák
Never used.
Signed-off-by: Marek Olšák
When compute fence did not signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is
When compute fence did signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is a t
From: Marek Olšák
Never used.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 41 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 25 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 --
drivers/gpu/drm/amd/amdgpu/gfx
This still needs to be moved into an atomic helper so it can be reused by
other drivers
...
...
however, I've had this patch series on my mind for a while and something
occurred to me that would be a lot easier. Why exactly are we not just
enabling DSC wherever it's supported, regardless of whethe
Great work!
Reviewed-by: Lyude Paul
On Wed, 2019-09-18 at 16:26 -0400, mikita.lip...@amd.com wrote:
> From: David Francis
>
> Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
> support virtual DPCD registers, but do support DSC.
> The DSC caps can be read from the physical aux,
> like in SST D
Reviewed-by: Lyude Paul
On Wed, 2019-09-18 at 16:26 -0400, mikita.lip...@amd.com wrote:
> From: David Francis
>
> Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
> register might have to be written on the leaf port's DPCD,
> its parent's DPCD, or the MST manager's DPCD. This fun
This also needs to be squashed into the previous two patches. There's no point
in using drm_dp_atomic_find_vcpi_slots() or drm_dp_atomic_release_vcpi_slots()
without drm_dp_mst_atomic_check(), since the VCPI allocations setup by the two
functions aren't validated until then.
On Wed, 2019-09-18 at
On Wed, 2019-09-18 at 16:26 -0400, mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> [why]
> Complying with new MST atomic check requirements.
> The driver needs to call this function on every
> atomic check to reset the VCPI slots if new state
> disables
> [how]
> - Verify that it is a MST
Ok, so reviewing this is kind of difficult because this series doesn't apply
to drm-tip, and also doesn't make any mention of what branch it's supposed to
apply to. So there's no way for me to apply any of these changes in my tree to
get an idea of how things look overall with these patches applied
On Wed, Aug 28, 2019 at 2:51 PM Raul E Rangel wrote:
>
> dcn20_resource.c:2636:9: error: missing braces around initializer
> [-Werror=missing-braces]
> struct _vcs_dpi_voltage_scaling_st
> calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
> ^
> Fixes: 7ed4e6352c16f ("drm/amd/display: A
On 9/19/19 9:06 AM, Mark Brown wrote:
> Hi all,
>
> Changes since 20190918:
>
../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/Makefile:70: *** missing
'endif'. Stop.
--
~Randy
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.f
Drop extra function parameter.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index 61f108ec2b5c..4917b548b7f2 100644
--- a/d
Fix DOC link name, clean up formatting in pp_dpm_* section.
Signed-off-by: Alex Deucher
---
Documentation/gpu/amdgpu.rst | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 13 +
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/Documentation/gpu/amdgpu.rst
Document the new parameter.
Fixes: 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu notifiers")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgp
Missing parameters, wrong comment type, etc.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2bb531
Add new sections to amdgpu.rst, fix up formatting issues,
add additional documentation to each section.
Signed-off-by: Alex Deucher
---
Documentation/gpu/amdgpu.rst| 24 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 53 +
2 files changed, 68 insertions
Fix parameters.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 1f2628f445c4..8f49d8131d63 100644
--- a/drivers/gpu
Friendly ping for review.
Thanks
This allows gfx cache to be probed and invalidated (for none-dirty cache lines)
on a HDP write (from either another GPU or CPU). This should work only for the
memory mapped as RW memory type newly added for arcturus, to achieve some cache
coherence b/t multiple memory clients.
Change-Id: I0a69d000
On 2019-09-18 12:30 p.m., Allen Pais wrote:
> alloc_workqueue is not checked for errors and as a result,
> a potential NULL dereference could occur.
>
> Signed-off-by: Allen Pais
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/dri
Hello everyone,
I desperately need to bring back userland mode setting (UMS) support on my
machine for hardware compatibility reasons. As you probably know, UMS support
was removed some years ago, and a new git branch was created with the
UMS-compatible source code of the driver.
I cloned the
On Thu, Sep 19, 2019 at 1:52 PM Harry Wentland wrote:
>
> We had a couple of missing definitions and formatting errors.
>
> v2: Fix 'notifying' type
>
> Signed-off-by: Harry Wentland
> Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/am
We had a couple of missing definitions and formatting errors.
v2: Fix 'notifying' type
Signed-off-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +-
2
On Thu, Sep 19, 2019 at 10:03 AM yu kuai wrote:
>
> Fixes gcc warning:
>
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:431: warning: Excess function
> parameter 'sw' description in 'vcn_v2_5_disable_clock_gating'
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:550: warning: Excess function
> parameter 'sw' desc
On 2019-09-19 1:42 p.m., Harry Wentland wrote:
> We had a couple of missing definitions and formatting errors.
>
> Signed-off-by: Harry Wentland
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +-
>
We had a couple of missing definitions and formatting errors.
Signed-off-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a
On 2019-09-18 6:31 p.m., Allen Pais wrote:
> alloc_workqueue is not checked for errors and as a result,
> a potential NULL dereference could occur.
>
> Signed-off-by: Allen Pais
> ---
> drivers/gpu/drm/radeon/radeon_display.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/
If the page tables are reserved or fenced while you allocate a new one, they
would not be evicted.
And exactly that's not correct. The TTM_OPT_FLAG_ALLOW_RES_EVICT flag
allows evicting of reserved objects.
This is useful for allocating per VM BOs, but is of course completely
fatal in all othe
On Thu, Sep 19, 2019 at 9:45 AM Harry Wentland wrote:
>
> On 2019-09-18 3:53 p.m., Arnd Bergmann wrote:
> > Without CONFIG_DEBUG_FS, we get a warning for an unused
> > variable:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6020:33: error:
> > unused variable 'source' [-Werr
Am 19.09.19 um 16:28 schrieb Sven Van Asbroeck:
> Hi Christian,
>
> On Thu, Sep 19, 2019 at 4:05 AM Koenig, Christian
> wrote:
>>> +out4:
>>> + kfree(i2s_pdata);
>>> +out3:
>>> + kfree(adev->acp.acp_res);
>>> +out2:
>>> + kfree(adev->acp.acp_cell);
>>> +out1:
>>> + kfree(adev->acp.
Hi Dave, Daniel,
A few fixes for 5.4.
The following changes since commit 945b584c94f8c665b2df3834a8a6a8faf256cd5f:
Merge branch 'linux-5.4' of git://github.com/skeggsb/linux into drm-next
(2019-09-17 16:31:34 +1000)
are available in the Git repository at:
git://people.freedesktop.org/~agd
We need a special programming sequence for updating
mmUTCL1_CGTT_CLK_CTRL golden settings.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 96 +-
1 file changed, 78 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.
Hi Christian,
On Thu, Sep 19, 2019 at 4:05 AM Koenig, Christian
wrote:
>
> > +out4:
> > + kfree(i2s_pdata);
> > +out3:
> > + kfree(adev->acp.acp_res);
> > +out2:
> > + kfree(adev->acp.acp_cell);
> > +out1:
> > + kfree(adev->acp.acp_genpd);
>
> kfree on a NULL pointer is harmless,
Let's add comments to clarifying why checking GFX IP BLOCK for SDMA interrupt
so people will not be confusing here.
Regards,
Hawking
-Original Message-
From: Chen, Guchun
Sent: 2019年9月19日 21:59
To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Zhang,
Hawking
Subject: RE: [PATCH 05/21]
I'm not disagreeing with the change. Just trying to understand how this
could have caused a VM fault. If the page tables are reserved or fenced
while you allocate a new one, they would not be evicted. If they are not
reserved or fenced, there should be no expectation that they stay resident.
Is
Two comments in patch 5 and patch 11. Apart from that, the series is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Thursday, September 19, 2019 3:12 PM
To: amd-gfx@lists.freedesktop.org; Chen, Guchun ; Zhang,
Hawking
Cc: Zhou1, Tao
Subject: [PAT
-Original Message-
From: Zhou1, Tao
Sent: Thursday, September 19, 2019 3:13 PM
To: amd-gfx@lists.freedesktop.org; Chen, Guchun ; Zhang,
Hawking
Cc: Zhou1, Tao
Subject: [PATCH 11/21] drm/amdgpu: add common gfx_ras_fini function
gfx_ras_fini can be shared among all generations of gfx
Fixes gcc warning:
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:431: warning: Excess function
parameter 'sw' description in 'vcn_v2_5_disable_clock_gating'
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:550: warning: Excess function
parameter 'sw' description in 'vcn_v2_5_enable_clock_gating'
Fixes: cbead2bdfcf1
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Thursday, September 19, 2019 3:13 PM
To: amd-gfx@lists.freedesktop.org; Chen, Guchun ; Zhang,
Hawking
Cc: Zhou1, Tao
Subject: [PATCH 05/21] drm/amdgpu: refine sdma4 ras_data_cb
simplify code logic and refine return value
S
On 2019-09-18 3:53 p.m., Arnd Bergmann wrote:
> Without CONFIG_DEBUG_FS, we get a warning for an unused
> variable:
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6020:33: error:
> unused variable 'source' [-Werror,-Wunused-variable]
>
> Hide the variable in an #ifdef like its o
Acked-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Thursday, September 19, 2019 9:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Zhang, Jack (Jian)
Subject: [PATCH] drm/amdgpu: restrict hotplug error message
We should print the
We should print the error only when we are hotplugged and crash
basically all userspace applications.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/driv
Acked-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Thursday, September 19, 2019 4:41 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: fix potential VM faults
When we allocate new page tables under memory
pressure we should
On Thu, Sep 19, 2019 at 3:14 AM Jesse Zhang wrote:
>
> From: zhexzhan
>
> Issue: DROOP coef read by HDT appear to be mismatch with requirement of
> BKM0.83
>
> Root cause: These values are supposed to be overwritten by PPLIB.
> However, driver missed code of this part.
>
> Solution: Add overwrit
Am 19.09.19 um 12:09 schrieb Jesse Zhang:
When compute fence did signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout
Hi
Am 19.09.19 um 12:02 schrieb Gerd Hoffmann:
> Rename ttm_fbdev_mmap to ttm_bo_mmap_obj. Move the vm_pgoff sanity
> check to amdgpu_bo_fbdev_mmap (only ttm_fbdev_mmap user in tree).
>
> The ttm_bo_mmap_obj function can now be used to map any buffer object.
> This allows to implement &drm_gem_o
When compute fence did signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is a t
Rename ttm_fbdev_mmap to ttm_bo_mmap_obj. Move the vm_pgoff sanity
check to amdgpu_bo_fbdev_mmap (only ttm_fbdev_mmap user in tree).
The ttm_bo_mmap_obj function can now be used to map any buffer object.
This allows to implement &drm_gem_object_funcs.mmap in gem ttm helpers.
Signed-off-by: Gerd
Ok, thanks very much.
Best wishes
Emily Deng
From: Koenig, Christian
Sent: Thursday, September 19, 2019 5:06 PM
To: Deng, Emily
Cc: Zhang, Jack (Jian) ; amd-gfx@lists.freedesktop.org;
Teng, Rui ; Cui, Flora
Subject: RE: [PATCH] drm/amdgpu/sriov: omit fbcon error under sriov or
passthrough
I
I can create a patch based on this today and push it on Monday.
Christian.
Am 19.09.2019 11:05 schrieb "Deng, Emily" :
Hi Christian,
Could you please help to push the code?
Best wishes
Emily Deng
From: Zhang, Jack (Jian)
Sent: Thursday, September 19, 2019 11:33 AM
To: Deng, Emily ; Koenig, Chri
Hi Christian,
Could you please help to push the code?
Best wishes
Emily Deng
From: Zhang, Jack (Jian)
Sent: Thursday, September 19, 2019 11:33 AM
To: Deng, Emily ; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; Teng, Rui ; Cui, Flora
Subject: RE: [PATCH] drm/amdgpu/sriov: omit fbcon err
When we allocate new page tables under memory
pressure we should not evict old ones.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/a
Am 19.09.19 um 10:00 schrieb Jesse Zhang:
When compute fence did not signal, compute ring cannot detect hardware
hang because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring tim
Am 18.09.19 um 21:05 schrieb Navid Emamdoost:
> In acp_hw_init there are some allocations that needs to be released in
> case of failure:
>
> 1- adev->acp.acp_genpd should be released if any allocation attemp for
> adev->acp.acp_cell, adev->acp.acp_res or i2s_pdata fails.
> 2- all of those allocati
When compute fence did not signal, compute ring cannot detect hardware
hang because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is
When compute fence did signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is a t
From: zhexzhan
Issue: DROOP coef read by HDT appear to be mismatch with requirement of BKM0.83
Root cause: These values are supposed to be overwritten by PPLIB.
However, driver missed code of this part.
Solution: Add overwriting process when reading pptable from vBIOS
Hardcode specific coef wit
add a common nbio ras fini implementation to cleanup nbio ras framework
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
3 files changed, 16 insertions(+),
umc_ras_late_init can get the info by itself
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +
3 files changed, 10 insertions(+), 14 deletions(-)
diff -
sdma_ras_fini can be shared among all generations of sdma
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 16 +---
3 files changed, 21 insertions
it's more suitable to put umc ras fini in umc block
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 1 +
3 files changed, 17 insertions(+), 11 deletions
simplify the code of accessing to eeprom_control struct
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index f72c9f011
it's more suitable to put xgmi ras fini in xgmi block
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 13 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 1 +
3 files changed, 17 insertions(+), 11 dele
gfx_ras_late_init can get the info by itself
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +
3 files changed, 9 insertions(+), 15 deletions(-)
diff --
common gmc_ecc_late_init can be shared among all generations of gmc
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 22 +-
3 files changed,
add ras fini for xgmi to cleanup xgmi ras framework
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 58a95a67336a..4cd206ee
mmhub_ras_if is relevant to mmhub
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c | 24 +++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
3 files changed, 14 insertions(+), 15 deletions(-)
diff --
it's more suitable to put mmhub ras fini in mmhub block
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 2 +-
3 files changed, 16 insertions(+), 12
simplify code logic and refine return value
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 32 ++
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index a
gfx_ras_fini can be shared among all generations of gfx
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +-
3 files changed, 17 insertions(+), 13 del
remove mmhub_funcs in adev
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/am
gmc_ras_fini can be shared among all generations of gmc
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 26 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 +
3 files changed, 28 in
put mmhub_funcs and ras_if pointer into mmhub struct
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 5 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgp
umc_ras_if is relevant to umc
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 28 -
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
4 files changed, 17
When compute fence did signal, compute ring cannot detect hardware hang
because its timeout value is set to be infinite by default.
In SR-IOV and passthrough mode, if user does not declare custome timeout
value for compute ring, then use gfx ring timeout value as default. So
that when there is a t
move umc ras irq functions from gmc v9 to generic umc block
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 65 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 6 +++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 68 +
3 files changed,
gfx ras ecc common functions could be reused among all gfx generations
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 33
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 41 ++---
3 files
sdma ras ecc functions can be reused among all sdma generations
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 28
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 6 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 ++--
3 files cha
change struct ras_err_data *err_data to void *err_data, align with the
implementation of umc code and the callback's declaration in each ras
block could pay no attention to the structure type
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
drivers/gpu/drm/amd/amdgpu/g
some refinements for RAS, no functional change:
1. make more ras code can be reusable among different generations of ras
block;
2. make some ras code simpler;
Tao Zhou (21):
drm/amdgpu: update parameter of ras_ih_cb
drm/amdgpu: move umc ras irq functions to umc block
drm/amdgpu: move gfx ec
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