Re: [PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals

Am 03.10.19 um 22:18 schrieb Davidlohr Bueso: > The amdgpu_vm interval tree really wants [a, b) intervals, NAK, we explicitly do need an [a, b[ interval here. Regards, Christian. > not fully closed ones. As such convert it to use the new > interval_tree_gen.h, and also rename the 'last' endpoint

Re: [PATCH] drm/amdgpu: user pages array memory leak fix

I've tested applying v2 of this patch against a v5.3 tagged kernel and it appears to fix the issue I reported. Thanks, -Joe On Thu, Oct 3, 2019 at 12:07 PM Yang, Philip wrote: > user_pages array should be freed regardless if user pages are > invalidated after bo is created because HMM change to

[PATCH] drm/amdgpu: Use the ALIGN() macro

Use the ALIGN() macro to set "num_dw" to a multiple of 8, i.e. lower 3 bits cleared. Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/

re: drm/amd/display: Add HDCP module - static analysis bug report

Hi, Static analysis with Coverity has detected a potential issue with function validate_bksv in drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c with recent commit: commit ed9d8e2bcb003ec94658cafe9b1bb3960e2139ec Author: Bhawanpreet Lakha Date: Tue Aug 6 17:52:01 2019 -0400 drm/

[PATCH 1/1] drm/amdgpu: Fix error handling in amdgpu_ras_recovery_init

Don't set a struct pointer to NULL before freeing its members. It's hard to see what's happening due to a local pointer-to-pointer data aliasing con->eh_data. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[PATCH][next] drm/amdgpu: fix uninitialized variable pasid_mapping_needed

From: Colin Ian King The boolean variable pasid_mapping_needed is not initialized and there are code paths that do not assign it any value before it is is read later. Fix this by initializing pasid_mapping_needed to false. Addresses-Coverity: ("Uninitialized scalar variable") Fixes: 6817bf283b2

[PATCH][next] drm/amdgpu: remove redundant variable r and redundant return statement

From: Colin Ian King There is a return statement that is not reachable and a variable that is not used. Remove them. Addresses-Coverity: ("Structurally dead code") Fixes: de7b45babd9b ("drm/amdgpu: cleanup creating BOs at fixed location (v2)") Signed-off-by: Colin Ian King --- drivers/gpu/drm

[PATCH v3] drm/amd/display: fix struct init in update_bounding_box

dcn20_resource.c:2636:9: error: missing braces around initializer [-Werror=missing-braces] struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0}; ^ Fixes: 7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by: Raul E Rangel

[PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals

The amdgpu_vm interval tree really wants [a, b) intervals, not fully closed ones. As such convert it to use the new interval_tree_gen.h, and also rename the 'last' endpoint in the node to 'end', which is both a more suitable name for the half closed interval and also reduces the chances of missing

[PATCH] drm/amdgpu: user pages array memory leak fix

user_pages array should always be freed after validation regardless if user pages are changed after bo is created because with HMM change parse bo always allocate user pages array to get user pages for userptr bo. Don't need to get user pages while creating uerptr bo because user pages will only b

[PATCH] drm/amdgpu: user pages array memory leak fix

user_pages array should be freed regardless if user pages are invalidated after bo is created because HMM change to always allocate user pages array to get user pages while parsing user page bo. Don't need to to get user pages while creating bo because user pages will only be used after parsing us

Re: [Follow-up] Status of AMD Sensor Fusion HUB for Linux

On Wed, Oct 2, 2019 at 3:35 AM Luya Tshimbalanga wrote: > > > On 2019-09-26 10:03 a.m., Alex Deucher wrote: > > On Thu, Sep 26, 2019 at 3:59 AM Luya Tshimbalanga > > wrote: > >> Hello, > >> > >> What is the current status of the driver or module for AMD Sensor Fusion > >> HUB for mobile Raven Rid

Re: [PATCH] drm/amdgpu: improve MSI-X handling (v3)

Looks good to me . Reviewed-by: Shaoyun liu On 2019-10-03 1:33 p.m., Tom St Denis wrote: Tested-by: Tom St Denis Cheers, Tom On Thu, Oct 3, 2019 at 1:30 PM Alex Deucher wrote: Check the number of sup

Re: [PATCH] drm/amdgpu: improve MSI-X handling (v3)

Tested-by: Tom St Denis Cheers, Tom On Thu, Oct 3, 2019 at 1:30 PM Alex Deucher wrote: > Check the number of supported vectors and fall back to MSI if > we return or error or 0 MSI-X vectors. > > v2: only allocate one vector. We can't currently use more than > one anyway. > > v3: install the

[PATCH] drm/amdgpu: improve MSI-X handling (v3)

Check the number of supported vectors and fall back to MSI if we return or error or 0 MSI-X vectors. v2: only allocate one vector. We can't currently use more than one anyway. v3: install the irq on vector 0. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 +++

Re: [PATCH][drm-next] drm/amd/display: fix spelling mistake AUTHENICATED -> AUTHENTICATED

On Thu, Oct 3, 2019 at 9:27 AM Harry Wentland wrote: > > On 2019-10-03 4:22 a.m., Colin King wrote: > > From: Colin Ian King > > > > There is a spelling mistake in the macros H1_A45_AUTHENICATED and > > D1_A4_AUTHENICATED, fix these by adding the missing T. > > > > Signed-off-by: Colin Ian King

RE: [PATCH 1/2] drm/amdgpu: improve MSI-X handling

Series are Reviewed-by: Huang Rui -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Thursday, October 3, 2019 10:13 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 1/2] drm/amdgpu: improve MSI-X handling Check the number of supported vectors a

[PATCH 10/11] drm/amd/display: Refactor HDCP encryption status update

[Why] The old way was to poll PSP and update the properties. But due to a limitation in the PSP interface this doesn't work for MST. [How] According to PSP if set_encryption return success, the link is encrypted and the only way it will not be is if we get a link loss(which we handle already). So

[PATCH 11/11] drm/amd/display: fix events handling for hdcp

[Why] When we execute a event, pending events should be canceled. This leads to cases where we execute the same event twice,if the new event is scheduled to run before the old event. Also watchdog event was being canceled inside callback event. This is incorrect. [How] Cancel pending events befor

[PATCH 04/11] drm/amd/display: Add logging for HDCP2.2

[Why] We need to log the state changes for 2.2 This patch extends the existing logging functions to handle HDCP2.2. [How] We do this by adding if/else in the defines, and output the log based on the hdcp version Signed-off-by: Bhawanpreet Lakha --- .../drm/amd/display/modules/hdcp/hdcp_log.c

[PATCH 07/11] drm/amd/display: Handle hdcp2.2 type0/1 in dm

[Why] HDCP 2.2 uses type0 and type1 content type. This is passed to the receiver to stream the proper content. For example, in a MST case if the main device is HDCP2.2 capable but the secondary device is only 1.4 capabale we can use Type0 Type0 content: use HDCP 1.4 or HDCP2.2 type0 Type1 content

[PATCH 08/11] drm/amd/display: Refactor HDCP to handle multiple displays per link

[Why] We need to do this to support HDCP over MST Currently we save a display per link, in a MST case we need to save multiple displays per link. [How] We can create an array per link to cache the displays, but it complicates the design. Instead we can use the module to cache the displays. Now w

[PATCH 06/11] drm/amd/display: Enable HDCP 2.2

[Why] HDCP 2.2 was disabled, we need to enable it [How] -Update display topology to support 2.2 -Unset hdcp2.disable in update_config -Change logic of event_update_property, now we set the property to be ENABLED for any level of encryption (2.2 or 1.4). Signed-off-by: Bhawanpreet Lakha --- driv

[PATCH 09/11] drm/amd/display: add force Type0/1 flag

[Why] Before we had a disable_type1 flag, this forced HDCP 2.2 to type0 There was no way to force type1. [How] Remove disable_type1 flag and instead add a flag to force type0/1. Signed-off-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/a

[PATCH 03/11] drm/amd/display: Add execution and transition states for HDCP2.2

The module works like a state machine +-+ --> | Execution.c | -- | +-+ | | V ++ +

[PATCH 00/11] HDCP 2 Content Protection

Just like with the 1.4 series of patches This only introduces the ability to authenticate and encrypt the link. These patches by themselves don't constitute a complete and compliant HDCP content protection solution but are a requirement for such a solution. Summary of the changes *Adds 2.2 code to

[PATCH 01/11] drm/amd/display: Add PSP block to verify HDCP2.2 steps

[Why] All the HDCP transactions should be verified using PSP [How] This patch adds the psp calls we need to verify the steps Signed-off-by: Bhawanpreet Lakha --- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 44 ++ .../drm/amd/display/modules/hdcp/hdcp_psp.c | 502 +- .../d

[PATCH 05/11] drm/amd/display: Change ERROR to WARN for HDCP module

[Why] HDCP is a bit finicky so we try it 3 times, this leads to a case where if we fail the first time and pass the second time the error is still shown in dmesg for the first failed attempt. This leads to false positive errors. [How] Change the logging from ERROR to WARNING. Warnings are still s

[PATCH 02/11] drm/amd/display: Add DDC handles for HDCP2.2

[Why] We need these to read and write to aux/i2c, during authentication [How] Create read/write functions for all the steps (Eg, h_prime, paring_info etc) Signed-off-by: Bhawanpreet Lakha --- .../drm/amd/display/modules/hdcp/hdcp_ddc.c | 326 ++ 1 file changed, 326 insertions(

[PATCH] drm/amd/display: Make plane z-pos explicit to userspace

[Why] Many userspace assumes that the DRM plane index indicates the plane z-order, with a lower index being lower depth and a higher index being higher depth. This is currently what we assume in DM. DRM has a zpos plane property to make this explicit to userspace and there are clients that make us

Re: [PATCH 2/2] drm/amdgpu: disable MSI-X on APUs

Thanks Alex and  Tom to catch and  revolve the issue .  I didn't do enough test on original test. We don't need to enable msix  on APU .   The serials is reviewed by shaoyun.liu Regards shaoyun.liu On 2019-10-03 10:13 a.m., Alex Deucher wrote: > Raven claims to support them, but seems to

[PATCH] drm/amdgpu/powerplay: fix typo in mvdd table setup

Polaris and vegam use count for the value rather than level. This looks like a copy paste typo from when the code was adapted from previous asics. I'm not sure that the SMU actually uses this value, so I don't know that it actually is a bug per se. Bug: https://bugs.freedesktop.org/show_bug.cgi?

[PATCH 2/2] drm/amdgpu: disable MSI-X on APUs

Raven claims to support them, but seems to have problems. Stick with MSIs for now on APUs. Tested-by: Tom St Denis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq

[PATCH 1/2] drm/amdgpu: improve MSI-X handling

Check the number of supported vectors and fall back to MSI if we return or error or 0 MSI-X vectors. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

On 03/10/2019 15:12, Deucher, Alexander wrote: > Does some variant of the patch on this thread help? > https://patchwork.freedesktop.org/patch/333068/ Hi Alex, The added condition in this patch is: !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12) || which will evaluate to

Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0

On Thu, Oct 03, 2019 at 06:49:05AM +, Lin, Wayne wrote: > > > > From: Ville Syrjälä > Sent: Wednesday, October 2, 2019 19:58 > To: Lin, Wayne > Cc: dri-de...@lists.freedesktop.org ; > amd-gfx@lists.freedesktop.org ; Li, Sun peng > (Leo) ; Kazlauskas, Nicho

Re: [PATCH][drm-next] drm/amd/display: fix spelling mistake AUTHENICATED -> AUTHENTICATED

On 2019-10-03 4:22 a.m., Colin King wrote: > From: Colin Ian King > > There is a spelling mistake in the macros H1_A45_AUTHENICATED and > D1_A4_AUTHENICATED, fix these by adding the missing T. > > Signed-off-by: Colin Ian King Reviewed-by: Harry Wentland Harry > --- > drivers/gpu/drm/amd/d

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

Does some variant of the patch on this thread help? https://patchwork.freedesktop.org/patch/333068/ Alex From: amd-gfx on behalf of Pelloux-prayer, Pierre-eric Sent: Thursday, October 3, 2019 4:25 AM To: Koenig, Christian ; amd-gfx@lists.freedesktop.org Subje

Re: [PATCH v2 00/14] DSC MST support for AMDGPU

On Tue, 01 Oct 2019, wrote: > This set of patches is a continuation of DSC enablement > patches for AMDGPU. This set enables DSC on MST. It also > contains implementation of both encoder and connector > atomic check routines. Please consider *not* using git send-email --chain-reply-to option (or

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

Am 03.10.2019 10:25 schrieb "Pelloux-prayer, Pierre-eric" : On 03/10/2019 10:09, Christian König wrote: > Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric: >> This can be safely skipped entirely. >> This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. > > NAK, pl

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

On 03/10/2019 10:09, Christian König wrote: > Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric: >> This can be safely skipped entirely. >> This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. > > NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least s

[PATCH][drm-next] drm/amd/display: fix spelling mistake AUTHENICATED -> AUTHENTICATED

From: Colin Ian King There is a spelling mistake in the macros H1_A45_AUTHENICATED and D1_A4_AUTHENICATED, fix these by adding the missing T. Signed-off-by: Colin Ian King --- drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h | 4 ++-- .../drm/amd/display/modules/hdcp/hdcp1_execution.c |

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric: This can be safely skipped entirely. This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least some NOP in the submitted IBs. Christian. Signed-

[PATCH] drm/amdgpu: do not execute 0-sized IBs

This can be safely skipped entirely. This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c