Ping
Best wishes
Emily Deng
>-Original Message-
>From: Emily Deng
>Sent: Wednesday, October 9, 2019 6:52 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH] SWDEV-206718 drm/amdgpu: Fix tdr3 could hang with slow
>compute issue
>
>When index is 1, need to set
Enable runtime VCN DPM on/off on Arcturus.
Change-Id: Ie7d94d67cb4c622c96acced1b5ef0f4e63db5aad
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c| 7 +
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30
2 files changed, 37 insertions(+)
diff
this helps to know whether the pptable is from firmware or vbios
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index
On Fri, Oct 11, 2019 at 7:23 PM Tuikov, Luben wrote:
>
> On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> > From: "Tianci.Yin"
> >
> > memory training using specific fixed vram segment, reserve these
> > segments before anyone may allocate it.
> >
> > Change-Id:
On Fri, Oct 11, 2019 at 6:53 PM Tuikov, Luben wrote:
>
> On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> > From: "Tianci.Yin"
> >
> > add new vram_reserve_block structure and atomfirmware_internal_constants
> > enumeration
> >
> > Change-Id: I6ba642ecd7ad94250162ae5c322ed8d85de9c35a
> >
On Fri, Oct 11, 2019 at 6:34 AM Kenneth Feng wrote:
>
> Bug fix for pcie paramerers override on swsmu.
> Below is a scenario to have this problem.
> pptable definition on pcie dpm:
> 0 -> pcie gen speed:1, pcie lanes: *16
> 1 -> pcie gen speed:4, pcie lanes: *16
> Then if we have a system only
Thanks. I'll make note of this in the commit message.
On Fri, Oct 11, 2019 at 9:42 PM Quan, Evan wrote:
>
> Thanks for the clarification. That will be fine then.
> Reviewed-by: Evan Quan
>
> -Original Message-
> From: Alex Deucher
> Sent: Friday, October 11, 2019 9:25 PM
> To: Quan,
Thanks for the clarification. That will be fine then.
Reviewed-by: Evan Quan
-Original Message-
From: Alex Deucher
Sent: Friday, October 11, 2019 9:25 PM
To: Quan, Evan
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: Re: [PATCH 2/5] drm/amdgpu: move gpu reset out of
On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> add memory training implementation code to save resume time.
>
> Change-Id: I625794a780b11d824ab57ef39cc33b872c6dc6c9
> Reviewed-by: Alex Deucher
> Signed-off-by: Tianci.Yin
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h |
On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> memory training using specific fixed vram segment, reserve these
> segments before anyone may allocate it.
>
> Change-Id: I1436755813a565608a2857a683f535377620a637
> Reviewed-by: Alex Deucher
> Signed-off-by: Tianci.Yin
>
On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> parse firmware to get memory training capability and fb location.
>
> Change-Id: I147c1d48e255e0191be4beb1ad6b637da607bf75
> Reviewed-by: Alex Deucher
> Signed-off-by: Tianci.Yin
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h
On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> add new vram_reserve_block structure and atomfirmware_internal_constants
> enumeration
>
> Change-Id: I6ba642ecd7ad94250162ae5c322ed8d85de9c35a
> Reviewed-by: Alex Deucher
> Signed-off-by: Tianci.Yin
> ---
>
On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> add a generic helper function for accessing framebuffer via MMIO
>
> Change-Id: I4baa0aa53c93a94c2eff98c6211a61f369239982
> Reviewed-by: Alex Deucher
> Signed-off-by: Tianci.Yin
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h
On 2019-10-11 12:26 p.m., Nicholas Kazlauskas wrote:
> [Why]
> We're leaking memory by not freeing the gamma used to calculate the
> transfer function for legacy gamma.
>
> [How]
> Release the gamma after we're done with it.
>
> Cc: Philip Yang
> Cc: Harry Wentland
> Cc: Bhawanpreet Lakha
>
From: Ahzo
This fixes kernel NULL pointer dereferences on shutdown:
RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]
Signed-off-by: Ahzo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8
1 file changed, 4 insertions(+), 4
We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8
1 file changed, 4 insertions(+), 4
a little late but: i915 does have this hack (or rather-possible_crtcs with MST
in i915 has been broken for a while and got fixed, but had to get reverted
because of this issue), it's where this originally came from.
On Wed, 2019-10-09 at 17:01 +0200, Daniel Vetter wrote:
> On Fri, Sep 27, 2019 at
Series is
Reviewed-by: Roman Li
-Original Message-
From: amd-gfx On Behalf Of Bhawanpreet
Lakha
Sent: Friday, October 11, 2019 3:53 PM
To: amd-gfx@lists.freedesktop.org
Cc: Berthe, Abdoulaye
Subject: [PATCH 01/29] drm/amd/display: update register field access mechanism
From:
The values for bounding box and res_caps were incorrect. So
Fix them
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++-
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
From: Eric Yang
[Why]
Renoir is gfx9, same as dcn10, not dcn20.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
From: joseph gravenor
[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of
the 0th table
of that is identical to the corrisponding value of MP0_BASE in the renoir
offset header file.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h| 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
index
Use requested_dispclk_khz / 1000 directly
Signed-off-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
From: Dmytro Laktyushkin
Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to
Handle 18 DecimalBPP like other cases
Signed-off-by: Bhawanpreet Lakha
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
it allows us to do urgent latency programming
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 16
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 39 +--
.../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17
From: Dmytro Laktyushkin
Renoir can use vm contexes as long as HOSTVM is off so
this should be initialized.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi all,
There was a delta betwwen internal dcn21 code and upstream dcn21 code.
These changes bring them inline.
Summary of Changes
*Add RN registors
*Add dcn12 hwseq and link_encoder
*RN specific fixes
*aux timeout support
*bounding box changes
v2:
*add usb-c functions
*compile
From: Lewis Huang
[why]
driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box
[How]
Move the patch function before calculate wm.
Signed-off-by: Lewis Huang
Signed-off-by: joseph graveno
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 25
From: Dmytro Laktyushkin
1 vmid limitation only exists for HOSTVM which is a custom
use case anyway.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: abdoulaye berthe
[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14
From: Lewis Huang
[Why]
Watermarks not propagated to DCHUBP after it is powered on
[How]
Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
[Why]
DCN20 and DCN21 have different phy programming sequences.
[How]
Create a separate dcn21_link_encoder for Renoir
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +-
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 +
Detile buffer size affects dcc caps, it was already added for
dcn2. Now add it for dcn21
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
DPM level is 8 these were incorrect before. Fix them
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
This patch adds handling of dp is usb-c, it is not tested but is
needed to support dp over usb-c
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 14 +++
.../amd/display/dc/dcn21/dcn21_link_encoder.c | 93 ++-
From: Eric Yang
[Why]
Handle the case where we don't get a valid table. Also fixes compiler
warning for variable potentially used before assignment.
[How]
If the entire table has no valid fclk, reject the table and use our own
hard code.
Signed-off-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/include/renoir_ip_offset.h| 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
index 094648cac392..07633e22e99a 100644
---
From: Michael Strauss
[WHY]
dprefclk is improperly read due to incorrect units used.
Causes an audio clock to be improperly set, making audio
non-functional and videos play back too fast
[HOW]
Scale dprefclk value from MHz to KHz (multiply by 1000)
to ensure that dprefclk_khz is in correct
use dcn20 common regs define to share some regs with dcn20
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
Incorrect page table address and programming sys aperture for
stutter gather, so fix it.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 23 ++-
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git
From: Sung Lee
[Why]
Previously only dummy functions were added in Diags for FPGA.
On silicon, this would lead to a segmentation fault on silicon diags.
[How]
Check if diags silicon and if so, add dummy functions.
Signed-off-by: Sung Lee
Acked-by: Bhawanpreet Lakha
---
From: Roman Li
[Why]
Earlier changes to support configurable aux timeout
caused dc init failure on vega due to missing reg defs.
Needs to be disabled until implemented for vega.
[How]
Set extended aux timeout cap for vega to false.
fixes: drm/amd/display: configurable aux timeout support
From: Dmytro Laktyushkin
Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 40
From: abdoulaye berthe
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family
Signed-off-by: abdoulaye berthe
Acked-by: Bhawanpreet Lakha
---
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index
This change adds renoir hw_seq, needed to do renoir
specific hw programing
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
From: Lewis Huang
[Why]
SMU fixed this issue after version 0x370c00
[How]
enable smu send message to set dcfclk after smu version 0x370c00
Signed-off-by: Lewis Huang
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4 ++--
1 file changed, 2
Hi Harry,
Do you need more information ?
Thx
Julien
On Tue, Oct 8, 2019 at 11:15 AM Julien Isorce
wrote:
> Hi Harry,
>
> I can reproduce on LG, Samsung and NEC monitors.
>
> "Have you checked whether the driver picks RGB or YCBCR420 without your
> patch?" -> it was selecting RGB .
>
> For
On 2019-10-11 1:33 p.m., Kuehling, Felix wrote:
> On 2019-10-11 10:36 a.m., Yang, Philip wrote:
>> user_pages array should always be freed after validation regardless if
>> user pages are changed after bo is created because with HMM change parse
>> bo always allocate user pages array to get user
On 2019-10-11 10:36 a.m., Yang, Philip wrote:
> user_pages array should always be freed after validation regardless if
> user pages are changed after bo is created because with HMM change parse
> bo always allocate user pages array to get user pages for userptr bo.
>
> v2: remove unused local
Hello, Daniel.
On Wed, Oct 09, 2019 at 06:06:52PM +0200, Daniel Vetter wrote:
> That's not the point I was making. For cpu cgroups there's a very well
> defined connection between the cpu bitmasks/numbers in cgroups and the cpu
> bitmasks you use in various system calls (they match). And that
I'm pleased to announce the 19.1.0 release of xf86-video-amdgpu, the
Xorg driver for AMD Radeon GPUs supported by the amdgpu kernel driver.
This release supports xserver versions 1.13-1.20.
There are no big changes in this release, just fixes and other minor
improvements.
Thanks to everybody
Thanks for the patches.
I think for all of them we should just drop the REG_READ calls
completely. They look like leftovers from when we had a different
register update scheme that would read the register, then update or get
the field value. Now we just use the REG_ macros that will combine the
[Why]
We're leaking memory by not freeing the gamma used to calculate the
transfer function for legacy gamma.
[How]
Release the gamma after we're done with it.
Cc: Philip Yang
Cc: Harry Wentland
Cc: Bhawanpreet Lakha
Cc: Leo Li
Signed-off-by: Nicholas Kazlauskas
---
Series is
Acked-by: Harry Wentland
Harry
On 2019-10-09 5:05 p.m., Bhawanpreet Lakha wrote:
> Hi all,
>
> There was a delta betwwen internal dcn21 code and upstream dcn21 code.
> These changes bring them inline.
>
>
> Summary of Changes
> *Add RN registors
> *Add dcn12 hwseq and link_encoder
user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.
v2: remove unused local variable and amend commit
v3: add back get user pages in
> -Original Message-
> From: amd-gfx On Behalf Of
> Hersen Wu
> Sent: Thursday, October 10, 2019 10:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wu, Hersen ; Wang, Kevin(Yang)
> ; Wentland, Harry
> Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
>
> there are
On 2019-10-10 11:10 a.m., Alex Deucher wrote:
> Use the dcn21 functions in dcn21_resource.c and make the
> dcn20 functions static since they are only used in
> dcn20_resource now.
>
> Cc: bhawanpreet.la...@amd.com
> Signed-off-by: Alex Deucher
Reviewed-by: Harry Wentland
Harry
> ---
>
On 2019-10-11 4:40 a.m., Christian König wrote:
> Am 03.10.19 um 21:44 schrieb Yang, Philip:
>> user_pages array should always be freed after validation regardless if
>> user pages are changed after bo is created because with HMM change parse
>> bo always allocate user pages array to get user
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Le Ma
Sent: 2019年10月11日 19:10
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: [PATCH 1/4] drm/amdgpu/soc15: disable doorbell interrupt as part of
BACO entry sequence
Workaround
Series is:
Reviewed-by: Alex Deucher
On Fri, Oct 11, 2019 at 7:10 AM Le Ma wrote:
>
> BACO reset is needed for RAS recovery.
>
> Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
> Signed-off-by: Le Ma
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
> 1 file changed, 3
On Thu, Oct 10, 2019 at 10:50 PM Dennis Li wrote:
>
> Add codes to query the EDC count of VML2 & ATCL2
>
> Change-Id: If2c251481ba0a1a34ce3405a85f86d65eecee461
> Signed-off-by: Dennis Li
Series is:
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 167
Reviewed-by: Kevin Wang
From: Feng, Kenneth
Sent: Thursday, October 10, 2019 3:00 PM
To: Yuan, Xiaojie ; Deucher, Alexander
; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan
Subject: RE: [PATCH 2/2]
Acked-by: Alex Deucher
From: Yuan, Xiaojie
Sent: Friday, October 11, 2019 4:20 AM
To: Deucher, Alexander ; Feng, Kenneth
; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ;
Zhang, Hawking ; Quan, Evan
Subject: Re: [PATCH 2/2]
it looks fine for me.
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: Hersen Wu
Sent: Thursday, October 10, 2019 10:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Wang, Kevin(Yang)
; Wu, Hersen
Subject: [PATCH] drm/amdgpu/powerplay: add
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Friday, October 11, 2019 12:09 AM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com ; Xiao, Jack
; Yuan, Xiaojie ; Zhang, Hawking
Subject: [PATCH v2] drm/amdgpu/discovery:
On Fri, Oct 11, 2019 at 5:27 AM Hans de Goede wrote:
>
> Hi,
>
> On 10-10-2019 18:59, Daniel Vetter wrote:
> > On Thu, Oct 10, 2019 at 6:28 PM Hans de Goede wrote:
> >>
> >> Bail from the pci_driver probe function instead of from the drm_driver
> >> load function.
> >>
> >> This avoid
On Fri, Oct 11, 2019 at 12:07 AM Quan, Evan wrote:
>
> It seems amdgpu_pmops_runtime_suspend() needs to be updated accordingly also.
I purposely left that out. I think that is a bug. We don't need to
reset the GPU for runtime suspend. We only need it for hibernation
because of the whole
Hi,
On 10-10-2019 18:59, Daniel Vetter wrote:
On Thu, Oct 10, 2019 at 6:28 PM Hans de Goede wrote:
Bail from the pci_driver probe function instead of from the drm_driver
load function.
This avoid /dev/dri/card0 temporarily getting registered and then
unregistered again, sending unwanted add
Workaround to make RAS recovery work in BACO reset.
Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 8
drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
3
1 indicates RAS recovery flag in SMU FW.
Change-Id: Icb8c14586fca1b8ae443bbde764570a9e41850fa
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.
Change-Id: I2a82c128fa5e9731b886dd61f1273dc48ea1923c
Signed-off-by: Le Ma
---
BACO reset is needed for RAS recovery.
Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will
Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will
Am 11.10.19 um 03:21 schrieb Alex Deucher:
This patch set enables BACO CI and VI asics. BACO is
Bus Active Chip Off. It allows us to turn off the GPU
while still keeping the bus interface up, so the device
does not disappear from the system. PowerXpress and
Hybrid Graphics laptops support
Good catch! Reviewed-by: Christian König
Am 09.10.19 um 19:11 schrieb Deucher, Alexander:
Reviewed-by: Alex Deucher
*From:* amd-gfx on behalf of
Yuan, Xiaojie
*Sent:* Wednesday, October 9, 2019 1:09 PM
*To:*
Series is reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, October 11, 2019 9:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 15/15] drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2)
Use BACO to reset
Am 03.10.19 um 21:44 schrieb Yang, Philip:
user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.
Don't need to get user pages while
Hi there,
Could someone give an RB or ACK? This patch has been verified on both navi12
and navi14.
Thanks.
BR,
Xiaojie
From: Deucher, Alexander
Sent: Thursday, October 10, 2019 8:20 PM
To: Feng, Kenneth ; Yuan, Xiaojie ;
amd-gfx@lists.freedesktop.org
Cc:
Forwarding to the appropriate display folks.
Can you guys take a look?
Christian.
Am 11.10.19 um 01:34 schrieb Gabriel C:
> Hello,
>
> I've built recently a new box with a Ryzen3 2200G APU.
>
> Each time I plug in an HDMI cable ( to a TV or Monitor ),
> or boot with HDMI connected a lot
On Thu, Oct 10, 2019 at 02:44:29PM -0500, KyleMahlkuch wrote:
> During kexec some adapters hit an EEH since they are not properly
> shut down in the radeon_pci_shutdown() function. Adding
> radeon_suspend_kms() fixes this issue.
> Enabled only on PPC because this patch causes issues on some other
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