From: changzhu
It may cause timeout waiting for sem acquire in VM flush when using
invalidate semaphore for picasso. So it needs to avoid using invalidate
semaphore for piasso.
Change-Id: I193e6a9eecc0a8b2c99baabf18ad816fb473da52
Signed-off-by: changzhu
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0
From: changzhu
It may fail to load guest driver in round 2 when using invalidate
semaphore for SRIOV. So it needs to avoid using invalidate semaphore for
SRIOV.
Fix for:http://ontrack-internal.amd.com/browse/SWDEV-214157
Change-Id: I1e498d33df2f8a53dbbec7a28672085cea68acb8
Signed-off-by: changz
issue unload_ta_cmd to tOS to unload asd driver
Change-Id: I697cfc1774205ed6cbe22eb3c16143b603543564
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/
asd shared memory is not needed since drivers doesn't
invoke any further cmd to asd directly after the asd
loading. trust application is the one who needs
to talk to asd after the initialization
Change-Id: I728afa4c7e8b67bc06678b10e92ac064ba10173e
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm
Platform TAs will independently toggle DF Cstate.
for instance, get/set topology from xgmi ta. do error
injection from ras ta. In such case, PMFW needs to be
loaded before TAs so that all the subsequent Cstate
calls recieved by PSP FW can be routed to PMFW.
Change-Id: I83db1a22577a84ae647e7e570c20
[Why]
If the payload_state is DP_PAYLOAD_DELETE_LOCAL in series, current
code doesn't delete the payload at current index and just move the
index to next one after shuffling payloads.
[How]
After shuffling payloads, decide whether to move on index or not
according to payload_state of current paylo
[Why]
While disabling mst topology manager in
drm_dp_mst_topology_mgr_set_mst(), now just reset the mgr->payloads
but doesn't handle the mgr->proposed_vcpis.
[How]
Remove mgr->proposed_vcpis to NULL.
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/drm_dp_mst_topology.c | 12
1 file ch
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, November 29, 2019 11:09 PM
> To: Lin, Wayne
> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH V2 1/2] drm/edid: Add aspect ratios to HDMI 4K modes
>
> On Mon, Nov 18, 2019 at 06:18:31PM
On Sat, Nov 30, 2019 at 10:03 AM Linus Torvalds
wrote:
>
> I'll try to figure the code out, but my initial reaction was "yeah,
> not in my VM".
Why is it ok to sometimes do
WRITE_ONCE(mni->invalidate_seq, cur_seq);
(to pair with the unlocked READ_ONCE), and sometimes then do
mni->inval
I just realized that at 4:2:2, the pixel clock isn't actually decreased to 3/4
of it's value at 4:4:4. I'll send a revised patch on Monday.
On Fri, Nov 22, 2019 at 09:29:00PM -0800, Thomas Anderson wrote:
> For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
> formats like YCbCr444
On Mon, Nov 25, 2019 at 12:42 PM Jason Gunthorpe wrote:
>
> Here is this batch of hmm updates, I think we are nearing the end of this
> project for now, although I suspect there will be some more patches related to
> hmm_range_fault() in the next cycle.
I've ended up pulling this, but I'm not ent
On Mon, Nov 25, 2019 at 12:42 PM Jason Gunthorpe wrote:
>
> You will probably be most interested in the patch "mm/mmu_notifier: add an
> interval tree notifier".
I'm trying to read that patch, and I'm completely unable to by the
absolutely *horrid* variable names.
There are zero excuses for name
On 2019-11-11 07:35, Kazlauskas, Nicholas wrote:
On 2019-11-10 7:00 p.m., Subsentient wrote:
Hi, I've been experiencing a bug on kernels 5.2 and up that
apparently is uncommon and/or unimportant enough to have both threads
mentioning it die.
On a Ryzen 3 2200G, the amdgpu driver fails upon li
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