RE: [PATCH] drm/amdgpu: simplify function return logic

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Le Ma -Original Message- From: Chen, Guchun Sent: Tuesday, December 24, 2019 2:33 PM To: Zhou1, Tao ; Zhang, Hawking ; Ma, Le ; amd-gfx@lists.freedesktop.org Cc: Chen, Guchun Subject: [PATCH] drm/amdgpu: simplify

polaris12_mc.bin error

Hello, I just compiled my 4.19 kernel with amdgpu driver (amdgpu as builtin). The driver is giving me -2 error because of polaris12_mc.bin did not found. I couldn't find that file anywhere. How can i get polaris12_mc.bin and where should I place it ? *Dmesg:* [5.425323] [drm] amdgpu kernel

[PATCH] drm/amdgpu: simplify function return logic

Former return logic is redundant. Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index bb701dbfd472..41af6d0801d9

RE: [PATCH] drm/amd/powerplay free driver_pptable for smu reinit

-Original Message- From: Jack Zhang Sent: Tuesday, December 24, 2019 1:05 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Jack (Jian) Subject: [PATCH] drm/amd/powerplay free driver_pptable for smu reinit During gpu recover, smu hw reinit will fail becasue

RE: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF

Hi, Kevin, Thank you for your code review. 1. I updated the patch to refine pm_enbable logic (attached). 1. For the following comments. “* Copy pptable bo in the vram…”, it is the original bare-metal comments. I didn’t change it. 1. “could you describe the function of pp_one_vf and

Re: [PATCH v3] drm/amd/display: Fix AppleDongle can't be detected

On Tue, Dec 17, 2019 at 10:57:11AM -0500, Harry Wentland wrote: > On 2019-12-11 2:33 a.m., Louis Li wrote: > > [Why] > > External monitor cannot be displayed consistently, if connecting > > via this Apple dongle (A1621, USB Type-C to HDMI). > > Experiments prove that the dongle needs 200ms at

RE: [PATCH] drm/amd/powerplay: support custom power profile setting

> -Original Message- > From: Alex Deucher > Sent: Tuesday, December 24, 2019 3:35 AM > To: Quan, Evan > Cc: amd-gfx list > Subject: Re: [PATCH] drm/amd/powerplay: support custom power profile > setting > > On Mon, Dec 23, 2019 at 3:05 AM Evan Quan wrote: > > > > Support custom

RE: [PATCH] drm/amdgpu/smu: make the set_performance_level logic easier to follow

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Tuesday, December 24, 2019 3:54 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/smu: make the set_performance_level logic > easier to follow >

RE: [PATCH] Revert "drm/amdgpu: simplify ATPX detection"

Acked-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Saturday, December 21, 2019 8:12 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] Revert "drm/amdgpu: simplify ATPX detection" > > This reverts commit

Re: [PATCH] drm/amd/display: Don't disable DP PHY when link loss happens

On 2019-12-23 3:46 p.m., Zhan Liu wrote: > [Why] > There is a use case that link loss happens accidentally, > and we need to recover that link loss as soon as possible. > Under this circumstance, DP PHY will perform link training, > then try to recover the link that's just lost. > > However, if

[PATCH] drm/amd/display: Don't disable DP PHY when link loss happens

[Why] There is a use case that link loss happens accidentally, and we need to recover that link loss as soon as possible. Under this circumstance, DP PHY will perform link training, then try to recover the link that's just lost. However, if link PHY is disabled by code here, then DP display will

[PATCH] drm/amdgpu/smu: make the set_performance_level logic easier to follow

Have every asic provide a callback for this rather than a mix of generic and asic specific code. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 44 +-- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 +

Re: [PATCH 3/5] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd

[AMD Official Use Only - Internal Distribution Only] True. There indeed are two vmhubs on Navi. So my two comments are not useful here. Yong From: Kuehling, Felix Sent: Monday, December 23, 2019 2:34 PM To: Zhao, Yong ; Sierra Guiza, Alejandro (Alex) ;

Re: [PATCH 0/5] drm/amdgpu: use true,false for bool variable

On Mon, Dec 23, 2019 at 10:26 AM zhengbin wrote: > > zhengbin (5): > drm/amdgpu: use true,false for bool variable in mxgpu_ai.c > drm/amdgpu: use true,false for bool variable in mxgpu_nv.c > drm/amdgpu: use true,false for bool variable in amdgpu_device.c > drm/amdgpu: use true,false for

Re: [PATCH 0/7] drm/radeon: use true,false for bool variable

On Mon, Dec 23, 2019 at 10:26 AM zhengbin wrote: > > zhengbin (7): > drm/radeon: use true,false for bool variable in r100.c > drm/radeon: use true,false for bool variable in si.c > drm/radeon: use true,false for bool variable in r600.c > drm/radeon: use true,false for bool variable in

Re: [PATCH] drm/amd/powerplay: support custom power profile setting

On Mon, Dec 23, 2019 at 3:05 AM Evan Quan wrote: > > Support custom power profile mode settings on Arcturus. > > Change-Id: Id14f9a1cced41433b7487f447c452f8852964891 > Signed-off-by: Evan Quan > --- > drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 132 +- >

Re: [PATCH 3/5] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd

On 2019-12-20 7:01 p.m., Yong Zhao wrote: On 2019-12-20 6:50 p.m., Yong Zhao wrote: Inline. On 2019-12-20 4:35 p.m., Felix Kuehling wrote: On 2019-12-20 1:24, Alex Sierra wrote: [Why] TLB flush method has been deprecated using kfd2kgd interface. This implementation is now on the

Re: [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors

On 12/20/19 4:41 PM, Lyude Paul wrote: So I reviewed this already but realized I made a very silly mistake, comments down below: On Fri, 2019-12-13 at 15:08 -0500, mikita.lip...@amd.com wrote: From: Mikita Lipski [why] Since for DSC MST connector's PBN is claculated differently due to

Re: [PATCH] Revert "drm/amdgpu: simplify ATPX detection"

Ping? On Fri, Dec 20, 2019 at 7:11 PM Alex Deucher wrote: > > This reverts commit f5fda6d89afe6e9cedaa1c3303903c905262f6e8. > > You can't use BASE_CLASS in pci_get_class. > > Bug: https://gitlab.freedesktop.org/drm/amd/issues/995 > Signed-off-by: Alex Deucher > --- >

[PATCH 1/7] drm/radeon: use true,false for bool variable in r100.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/r100.c:1826:3-31: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:1828:3-31: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:2390:2-22: WARNING: Assignment of 0/1 to bool variable

Re: INFO: task hung in fb_release

syzbot has bisected this bug to: commit e3933f26b657c341055443103bad331f4537b113 Author: Rex Zhu Date: Tue Jan 16 10:35:15 2018 + drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=12b5a799e0 start

[PATCH 5/5] drm/amdgpu: use true, false for bool variable in amdgpu_psp.c

Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:674:2-26: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:794:1-25: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:897:2-36: WARNING: Assignment of 0/1 to

[PATCH 1/5] drm/amdgpu: use true, false for bool variable in mxgpu_ai.c

Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:253:2-20: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:265:2-20: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin ---

[PATCH 5/7] drm/radeon: use true,false for bool variable in rv770.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/rv770.c:1706:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin --- drivers/gpu/drm/radeon/rv770.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 4/5] drm/amdgpu: use true, false for bool variable in amdgpu_debugfs.c

Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:132:2-10: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:140:2-10: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:142:13-21: WARNING:

[PATCH 7/7] drm/radeon: use true,false for bool variable in ni.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/ni.c:2020:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/ni.c:2088:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin --- drivers/gpu/drm/radeon/ni.c | 4 ++-- 1 file

[PATCH 2/5] drm/amdgpu: use true, false for bool variable in mxgpu_nv.c

Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:255:2-20: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:267:2-20: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin ---

[PATCH 2/7] drm/radeon: use true,false for bool variable in si.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/si.c:6475:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/si.c:6542:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin --- drivers/gpu/drm/radeon/si.c | 4 ++-- 1 file

[PATCH 0/5] drm/amdgpu: use true,false for bool variable

zhengbin (5): drm/amdgpu: use true,false for bool variable in mxgpu_ai.c drm/amdgpu: use true,false for bool variable in mxgpu_nv.c drm/amdgpu: use true,false for bool variable in amdgpu_device.c drm/amdgpu: use true,false for bool variable in amdgpu_debugfs.c drm/amdgpu: use true,false

[PATCH 3/5] drm/amdgpu: use true, false for bool variable in amdgpu_device.c

Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3961:1-19: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3981:1-19: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin ---

[PATCH 3/7] drm/radeon: use true,false for bool variable in r600.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/r600.c:3056:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin --- drivers/gpu/drm/radeon/r600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/r600.c

[PATCH 4/7] drm/radeon: use true, false for bool variable in evergreen.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/evergreen.c:4948:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin --- drivers/gpu/drm/radeon/evergreen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 6/7] drm/radeon: use true,false for bool variable in cik.c

Fixes coccicheck warning: drivers/gpu/drm/radeon/cik.c:8140:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/cik.c:8212:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot Signed-off-by: zhengbin --- drivers/gpu/drm/radeon/cik.c | 4 ++-- 1 file

[PATCH 0/7] drm/radeon: use true,false for bool variable

zhengbin (7): drm/radeon: use true,false for bool variable in r100.c drm/radeon: use true,false for bool variable in si.c drm/radeon: use true,false for bool variable in r600.c drm/radeon: use true,false for bool variable in evergreen.c drm/radeon: use true,false for bool variable in

Re: [PATCH] drm/amd/display: fix kernel_fpu_begin/_end() warnings

On 2019-12-22 10:22 p.m., Xiaojie Yuan wrote: > kernel_fpu_begin/_end() are already called inside dcn20_resource_construct, > and calling kernel_fpu_begin/_end() recursively triggers WARN_ON() when > CONFIG_X86_DEBUG_FPU is enabled. > > [ 107.060434] WARNING: CPU: 6 PID: 1370 at

Re: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF

[AMD Official Use Only - Internal Distribution Only] add @Quan, Evan to support arcturus asic. comment inline. From: Zhang, Jack (Jian) Sent: Monday, December 23, 2019 4:42 PM To: Feng, Kenneth ; Wang, Kevin(Yang) ; Tao, Yintian ;

RE: [PATCH 2/2] drm/amdgpu: add psp session ID get interface for sriov

[AMD Official Use Only - Internal Distribution Only] Hi Frank, The new function amdgpu_xgmi_get_session_id seems not necessary to me because you just need to delay the xgmi ta loading until IH get initialized. The xgmi session Id will be updated to xgmi_context so it should be okay anytime you

RE: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF

-Original Message- From: Jack Zhang Sent: Monday, December 23, 2019 4:40 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Jack (Jian) Subject: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF Before, initialization of smu ip block would be skipped for sriov ASICs. But if

[PATCH] drm/amd/powerplay: support custom power profile setting

Support custom power profile mode settings on Arcturus. Change-Id: Id14f9a1cced41433b7487f447c452f8852964891 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 132 +- .../powerplay/inc/smu11_driver_if_arcturus.h | 6 +- 2 files changed, 128