Reviewed-by: Evan Quan
> -Original Message-
> From: Kenneth Feng
> Sent: Thursday, January 9, 2020 3:13 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Feng, Kenneth
>
> Subject: [PATCH v2] drm/amd/powerplay: sw ctf for arcturus
>
> change the sw ctf setting to smu_v11_0_set_
change the sw ctf setting to smu_v11_0_set_thermal_range()
since software_shutdown_temp shares the same definition and
name in all the smu11 project.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a
On Wed, Jan 08, 2020 at 05:34:53PM -0500, Alex Deucher wrote:
> All of the sdma stuff these were used for moves to
> the sdma code, so remove them.
>
> Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 -
> 1 file changed, 9 deletions
On Wed, Jan 08, 2020 at 05:49:08PM -0500, Alex Deucher wrote:
> It won't get used unless the driver allows the gtt domain for
> display buffers which is controlled elsewhere.
>
> Signed-off-by: Alex Deucher
Series are Acked-by: Huang Rui
Any suggestion for testing, I would like to give a try i
On Wed, Jan 08, 2020 at 10:16:01PM -0500, Alex Deucher wrote:
> Leftover from bring up. We look up the actual pre-OS memory usage
> value later in the same function.
>
> Signed-off-by: Alex Deucher
Series are Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 9 -
If a user specifies a non-existant sdma instance,
warn and return the offset for instance 0.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arc
On Wed, Jan 8, 2020 at 8:10 PM Guchun Chen wrote:
>
> Hardcoded offset is not friendly. And another benifit of this
> patch is to keep read and write access to this register be
> consistent with other similar UMC regsiters in this file.
>
> Signed-off-by: Guchun Chen
Series is:
Reviewed-by: Ale
the parameter is the mst manager, not the port.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 7e9b9b7e50cf..a4be2f82589
[AMD Public Use]
To address your concerns
1). The SDMA_EDC_COUTNERS will be cleared by HW after the reading. This is a
read-only registers. Either explicitly clear this register or programming
EDC_COUNTER_CLEAR register is unnecessary.
2). The error injection and error reporting are actually se
[AMD Official Use Only - Internal Distribution Only]
Ok, thanks very much Alex!
From: Alex Deucher
Sent: Thursday, January 9, 2020 11:12
To: Yin, Tianci (Rico)
Cc: Christian König ; Koenig, Christian
; Long, Gang ; Wang, Kevin(Yang)
; Xu, Feifei ; amd-gfx list
Leftover from bring up. We look up the actual pre-OS memory usage
value later in the same function.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/am
We don't need to store the pre-OS console memory after
the driver has loaded so free it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
i
On Wed, Jan 8, 2020 at 10:07 PM Yin, Tianci (Rico) wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Thanks Alex and Christian!
>
> Hi Christian,
>
> On ASICs with gmc v10, I find amdgpu_bo_late_init() is not invoked, so stolen
> memory never get free, on other ASICs with gmc
[AMD Official Use Only - Internal Distribution Only]
Thanks Alex and Christian!
Hi Christian,
On ASICs with gmc v10, I find amdgpu_bo_late_init() is not invoked, so stolen
memory never get free, on other ASICs with gmc v9/v8/v7/v6, stolen memory was
freed in gmc_v*_0_late_init(). I don't know
[AMD Official Use Only - Internal Distribution Only]
fine for me.
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Kenneth Feng
Sent: Thursday, January 9, 2020 9:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth
Su
software ctf implementation on arcturs.
has been verified on the system by setting a fake software ctf
temperature limit like 40 degrees centigrade.
then the interrupt is triggered from ih ring and
the warning can be observed from dmesg.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerp
Hardcoded offset is not friendly. And another benifit of this
patch is to keep read and write access to this register be
consistent with other similar UMC regsiters in this file.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 ++
1 file changed, 6 insertions(+
Both are needed on vega20 and arcturus chip.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/
[AMD Public Use]
Two comments in patch 1.
And one more question for the series is, we add SDMA block case in ras query,
but no such case in ras error injection.
Then how we get to know who triggers SDMA ECC counter? Still by the GFX
injecton?
With above concerns fixed/clarified, series is:
Rev
[AMD Public Use]
-Original Message-
From: Hawking Zhang
Sent: Thursday, January 9, 2020 12:17 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Li, Dennis ; Clements, John
; Chen, Guchun ; Zhou1, Tao
; Li, Candice ; Long, Gang
Cc: Zhang, Hawking
Subject: [PATCH 1/4] drm/
Patches 1 & 3 are
Reviewed-by: Harry Wentland
Patch 2 is
Acked-by: Harry Wentland
Harry
On 2020-01-08 5:49 p.m., Alex Deucher wrote:
> It won't get used unless the driver allows the gtt domain for
> display buffers which is controlled elsewhere.
>
> Signed-off-by: Alex Deucher
> ---
> drive
It won't get used unless the driver allows the gtt domain for
display buffers which is controlled elsewhere.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/di
It won't get used unless the driver allows the gtt domain for
display buffers which is controlled elsewhere.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/
It should work on all Raven variants, but some users have
reported issues with original Raven with IOMMU enabled.
So far there have been no issues observed with PCO or RV2.
v2: split out the dm init and domain changes into separate
patches.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/am
All of the sdma stuff these were used for moves to
the sdma code, so remove them.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index
On Wed, Jan 8, 2020 at 5:19 AM Christian König
wrote:
>
> Am 07.01.20 um 22:13 schrieb Alex Deucher:
> > It should work on all Raven variants, but some users have
> > reported issues with original Raven with IOMMU enabled.
> > So far there have been no issues observed with PCO or RV2.
> >
> > Sign
Hi Dave, Daniel,
A few minor fixes for 5.5. This also enables DRIVER_SYNCOBJ_TIMELINE which
has been implemented for ages, but was awaiting Khronos which has since
happened. The relevant amdvlk code is in:
https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/os/amdgpu/amdgpuDevice.cpp
The f
On Wed, Jan 08, 2020 at 01:56:47PM +0100, Christian König wrote:
> Am 07.01.20 um 20:25 schrieb Tianlin Li:
> > Right now several architectures allow their set_memory_*() family of
> > functions to fail, but callers may not be checking the return values.
> > If set_memory_*() returns with an error,
On Wed, Jan 8, 2020 at 12:39 PM Kees Cook wrote:
>
> On Wed, Jan 08, 2020 at 01:56:47PM +0100, Christian König wrote:
> > Am 07.01.20 um 20:25 schrieb Tianlin Li:
> > > Right now several architectures allow their set_memory_*() family of
> > > functions to fail, but callers may not be checking the
On Wed, Jan 8, 2020 at 11:18 AM Hawking Zhang wrote:
>
> SDMA edc counter registers were added in gfx edc counters
> array. When querying gfx error counter in that array, there
> is no way to differentiate sdma instance number for different
> asic and then results to NULL pointer access when tryin
On Wed, Jan 8, 2020 at 11:18 AM Hawking Zhang wrote:
>
> move ras_late_init and ras_fini to sdma_ras_funcs table
>
> Change-Id: If3a6c0defde4d23f81d2ff7ff79daa98a732efde
> Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 3 +++
> driver
On Wed, Jan 8, 2020 at 11:17 AM Hawking Zhang wrote:
>
> query_ras_error_count function will be invoked to query
> single bit error count detected in sdma ip block
>
> Change-Id: I1b17df7c66e71739ae4c31900bd96c5359af2240
> Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
> ---
> drivers
On Wed, Jan 8, 2020 at 11:17 AM Hawking Zhang wrote:
>
> invoke sdma query_ras_error_count to get sdma single
> bit error count
>
> Change-Id: Iaaa86bb79dc28fe714937ca832da8a1cb5541930
> Signed-off-by: Hawking Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++
> 1 file changed, 7
query_ras_error_count function will be invoked to query
single bit error count detected in sdma ip block
Change-Id: I1b17df7c66e71739ae4c31900bd96c5359af2240
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 6 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 163
SDMA edc counter registers were added in gfx edc counters
array. When querying gfx error counter in that array, there
is no way to differentiate sdma instance number for different
asic and then results to NULL pointer access when trying to
read sdma register base address for instances greater
than
move ras_late_init and ras_fini to sdma_ras_funcs table
Change-Id: If3a6c0defde4d23f81d2ff7ff79daa98a732efde
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 3 +++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 --
2 files changed, 7 insertions(+), 2 deletions(-)
d
invoke sdma query_ras_error_count to get sdma single
bit error count
Change-Id: Iaaa86bb79dc28fe714937ca832da8a1cb5541930
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b
Currently, sdma edc counters are grouped in gfx edc counter
registers array (sec_ded_counter_registers), which results
to several issues including:
1). count sdma ras error into gfx ip blocks when querying gfx
error counter (i.e. through sysfs gfx_error_count node).
2). kernel crash (access NULL po
> On Jan 8, 2020, at 6:56 AM, Christian König wrote:
>
> Am 07.01.20 um 20:25 schrieb Tianlin Li:
>> Right now several architectures allow their set_memory_*() family of
>> functions to fail, but callers may not be checking the return values.
>> If set_memory_*() returns with an error, call-site
From: Michael Strauss
[WHY]
Only a single voltage level should be available to Pollock (min level)
Pollock & Dali get misidentified as Renoir, use wrong clk mgr constructor
[HOW]
Add provided Pollock IDs to ASIC Rev. ID list.
Create new Pollock ASIC RID check, fix RV2 & Dali ASIC checks.
Check R
On 2020-01-07 11:05 p.m., Alex Deucher wrote:
> Otherwise we get undefined symbols.
>
> Signed-off-by: Alex Deucher
There is probably a way to reduce some of the DCN guards so this won't
be an issue.
Either way this is
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/display/am
Series is
Reviewed-by: Harry Wentland
Harry
On 2020-01-07 4:13 p.m., Alex Deucher wrote:
> Everything is in place so go ahead and enable this for
> renoir.
>
> Signed-off-by: Alex Deucher
> ---
>
> I don't have a renoir board handy. Can someone test this?
>
> drivers/gpu/drm/amd/amdgpu/amd
Am 08.01.20 um 15:49 schrieb Alex Deucher:
On Wed, Jan 8, 2020 at 7:52 AM Christian König wrote:
Am 08.01.20 um 13:36 schrieb Tianci Yin:
From: "Tianci.Yin"
[why]
In dual GPUs scenario, stolen_size is assigned to zero on the 2nd GPU,
then the bottom region of VRAM was allocated as GTT, unfor
On Wed, Jan 8, 2020 at 7:52 AM Christian König wrote:
>
> Am 08.01.20 um 13:36 schrieb Tianci Yin:
> > From: "Tianci.Yin"
> >
> > [why]
> > In dual GPUs scenario, stolen_size is assigned to zero on the 2nd GPU,
> > then the bottom region of VRAM was allocated as GTT, unfortunately
> > a small reg
On Wed, Jan 8, 2020 at 1:15 AM Tiecheng Zhou wrote:
>
> guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
> as a consequence, the rev_id and external_rev_id are wrong.
>
> workaround it by hardcoding the rev_id to 0, which is the default value.
>
> Signed-off-by: Tiecheng Zhou
> ---
>
Am 07.01.20 um 20:25 schrieb Tianlin Li:
Right now several architectures allow their set_memory_*() family of
functions to fail, but callers may not be checking the return values.
If set_memory_*() returns with an error, call-site assumptions may be
infact wrong to assume that it would either suc
Am 08.01.20 um 13:36 schrieb Tianci Yin:
From: "Tianci.Yin"
[why]
In dual GPUs scenario, stolen_size is assigned to zero on the 2nd GPU,
then the bottom region of VRAM was allocated as GTT, unfortunately
a small region of bottom VRAM was encroached by UMC firmware during
GDDR6 BIST training, th
From: "Tianci.Yin"
[why]
In dual GPUs scenario, stolen_size is assigned to zero on the 2nd GPU,
then the bottom region of VRAM was allocated as GTT, unfortunately
a small region of bottom VRAM was encroached by UMC firmware during
GDDR6 BIST training, this cause pagefault.
[how]
Forcing stolen_s
Am 07.01.20 um 22:13 schrieb Alex Deucher:
It should work on all Raven variants, but some users have
reported issues with original Raven with IOMMU enabled.
So far there have been no issues observed with PCO or RV2.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
Am 08.01.20 um 10:40 schrieb Nirmoy Das:
Do not ignore amdgpu_irq_add_id return value while registering
VMC page fault interrupt.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/driver
Do not ignore amdgpu_irq_add_id return value while registering
VMC page fault interrupt.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
i
[Why]
While handling LINK_ADDRESS reply, current code expects a peer device
can handle sideband message once the peer device type is reported as
DP_PEER_DEVICE_MST_BRANCHING. However, when the connected device is
a SST branch case, it can't handle the sideband message(MST_CAP=0 in
DPCD 00021h).
Cu
[Why]
For later usage convenience, add the function
drm_dp_mst_is_dp_mst_end_device() to decide whether a peer device
connected to a DFP is mst end device. Which also indicates if the peer
device is capable of handling message or not.
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/drm_dp_mst_topol
Noticed this while testing 4 ports MST hub from StarTech.com.
While plugging in and display a MST monitor(Dell U2417H), change the MST
feature to off from OSD. Monitor then can't display anymore.
After analyzing, found out that the CSN reports the specific port from
Device with MST Branching Unit
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