RE: [PATCH] drm/amdgpu: check if driver should try recovery in ras recovery path

[AMD Public Use] Seems it's better to sperate it into two patches, considering the patch purpose. One patch is to add user recovery capability by module parameter for Arcturus chip, and another is to check if driver should try recovery in RAS function, applying to all supported asics who enable

Re: [PATCH] drm/amdgpu: fill the alignment for secure buffer

On Wed, Jan 15, 2020 at 03:45:50PM +0800, Koenig, Christian wrote: > Am 15.01.20 um 08:07 schrieb Huang Rui: > > The alignment should match the page size for secure buffer. > > That is superfluous, buffer are aligned to a page size anyway. > If use huge page, will buffer still be aligned? Thank

Re: [PATCH] drm/amdgpu: fill the alignment for secure buffer

Am 15.01.20 um 08:07 schrieb Huang Rui: The alignment should match the page size for secure buffer. That is superfluous, buffer are aligned to a page size anyway. Christian. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 --- 1 file changed, 4 insertions(+)

Re: [PATCH] drm/amdgpu: always reset asic when going into suspend

On Thu, Dec 19, 2019 at 10:08 PM Alex Deucher wrote: > I think there may be some AMD specific handling needed in > drivers/acpi/sleep.c. My understanding from reading the modern > standby documents from MS is that each vendor needs to provide a > platform specific PEP driver. I'm not sure how mu

Re: [PATCH 01/23] drm: Add get_scanout_position() to struct drm_crtc_helper_funcs

Hi Am 14.01.20 um 16:31 schrieb Yannick FERTRE: > Thanks for the patch. > > Tested-by: Yannick Fertré Thanks for testing all these patches. Best regards Thomas > > BR > Yannick Fertré > > > On 1/10/20 10:21 AM, Thomas Zimmermann wrote: >> The new callback get_scanout_position() reads the

[PATCH] drm/amdgpu: fill the alignment for secure buffer

The alignment should match the page size for secure buffer. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f39

[PATCH] drm/amdgpu: flush the fence on the bo after we individualize

As we move the ttm_bo_individualize_resv() upwards, we need flush the copied fence too. Otherwise the driver keeps waiting for fence. run&Kill kfdtest, then perf top. 25.53% [ttm] [k] ttm_bo_delayed_delete 24.29% [kernel] [k] dma_resv_test_signaled_rcu

RE: [PATCH] drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training enabled(V5)

Reviewed-by: Feifei Xu -Original Message- From: Tianci Yin Sent: Monday, January 13, 2020 10:06 AM To: amd-gfx@lists.freedesktop.org Cc: Tuikov, Luben ; Koenig, Christian ; Deucher, Alexander ; Zhang, Hawking ; Xu, Feifei ; Yuan, Xiaojie ; Long, Gang ; Wang, Kevin(Yang) ; Yin, Tia

[PATCH] drm/amdgpu: check if driver should try recovery in ras recovery path

To allow the flexibilty for user to disable gpu recovery in RAS recovery path by module parameter amdgpu_gpu_recovery Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 ++- 2 files changed, 3 insertions(+), 1 deletio

RE: [PATCH] drm/amdgpu: check if driver should try recovery in ras recovery path

[AMD Official Use Only - Internal Distribution Only] Please ignore the patch, I will send out another one -Original Message- From: Hawking Zhang Sent: Wednesday, January 15, 2020 11:48 To: amd-gfx@lists.freedesktop.org; Chen, Guchun Cc: Zhang, Hawking Subject: [PATCH] drm/amdgpu: chec

[PATCH] drm/amdgpu: check if driver should try recovery in ras recovery path

To allow the flexibilty for user to disable gpu recovery in RAS recovery path by module parameter amdgpu_gpu_recovery Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 ++- 2 files changed, 3 insertions(+), 1 deletio

Re: [follow-up] AMD Sensir Fusion HUB status

Thanks for the update! On 2020-01-11 1:16 a.m., Mihai wrote: Finally arrived: https://patchwork.kernel.org/project/linux-iio/list/?submitter=175589 On Fri, Dec 13, 2019, 5:25 PM Luya Tshimbalanga mailto:l...@fedoraproject.org>> wrote: Any update about the Sensor Fusion HUB status? Thank

Re: [PATCH 1/5] drm/amdgpu: only set cp active field for kiq queue

On Tue, Jan 14, 2020 at 11:30:15PM +0800, Kuehling, Felix wrote: > Patch 1 is > > Reviewed-by: Felix Kuehling > > Patches 2 and 3 should be squashed. In that case they are > > Reviewed-by: Felix Kuehling > > Patches 4 and 5 need to be tested. I think you mentioned GFX10 worked > (patch 4) bu

RE: [PATCH 2/2] drm/dp_mst: Handle SST-only branch device case

[AMD Public Use] > -Original Message- > From: Lyude Paul > Sent: Wednesday, January 15, 2020 5:19 AM > To: Lin, Wayne ; dri-de...@lists.freedesktop.org; > amd-gfx@lists.freedesktop.org > Cc: Kazlauskas, Nicholas ; Wentland, Harry > ; Zuo, Jerry ; Ville Syrjälä > ; Wentland, Harry > Sub

RE: [PATCH 1/2] drm/dp_mst: Add a function to determine the mst end device

[AMD Public Use] > -Original Message- > From: Lyude Paul > Sent: Wednesday, January 15, 2020 5:16 AM > To: Lin, Wayne ; dri-de...@lists.freedesktop.org; > amd-gfx@lists.freedesktop.org > Cc: Kazlauskas, Nicholas ; Wentland, Harry > ; Zuo, Jerry > Subject: Re: [PATCH 1/2] drm/dp_mst: Ad

RE: [PATCH] drm/amdgpu/pm: clean up return types

Reviewed-by: Evan Quan -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Wednesday, January 15, 2020 1:26 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu/pm: clean up return types count is size_t so don't use negative values. Sign

Re: [PATCH] drm/scheduler: fix documentation by replacing rq_list with sched_list

[AMD Official Use Only - Internal Distribution Only] Hi Nirmoy, Seems like documentation for struct drm_sched_entity@gpu_scheduler.h need update as well. BR, Xiaojie From: amd-gfx on behalf of Nirmoy Das Sent: Tuesday, January 14, 2020 5:58 PM To: am

Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

[AMD Official Use Only - Internal Distribution Only] Thanks Alex! From: Alex Deucher Sent: Wednesday, January 15, 2020 1:39 To: Yin, Tianci (Rico) Cc: amd-gfx list ; Xu, Feifei ; Zhang, Hawking Subject: Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settin

Re: [PATCH 0/2] Adjust AMD GPU ATS quirks

On Tue, Jan 14, 2020 at 03:55:21PM -0500, Alex Deucher wrote: > We've root caused the issue and clarified the quirk. > This also adds a new quirk for a new GPU. > > Alex Deucher (2): > pci: Clarify ATS quirk > pci: add ATS quirk for navi14 board (v2) > > drivers/pci/quirks.c | 32 +++

[PATCH v3 1/5] drm/amdgpu/vcn: support multiple-instance dpg pause mode

Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- 4 files c

[PATCH v3 3/5] drm/amdgpu/vcn2.5: add DPG mode start and stop

Add DPG mode start and stop functions for vcn2.5 v2: Correct firmware ucode index in vcn_v2_5_mc_resume_dpg_mode Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 295 +- 1 file changed, 293 insertions(+), 2 deletions(-) diff --git a/drivers/g

[PATCH v3 0/5] support Arcturus IFM workaround

Add vcn2.5 dpg mode/dpg pause mode/dpg sram mode to support acturus IFM(instruction fetch monitor) work around. v2: Correct firmware ucode index in vcn_v2_5_mc_resume_dpg_mode v3: Share multiple instance indirect DPG SRAM mode support for vcn2 James Zhu (5): drm/amdgpu/vcn: support multiple-ins

[PATCH v3 2/5] drm/amdgpu/vcn2.5: support multiple instance direct SRAM read and write

Add multiple instance direct SRAM read and write support for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 27 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 46 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 94 -

[PATCH v3 4/5] drm/amdgpu/vcn2.5: add dpg pause mode

Add dpg pause mode support for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 70 +++ 1 file changed, 70 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index b3ddf68..7ce5a9e

[PATCH v3 5/5] drm/amdgpu/vcn2.5: implement indirect DPG SRAM mode

Implement indirect DPG SRAM mode for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 ++ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 69 +++-- 2 files changed, 52 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/am

Re: [PATCH 2/2] drm/dp_mst: Handle SST-only branch device case

On Wed, 2020-01-08 at 16:44 +0800, Wayne Lin wrote: > [Why] > While handling LINK_ADDRESS reply, current code expects a peer device > can handle sideband message once the peer device type is reported as > DP_PEER_DEVICE_MST_BRANCHING. However, when the connected device is > a SST branch case, it ca

Re: [PATCH 1/2] drm/dp_mst: Add a function to determine the mst end device

This patch series looks awesome so far, thank you for the great work! This patch looks great, I think we should just squash it into the next patch though since we don't use this function until then. On Wed, 2020-01-08 at 16:44 +0800, Wayne Lin wrote: > [Why] > For later usage convenience, add the

[PATCH 2/2] pci: add ATS quirk for navi14 board (v2)

On some harvest configurations, a driver needs to properly initialize some of the caches on the GPU for instances that are harvested (parts of the chip that are disabled due to silicon flaws). For navi we implemented this in the vbios, but it appears some boards went to production with an older vb

[PATCH 1/2] pci: Clarify ATS quirk

We finally root caused this to a GPU configuration issue. On some harvest configurations, a driver needs to properly initialize some of the caches on the GPU for instances that are harvested (parts of the chip that are disabled due to silicon flaws). The necessary code to fix this up is too compl

[PATCH 0/2] Adjust AMD GPU ATS quirks

We've root caused the issue and clarified the quirk. This also adds a new quirk for a new GPU. Alex Deucher (2): pci: Clarify ATS quirk pci: add ATS quirk for navi14 board (v2) drivers/pci/quirks.c | 32 +--- 1 file changed, 25 insertions(+), 7 deletions(-) -- 2

[RFC PATCH] drm/scheduler: use idle time to do better loadbalance

This patch adds required fields to drm_sched_job and drm_gpu_scheduler structure to cumulatively calculate amount of time a drm_gpu_scheduler spend on serving a job. Using least used drm scheduler to choose a run queue improves drm_sched_entity_get_free_sched()'s job distribution Below are test r

Re: [PATCH 2/6] drm/amdgpu/vcn2.5: add direct SRAM read and write

Sure. Thanks! James On 2020-01-14 2:06 p.m., Leo Liu wrote: I think you can avoid the duplication, instead adding instance to "RREG32(WREG)_SOC15_DPG_MODE_2_0(offset, mask_en) ", just like adding instance to other part of the code. Regards, Leo On 2020-01-14 12:58 p.m., James Zhu wrote:

Re: [PATCH 4/6] drm/amdgpu/vcn2.5: add dpg pause mode

On 2020-01-14 2:10 p.m., Leo Liu wrote: On 2020-01-14 12:58 p.m., James Zhu wrote: Add dpg pause mode support for vcn2.5 Signed-off-by: James Zhu ---   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 70 +++   1 file changed, 70 insertions(+) diff --git a/drivers/gp

Re: [PATCH 4/6] drm/amdgpu/vcn2.5: add dpg pause mode

On 2020-01-14 12:58 p.m., James Zhu wrote: Add dpg pause mode support for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 70 +++ 1 file changed, 70 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/

Re: [PATCH 2/6] drm/amdgpu/vcn2.5: add direct SRAM read and write

I think you can avoid the duplication, instead adding instance to "RREG32(WREG)_SOC15_DPG_MODE_2_0(offset, mask_en) ", just like adding instance to other part of the code. Regards, Leo On 2020-01-14 12:58 p.m., James Zhu wrote: Add direct SRAM read and write MACRO for vcn2.5 Signed-off-by:

Re: [PATCH 1/6] drm/amdgpu/vcn: support multiple-instance dpg pause mode

Reviewed-by: Leo Liu On 2020-01-14 12:58 p.m., James Zhu wrote: Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |

Re: [PATCH v2] drm/dp_mst: clear time slots for ports invalid

Pushed, thanks! On Mon, 2020-01-06 at 18:21 +0800, Wayne Lin wrote: > [Why] > When change the connection status in a MST topology, mst device > which detect the event will send out CONNECTION_STATUS_NOTIFY messgae. > > e.g. src-mst-mst-sst => src-mst (unplug) mst-sst > > Currently, under the abo

[PATCH v2 3/6] drm/amdgpu/vcn2.5: add DPG mode start and stop

Add DPG mode start and stop functions for vcn2.5 v2: Correct firmware ucode index in vcn_v2_5_mc_resume_dpg_mode Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 295 +- 1 file changed, 293 insertions(+), 2 deletions(-) diff --git a/drivers/g

[PATCH 1/6] drm/amdgpu/vcn: support multiple-instance dpg pause mode

Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- 4 files c

[PATCH 5/6] drm/amdgpu/vcn: support multiple-instance dpg sram mode

Add multiple-instance dpg sram mode support for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 27 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 12 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 3 files changed, 23 inse

[PATCH 0/6] support ArcturusIFM workaround

Add vcn2.5 dpg mode/dpg pause mode/dpg sram mode to support acturus IFM(instruction fetch monitor) work around. James Zhu (6): drm/amdgpu/vcn: support multiple-instance dpg pause mode drm/amdgpu/vcn2.5: add direct SRAM read and write drm/amdgpu/vcn2.5: add DPG mode start and stop drm/amdgp

[PATCH 3/6] drm/amdgpu/vcn2.5: add DPG mode start and stop

Add DPG mode start and stop functions for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 295 +- 1 file changed, 293 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2

[PATCH 4/6] drm/amdgpu/vcn2.5: add dpg pause mode

Add dpg pause mode support for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 70 +++ 1 file changed, 70 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index ea70aa8..8de51c9

[PATCH 6/6] drm/amdgpu/vcn2.5: implement indirect DPG SRAM mode

Implement indirect DPG SRAM mode for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 15 --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 69 +++-- 3 files changed, 62 insertions(+), 25 de

[PATCH 2/6] drm/amdgpu/vcn2.5: add direct SRAM read and write

Add direct SRAM read and write MACRO for vcn2.5 Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 26c6623..d3d75ec 1

Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

On Tue, Jan 14, 2020 at 6:42 AM Tianci Yin wrote: > > From: "Tianci.Yin" > > remove registers: mmSPI_CONFIG_CNTL > add registers: mmSPI_CONFIG_CNTL_1 > > Change-Id: I0bbaeca184e7dc85463d6c5740151d6ba1b08c06 > Signed-off-by: Tianci.Yin Series is: Reviewed-by: Alex Deucher > --- > drivers/gpu/

[PATCH] drm/amdgpu/pm: clean up return types

count is size_t so don't use negative values. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 39 -- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c i

Re: [PATCH 01/23] drm: Add get_scanout_position() to struct drm_crtc_helper_funcs

Thanks for the patch. Tested-by: Yannick Fertré BR Yannick Fertré On 1/10/20 10:21 AM, Thomas Zimmermann wrote: The new callback get_scanout_position() reads the current location of the scanout process. The operation is currentyl located in struct drm_driver, but

Re: [PATCH] drm/scheduler: fix race condition in load balancer

Am 14.01.20 um 17:13 schrieb Nirmoy: On 1/14/20 5:01 PM, Christian König wrote: Am 14.01.20 um 16:43 schrieb Nirmoy Das: Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queue in drm_sched_entity_select_rq() so that we

Re: [PATCH] drm/scheduler: fix race condition in load balancer

On 1/14/20 5:23 PM, Christian König wrote: Am 14.01.20 um 17:20 schrieb Nirmoy: On 1/14/20 5:01 PM, Christian König wrote: Am 14.01.20 um 16:43 schrieb Nirmoy Das: Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queu

Re: [PATCH] drm/scheduler: fix race condition in load balancer

Am 14.01.20 um 17:20 schrieb Nirmoy: On 1/14/20 5:01 PM, Christian König wrote: Am 14.01.20 um 16:43 schrieb Nirmoy Das: Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queue in drm_sched_entity_select_rq() so that we

Re: [PATCH] drm/scheduler: fix race condition in load balancer

On 1/14/20 5:01 PM, Christian König wrote: Am 14.01.20 um 16:43 schrieb Nirmoy Das: Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queue in drm_sched_entity_select_rq() so that we don't loadbalance jobs within an entit

Re: [PATCH 19/23] drm/stm: Convert to CRTC VBLANK callbacks

Thanks for the patch. Tested-by: Yannick Fertré BR Yannick Fertré On 1/10/20 10:21 AM, Thomas Zimmermann wrote: VBLANK callbacks in struct drm_driver are deprecated in favor of their equivalents in struct drm_crtc_funcs. Convert stm over. Signed-off-by: Thomas Z

Re: [PATCH] drm/scheduler: fix race condition in load balancer

On 1/14/20 5:01 PM, Christian König wrote: Am 14.01.20 um 16:43 schrieb Nirmoy Das: Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queue in drm_sched_entity_select_rq() so that we don't loadbalance jobs within an entit

Re: [PATCH 23/23] drm: Cleanup VBLANK callbacks in struct drm_driver

Thanks for the patch. Tested-by: Yannick Fertré BR Yannick Fertré On 1/10/20 10:21 AM, Thomas Zimmermann wrote: All non-legacy users of VBLANK functions in struct drm_driver have been converted to use the respective interfaces in struct drm_crtc_funcs. The remain

Re: [PATCH 08/23] drm/stm: Convert to struct drm_crtc_helper_funcs.get_scanout_position()

Thanks for the patch. Tested-by: Yannick Fertré BR Yannick Fertré On 1/10/20 10:21 AM, Thomas Zimmermann wrote: The callback struct drm_driver.get_scanout_position() is deprecated in favor of struct drm_crtc_helper_funcs.get_scanout_position(). Convert stm over.

Re: [PATCH] drm/scheduler: fix race condition in load balancer

Am 14.01.20 um 16:43 schrieb Nirmoy Das: Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queue in drm_sched_entity_select_rq() so that we don't loadbalance jobs within an entity. But because we update entity->job_queue l

Re: [PATCH 09/23] drm: Remove struct drm_driver.get_scanout_position()

Thanks for the patch. Tested-by: Yannick Fertré BR Yannick Fertré On 1/10/20 10:21 AM, Thomas Zimmermann wrote: All users of struct drm_driver.get_scanout_position() have been covnerted to the respective CRTC helper function. Remove the callback from struct drm_d

[PATCH] drm/scheduler: fix race condition in load balancer

Jobs submitted in an entity should execute in the order those jobs are submitted. We make sure that by checking entity->job_queue in drm_sched_entity_select_rq() so that we don't loadbalance jobs within an entity. But because we update entity->job_queue later in drm_sched_entity_push_job(), there

Re: [PATCH 1/5] drm/amdgpu: only set cp active field for kiq queue

Patch 1 is Reviewed-by: Felix Kuehling Patches 2 and 3 should be squashed. In that case they are Reviewed-by: Felix Kuehling Patches 4 and 5 need to be tested. I think you mentioned GFX10 worked (patch 4) but GFX8 was failing (patch 5). Have you found the problem? I haven't seen any update

Re: [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro

(On Tue, Jan 14, 2020 at 6:42 AM chen gong wrote: > > Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to > hang when GPU is in "gfxoff" state. > I do a uniform substitution here. > > Signed-off-by: chen gong Alternatively, we could wrap this function with amdgpu_gfx_off_ctrl()

Re: [PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32

On Tue, Jan 14, 2020 at 6:43 AM chen gong wrote: > > Reading some registers by mmio will result in hang when GPU is in > "gfxoff" state. > > This problem can be solved by GPU in "ring command packages" way. > > Signed-off-by: chen gong > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++ >

Re: [PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ

On Tue, Jan 14, 2020 at 6:42 AM chen gong wrote: > > Move amdgpu_virt_kiq_rreg function to amdgpu_device.c, and rename it to > amdgpu_kiq_rreg.Make it generic and flexible。 > > Signed-off-by: chen gong > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +- > drivers/gpu/drm/amd/amdgpu/amdgp

Re: [PATCH 23/23] drm: Cleanup VBLANK callbacks in struct drm_driver

Hi Am 12.01.20 um 23:53 schrieb Daniel Vetter: > On Fri, Jan 10, 2020 at 10:21:27AM +0100, Thomas Zimmermann wrote: >> All non-legacy users of VBLANK functions in struct drm_driver have been >> converted to use the respective interfaces in struct drm_crtc_funcs. The >> remaining users of VBLANK ca

[PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

From: "Tianci.Yin" remove registers: mmSPI_CONFIG_CNTL add registers: mmSPI_CONFIG_CNTL_1 Change-Id: I8d1c5d0a0553d60a6e419d6acb9750e5b2634e49 Signed-off-by: Tianci.Yin --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/dr

[PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32

Reading some registers by mmio will result in hang when GPU is in "gfxoff" state. This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 2 files changed

[PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ

Move amdgpu_virt_kiq_rreg function to amdgpu_device.c, and rename it to amdgpu_kiq_rreg.Make it generic and flexible。 Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 +- drivers/gpu/drm/a

[PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro

Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to hang when GPU is in "gfxoff" state. I do a uniform substitution here. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gp

[PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14

From: "Tianci.Yin" remove registers: mmSPI_CONFIG_CNTL add registers: mmSPI_CONFIG_CNTL_1 Change-Id: I0bbaeca184e7dc85463d6c5740151d6ba1b08c06 Signed-off-by: Tianci.Yin --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/dr

Re: [PATCH RESEND] drm/amdgpu: error out on entity with no run queue

Am 14.01.20 um 10:50 schrieb : Disabled HW IP's entity initialized with NULL rq. We should not process any submit request from userspace for a disabled HW IP. Signed-off-by: Nirmoy Das Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 + 1 file changed, 5 i

Re: [PATCH] drm/scheduler: fix documentation by replacing rq_list with sched_list

Am 14.01.20 um 10:58 schrieb Nirmoy Das: Signed-off-by: Nirmoy Das Reviewed-by: Christian König --- drivers/gpu/drm/scheduler/sched_entity.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_ent

[PATCH] drm/scheduler: fix documentation by replacing rq_list with sched_list

Signed-off-by: Nirmoy Das --- drivers/gpu/drm/scheduler/sched_entity.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 2e3a058fc239..62bcca855c69 100644 --- a/drivers/gpu/drm/scheduler/s

[PATCH RESEND] drm/amdgpu: error out on entity with no run queue

Disabled HW IP's entity initialized with NULL rq. We should not process any submit request from userspace for a disabled HW IP. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/

Re: [PATCH 1/5] drm/amdgpu: only set cp active field for kiq queue

Ping~ On Fri, Jan 10, 2020 at 02:37:09PM +0800, Huang, Ray wrote: > The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped by > MAP_QUEUES packet. So we only need set cp active field for kiq queue. > > Signed-off-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +

Re: [PATCH] drm/amdgpu: modify packet size for pm4 flush tlbs

Am 14.01.20 um 04:43 schrieb Alex Sierra: [Why] PM4 packet size for flush message was oversized. [How] Packet size adjusted to allocate flush + fence packets. Change-Id: I9a577d2118398b3139011829de12789b2a577a19 Signed-off-by: Alex Sierra Reviewed-by: Christian König --- drivers/gpu/drm