ALLOC_MEM_FLAGS_* used are the same as the KFD_IOC_ALLOC_MEM_FLAGS_*,
but they are interweavedly used in kernel driver, resulting in bad
readability. For example, KFD_IOC_ALLOC_MEM_FLAGS_COHERENT is not
referenced in kernel, and it functions implicitly in kernel through
ALLOC_MEM_FLAGS_COHERENT,
final correction: I probably could actually get rid of this patch and do this
a bit more nicely by just making sure that we reprobe path resources for
connectors while under drm_dp_mst_topology_mgr->base.lock on CSNs, instead of
punting it off to the link address work like we seem to be doing. So,
On Thu, 2020-03-05 at 20:29 +0200, Ville Syrjälä wrote:
> On Thu, Mar 05, 2020 at 01:13:36PM -0500, Lyude Paul wrote:
> > On Thu, 2020-03-05 at 15:11 +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 04, 2020 at 05:36:12PM -0500, Lyude Paul wrote:
> > > > It's next to impossible for us to do connector
Please send a proper patch using git format-patch. Have you actually
tested this patch? Can you provide the details of your specific
board? The reason the clock as forced lower was due to stability
issues with the higher clocks on most HAINAN boards. If it's working
for you, I'd suggest just
To fit the latest SMC firmware 53.27 and eliminate the
warning on driver loading.
Change-Id: I3f524d03e53ec6778b7118ef72652a538eec4ace
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
It can support different NV1x ASIC better. And this can guard
no member got missing.
Change-Id: Id5e6608f6be1b31ef1c0a5c1d399da295524ff43
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/atomfirmware.h | 102 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 99
Yeah, that one looks important. Feel free to add an Acked-by: Christian
König .
Regards,
Christian.
Am 05.03.20 um 17:06 schrieb Felix Kuehling:
[moving to public mailing list]
Thank you. I'll also apply patch 2/2 to amd-staging-drm-next. It's not
fixing a memory leak there, but it should
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