回复: [PATCH] drm/amdgpu: revise RLCG access path

Reviewed-by: Emily Deng -邮件原件- 发件人: amd-gfx 代表 Monk Liu 发送时间: 2020年3月16日 12:06 收件人: amd-gfx@lists.freedesktop.org 抄送: Liu, Monk 主题: [PATCH] drm/amdgpu: revise RLCG access path what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to

[PATCH] drm/amdgpu: revise RLCG access path

what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help now even debugfs's reg_op can used to dump wave. tested-by: Monk Liu tested-by: Zhou pengju

[PATCH AUTOSEL 4.19 15/20] drm/amd/display: Clear link settings on MST disable connector

From: Bhawanpreet Lakha [ Upstream commit 5ac7fd2f597b88ee81f4748ee50cab06192a8dc3 ] [Why] If we have a single MST display and we disconnect it, we dont disable that link. This causes the old link settings to still exist Now on a replug for MST we think its a link loss and will try to

[PATCH AUTOSEL 5.4 30/35] drm/amd/display: Clear link settings on MST disable connector

From: Bhawanpreet Lakha [ Upstream commit 5ac7fd2f597b88ee81f4748ee50cab06192a8dc3 ] [Why] If we have a single MST display and we disconnect it, we dont disable that link. This causes the old link settings to still exist Now on a replug for MST we think its a link loss and will try to

[PATCH AUTOSEL 5.4 31/35] drm/amd/display: fix dcc swath size calculations on dcn1

From: Josip Pavic [ Upstream commit a0275dfc82c9034eefbeffd556cca6dd239d7925 ] [Why] Swath sizes are being calculated incorrectly. The horizontal swath size should be the product of block height, viewport width, and bytes per element, but the calculation uses viewport height instead of width.

[PATCH AUTOSEL 5.4 29/35] drm/amdgpu: clean wptr on wb when gpu recovery

From: Yintian Tao [ Upstream commit 2ab7e274b86739f4ceed5d94b6879f2d07b2802f ] The TDR will be randomly failed due to compute ring test failure. If the compute ring wptr & 0x7ff(ring_buf_mask) is 0x100 then after map mqd the compute ring rptr will be synced with 0x100. And the ring test packet

[PATCH AUTOSEL 4.19 16/20] drm/amd/display: fix dcc swath size calculations on dcn1

From: Josip Pavic [ Upstream commit a0275dfc82c9034eefbeffd556cca6dd239d7925 ] [Why] Swath sizes are being calculated incorrectly. The horizontal swath size should be the product of block height, viewport width, and bytes per element, but the calculation uses viewport height instead of width.

[PATCH AUTOSEL 5.5 34/41] drm/amd/display: Clear link settings on MST disable connector

From: Bhawanpreet Lakha [ Upstream commit 5ac7fd2f597b88ee81f4748ee50cab06192a8dc3 ] [Why] If we have a single MST display and we disconnect it, we dont disable that link. This causes the old link settings to still exist Now on a replug for MST we think its a link loss and will try to

[PATCH AUTOSEL 5.5 35/41] drm/amd/display: fix dcc swath size calculations on dcn1

From: Josip Pavic [ Upstream commit a0275dfc82c9034eefbeffd556cca6dd239d7925 ] [Why] Swath sizes are being calculated incorrectly. The horizontal swath size should be the product of block height, viewport width, and bytes per element, but the calculation uses viewport height instead of width.

[PATCH AUTOSEL 5.5 33/41] drm/amdgpu: clean wptr on wb when gpu recovery

From: Yintian Tao [ Upstream commit 2ab7e274b86739f4ceed5d94b6879f2d07b2802f ] The TDR will be randomly failed due to compute ring test failure. If the compute ring wptr & 0x7ff(ring_buf_mask) is 0x100 then after map mqd the compute ring rptr will be synced with 0x100. And the ring test packet