[AMD Public Use]
Exactly Tao.
When hw_support capability is aligned with AMDGPU_RAS_BLOCK_MASK by and
operation, sw_support capability is calculated on top of hw_support value and
amdgpu_ras_mask accordingly.
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Tuesday, June 2,
[AMD Public Use]
I think the real reason is we have " *hw_supported &= AMDGPU_RAS_BLOCK_MASK;"
already, but the patch is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chen, Guchun
> Sent: 2020年6月2日 13:58
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao ; Li,
>
[AMD Public Use]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chen, Guchun
> Sent: 2020年6月2日 13:50
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao
> Cc: Chen, Guchun
> Subject: [PATCH] drm/amdgpu: fix RAS memory leak in error case
>
> RAS context memory needs
Module parameter amdgpu_ras_mask has been involved in
the calculation of ras support capability, so drop this
redundant code.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/dri
RAS context memory needs to freed in failure case.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
in
[AMD Official Use Only - Internal Distribution Only]
Ping...
Thanks,
> -Original Message-
> From: Liang, Prike
> Sent: Friday, May 29, 2020 11:28 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liang, Prike
> Subject: [PATCH] drm/amdgpu: enable renoir di
Sienna Cichlid is GPU from AMD. This patch set adds support for it
including asic init, power management, display, interrupts, gfx, multi-media,
etc.
The new register headers (patches 1-4) are quite large so I did not send
them to the mailing list. The full patch set including register headers
c
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 1911a34cc060..34ae4f3a32f4 100644
--- a/drivers/gpu/drm/a
From: Bhawanpreet Lakha
Initilize function tables for hw programing
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 148 ++
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.h | 33
2 files changed, 181 insertions(+)
create mode 100644 driv
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/Makefile | 4 ++
drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 54 +++
2 files changed, 58 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/Makefile
diff -
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c| 17 -
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h| 12
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 3 +--
3 files changed, 1 insertion(+), 31 d
From: Dmytro Laktyushkin
This was done already done for DCN
From:
f7a695da88cf ("drm/amd/display: fix and simplify pipe split logic")
Signed-off-by: Dmytro Laktyushkin
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 213 --
1 file changed,
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index ef3f07dc89cd..a7cfe3ac7cb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++
From: Bhawanpreet Lakha
Add HW sequence programing for DCN3
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 +
drivers/gpu/drm/amd/display/dc/dc_stream.h| 15 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 46 ++
.../amd/display/dc/dcn10/dcn10_
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 1e5a92b192a1..555af
From: Bhawanpreet Lakha
DMUB (Display Micro-Controller Unit)
Used to read/write regs
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 +
drivers/gpu/drm/amd/display/dmub/src/Makefile | 3 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 184 +
From: Bhawanpreet Lakha
Audio formating
Audio related code for setup/control
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 206
.../gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h | 230 ++
2 files changed, 436 insertions(+)
c
From: Bhawanpreet Lakha
Handle DCN3 in amdgpu_dm
v2: fix num_pkrs handling
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 20 ++
drivers/gpu/drm/amd/display/dc/dc_hw_types
From: Bhawanpreet Lakha
Add support for programming the DCN3 OPTC (Output Timing Controller)
HW Blocks:
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Bhawanpreet La
From: Bhawanpreet Lakha
Add programming of the DCCG (Display Controller Clock Generator)
block:
HW Blocks:
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 22
From: Bhawanpreet Lakha
-Handle DCN3 cases for bios parser and command tables
-Add command function tables for DCN3
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/bios/bios_parser2.c| 3 ++
.../display/dc/bios/command_table_helper2.c | 5 +++
.../dce112/command_table_helpe
From: Bhawanpreet Lakha
Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface)
HW Blocks:
+++--+ +--+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+++--+ +--+
|
v
++
| DPP |
++
|
From: Bhawanpreet Lakha
Add support to program the DCN3 DPP (Multiple pipe and plane combine)
HW Blocks:
++
| DPP |
++
|
v
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
From: Bhawanpreet Lakha
Add support to program GPIO HW block
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 10 +
.../display/dc/gpio/dcn30/hw_factory_dcn30.c | 257
.../display/dc/gpio/dcn30/hw_factory_dcn30.h | 33 ++
.../dc/gpio/dcn30/h
From: Bhawanpreet Lakha
Video Package generator.
used to prepare avi info, DP info etc
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c | 194 ++
.../gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h | 133
2 files changed, 327 insertions
From: Bhawanpreet Lakha
Add support for managing resources for DCN3
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 36 +-
drivers/gpu/drm/amd/display/dc/dc.h | 24 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 20 +
.../drm/amd/display/
From: Bhawanpreet Lakha
Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 10 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 22 +
.../drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h | 60 ++
..
From: Bhawanpreet Lakha
Add support to program the DCN3 OPP (Output Plane Processing)
HW Blocks:
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
+--
From: Bhawanpreet Lakha
Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)
HW Blocks:
+++--+
| HUBBUB || HUBP |
+++--+
|
v
++
| DPP |
++
|
v
++
| MPC |
+---
From: Bhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4
drivers/gpu/drm/amd/display/include/dal_types.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/a
From: Bhawanpreet Lakha
Add support to program the HUBBUB (DCN memory HUB interface)
HW Blocks:
++
| HUBBUB |
++
|
v
++
| DPP |
++
|
v
++
| MPC |
++
|
v
+---+
From: Bhawanpreet Lakha
Add support to program the DCN3 DWB (Display Writeback)
HW Blocks:
+++--+ +--+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+++--+ +--+
| ^
v |
++
From: Bhawanpreet Lakha
Add IWQ services for DCN3,
This allows us to create/init and manage irqs for DCN3
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn30/irq_service_dcn30.c | 384 ++
.../display/dc/irq/dcn3
From: Bhawanpreet Lakha
Add support for the DIO (Display IO) block of DCN3, which entails our
stream and link encoders.
HW Blocks:
++
| DIO |
++
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +
.../amd/display/dc/dcn1
From: Bhawanpreet Lakha
Add support to program the DCN3 MPC (Multiple pipe and plane combine)
HW Blocks:
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
From: shaoyunl
This is a regression due to the rebase , add sienna_cichlid sriov detection back
Signed-off-by: shaoyunl
Reviewed-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
From: Kenneth Feng
The instant retrieved gfxclk value should be 0 in gfxoff state.
This can be fetched with gfxoff enabled.
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 7 ---
1 file changed, 4 ins
From: Likun Gao
Enable uclk deep sleep for sienna_cichlid.
Df cstate kicks in first, then df triggers uclk ds with the sideband.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 inse
We don't want a gpu scheduler for mes.
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 5c28868f7adc..4b746
From: Likun Gao
Add support for PSP SPL (Security patch level) table to support
anti-rollback of FW loaded by Trusted OS.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_uc
From: Likun Gao
Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards
for all the use cases (IP discovery/G6 memory
training/profiling/diagnostic data.etc), otherwise, fallback to legacy
approach to check and reserve tmr block for ip discovery data and G6
memory trainin
From: Boyuan Zhang
To workaround an issue in DPG
V2: update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/dr
From: Boyuan Zhang
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and
WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0.
These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename
it to be a general name.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Acked-
From: Likun Gao
Only enable one gfx pipe for sienna_cichlid currently.
Signed-off-by: Likun Gao
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gf
From: Boyuan Zhang
Enable DPG mode for VCN3.0 by updating related flag.
V2: update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c |
From: Likun Gao
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm
From: Likun Gao
Enable GFXOFF for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_
VCN3 has 2 unsymmetrical instances, i.e there're less codecs
on instance 1, we use 0 for decode and 1 for encode for now
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/a
From: Likun Gao
VCN removed JPEG for instance 1, so drop jpeg instance1 dpm setup.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/am
From: Likun Gao
a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
From: Likun Gao
Add memory training support for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
From: Likun Gao
Drop the hardcode of sienna_cichlid which will force to use softpptable,
so that it can use pptable on vbios once the value of pp_table_id get
from vbios is 0.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sm
From: Likun Gao
C2P memory reserved should not in tmr memory range.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 48 ++---
1 file changed, 19 insertions(+), 29 deletions(-)
diff --git a/driv
From: Kenneth Feng
fw ctf can be triggered if the temperature can't be throttled below the limit.
then the gpu will be powered off and the whole system will hang.
Signed-off-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file chang
From: Evan Quan
For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No
need to have driver stepped in.
V2: limit this for baco really
Signed-off-by: Evan Quan
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 24 +++
From: Likun Gao
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Likun Gao
Add function to append powerplay table from vbios for sienna_cichlid.
v2: squash in warning fix
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 101 ++
1 file changed, 101 inse
From: Likun Gao
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 123 +
1 file changed, 123 insertions(+)
diff --git a/drivers/gpu/drm
From: Likun Gao
Add support for loading SPL firmware.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 4 +++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 34 ++
From: Likun Gao
Support for psp firmware header version v1_3 initialization and
information print.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 24 +
From: Likun Gao
Add support to force and unforce MCLK or SOCCLK to dpm limit value.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/am
From: shaoyunl
On SRIOV run time, driver shouldn't directly access invalidation registers
through MMIO.
Use kiq to submit wait_reg_mem package for the invalidation
Signed-off-by: shaoyunl
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |
From: Likun Gao
Disable runtime pm for sienna_cichlid temporarily as BACO regression issue.
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdg
From: Likun Gao
For Sienna_Cichlid, GFXOFF state puts gfx dpm into standby mode, then the
gfxclk can't be retireved.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 71 ---
1 file changed, 60 i
From: Likun Gao
Add function to check whether baco is support for sienna cichlid.
Remove fucntion of get clock by type with latency as it will not be
called.
Signed-off-by: Likun Gao
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 101 --
1 file
From: Likun Gao
Enable VDDCI and MVDD if PP_MCLK_DPM_MASK was enable for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Boyuan Zhang
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for
VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm
From: Likun Gao
Enable RSMU SMN PG for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
From: Boyuan Zhang
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 34 +++
1 f
From: Likun Gao
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/dr
From: Boyuan Zhang
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd
From: Boyuan Zhang
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0
These two macros are used specifically for VCN1.0, therefore rename
it from general name to VCN1.0 specific name.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Acked-by: Alex Deucher
Signed-off-by: Alex
From: Boyuan Zhang
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 66 +++
1
From: Likun Gao
Enable APCC DFLL for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
From: Likun Gao
Add function to get pptable power limit for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/pow
From: Yong Zhao
v4: drop get_tile_config, comment out other callbacks
Signed-off-by: Yong Zhao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 13 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 834 ++
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
From: Hawking Zhang
For Sienna_Cichlid, query fw_reserved_fb_size from vbios directly.
For navi1x, fall back to default 64K TMR size.
For pre-navi, no need to reserve tmr region in top LFB.
v2: fix TMR define (Alex)
v3: partially revert size change
Signed-off-by: Hawking Zhang
Reviewed-by: Ale
From: "Jerry (Fangzhi) Zuo"
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/a
From: Kenneth Feng
add HDP mgcg and ls support and verified
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/
From: Kenneth Feng
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a
From: Boyuan Zhang
Add range for vcn instance 1 for translation for internal register offset, which
is needed for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
From: Likun Gao
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.
Signed-off-by: Likun Gao
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/g
From: Kenneth Feng
enable athub pg and the status can be checked in
ATHUB_MISC_CNTL.
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c| 3 ++-
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 +++
2 fi
From: Le Ma
Update mes_api_def.h to match the latest mes fw.
v2: clean up coding style based on kernel standards:
- fix indentation and alignment
- break long lines
- put the opening brace last on the line
- remove unnecessary blank line and space
- replace uint(32|64) with standard ui
From: Likun Gao
Enable OUT OF BAND MONITER for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/power
From: Likun Gao
Update gfx golden setting for gfx10.3.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/dr
From: Likun Gao
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Feifei Xu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/driv
From: Kenneth Feng
athub ls is bounded with hdp ls,verified.
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/
From: Leo Liu
for the second instance with correct index
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/dri
From: Likun Gao
Enable VCN dpm set for sienna_cichlid.
Enable JPEG dpm set for sienna_cichlid.
v2: squash in BACO fix (Kenneth)
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
.../drm/amd/powerplay/sien
From: Likun Gao
Enable mmhub clockgating.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 451557544b8
From: Kenneth Feng
mmhub pg can be obvserved from PCTL_CTRL
Signed-off-by: Kenneth Feng
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c| 3 ++-
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 +++
2 files changed, 5 insertions
From: Le Ma
Statically allocated VM inv eng of gfxhub on sienna_cichlid is used up.
Also VM inv eng is no need for mes ring.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 +++
1 file changed, 3 insertions(+)
diff
From: Boyuan Zhang
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for
VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm
From: Hersen Wu
dp/hdmi ati hda is not shown in audio settings
Signed-off-by: Hersen Wu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
sound/pci/hda/hda_intel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 92a04
From: Likun Gao
Enable the feature of Voltage Regulator (VR) Hot for sienna_cichlid.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/p
From: Boyuan Zhang
Use indirect sram for secure DPG mode
V2: update description.
Signed-off-by: Boyuan Zhang
Reviewed-by: James Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drive
From: Le Ma
Pass a piece of memory to MES ucode to fill contents.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 36 ++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/
From: Jay Cornwall
- Replace SQC stores with TCP stores
- Synchronize with MSG_SAVEWAVE via lgkmcnt
- HW_REG_IB_STS is now read-only
Signed-off-by: Jay Cornwall
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 844 +-
.../amd/amdkfd/cwsr_trap_han
From: Jay Cornwall
- Preserve scalar GPRs ttmp[4:11] and ttmp13
- Add single step exception during context save workaround
- Remove incorrect PC adjustment during context save
Signed-off-by: Jay Cornwall
Reviewed-by: Yong Zhao
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdkfd/cwsr_trap_
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