Am 05.06.20 um 16:29 schrieb Andrey Grodzovsky:
On 5/11/20 2:45 AM, Christian König wrote:
Am 09.05.20 um 20:51 schrieb Andrey Grodzovsky:
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/ttm/ttm_bo.c | 22 +-
include/drm/ttm/ttm_bo_driver.h | 2 ++
2 files
Use kvfree() instead of kfree() to free coeff in build_regamma()
because the memory is allocated with kvzalloc().
Fixes: e752058b8671 ("drm/amd/display: Optimize gamma calculations")
Cc: sta...@vger.kernel.org
Signed-off-by: Denis Efremov
---
Use kfree() instead of kvfree() to free rgb_user in
calculate_user_regamma_ramp() because the memory is allocated with
kcalloc().
Signed-off-by: Denis Efremov
---
Looks like this kvfree is from merge conflict between
1fafef9dfe12 ("Merge drm-fixes-for-v4.17-rc6-urgent into drm-next")
and
The PWR block moved into SMUIO, so the ip discovery table
doesn't have an entry for PWR, but the register has the
same absolute offset, so just patch up the offsets after
updating the offsets from the IP discovery table.
v2: PWR became SMUIO block 1. fix the mapping.
Signed-off-by: Alex Deucher
On Fri, Jun 5, 2020 at 11:34 AM Alex Deucher wrote:
>
> The PWR block moved into SMUIO, so the ip discovery table
> doesn't have an entry for PWR, but the register has the
> same absolute offset, so just patch up the offsets after
> updating the offsets from the IP discovery table.
>
>
The PWR block moved into SMUIO, so the ip discovery table
doesn't have an entry for PWR, but the register has the
same absolute offset, so just patch up the offsets after
updating the offsets from the IP discovery table.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 6
On 6/5/20 3:29 PM, Daniel Vetter wrote:
Design is similar to the lockdep annotations for workers, but with
some twists:
- We use a read-lock for the execution/worker/completion side, so that
this explicit annotation can be more liberally sprinkled around.
With read locks lockdep isn't
[AMD Public Use]
Sorry, please skip for that fix, on the newest code, system will check whether
ASIC is newer that navi10 first and only if it was newer than navi10, it will
reserve memory for TMR.
So, the issue will not appear on the newest code struct.
Regards,
Likun
-Original
On 5/11/20 2:45 AM, Christian König wrote:
Am 09.05.20 um 20:51 schrieb Andrey Grodzovsky:
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/ttm/ttm_bo.c | 22 +-
include/drm/ttm/ttm_bo_driver.h | 2 ++
2 files changed, 23 insertions(+), 1 deletion(-)
diff
[AMD Public Use]
It looks more reasonable to me to move the AISC type check to the following. We
usually don't add any ASIC type check in atomfirmware interfaces.
adev->discovery_tmr_size =
amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
Regards,
Hawking
[AMD Public Use]
Wait, I see the risk. the amdgpu_ttm_init is general one even the prior Vega10
ASIC will invoke it, and they don't have atomfirmware support.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, June 5, 2020 22:05
To: Gao, Likun
[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, June 5, 2020 2:07 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 4/4] drm/amd/powerplay: use the same interval as PMFW on
[AMD Public Use]
Does it mean there is legacy VBIOS that even doesn't have firmwareinfo table
and introduce crash?
I think we expect the atomfirmware interface return 0 for ASICs prior to Sienna
Cichlid
Regards,
Hawking
-Original Message-
From: Gao, Likun
Sent: Friday, June 5, 2020
Design is similar to the lockdep annotations for workers, but with
some twists:
- We use a read-lock for the execution/worker/completion side, so that
this explicit annotation can be more liberally sprinkled around.
With read locks lockdep isn't going to complain if the read-side
isn't
Hello Bhawanpreet Lakha,
This is a semi-automatic email about new static checker warnings.
The patch 581b9589487e: "drm/amd/display: Add DCN3 HWSEQ" from May
21, 2020, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:618
dcn30_init_hw()
Hello Bhawanpreet Lakha,
This is a semi-automatic email about new static checker warnings.
The patch 581b9589487e: "drm/amd/display: Add DCN3 HWSEQ" from May
21, 2020, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:463
dcn30_init_hw()
From: Likun Gao
Skip for reserved fb size query for the ASIC older than navi10, as those
asic do not need for TMR region reserve and may get an invalid value.
Signed-off-by: Likun Gao
Change-Id: Idbc57805b8070f27ba6c3cf22f1892d6dab92f06
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 3
On Fri, Jun 5, 2020 at 10:30 AM Pierre-Eric Pelloux-Prayer
wrote:
>
> Hi Daniel,
>
> On 04/06/2020 10:12, Daniel Vetter wrote:
> [...]
> > @@ -6910,7 +6910,11 @@ static void amdgpu_dm_commit_planes(struct
> > drm_atomic_state *state,
> >* explicitly on fences instead
> >
On 6/5/20 1:34 PM, Prike.Liang wrote:
fix e467ab869f57 drm/amdgpu: use IP discovery table for renoir.
This nullptr issue should be specific on the Renoir series during try access
the PWR_MISC_CNTL_STATUS
when PWR IP not been detected by discovery table. Moreover the PWR IP not
existing in
This was for Vega20. However Vega20 support is
already dropped from current swSMU.
Change-Id: I5400496dff2e338de4622823484b88cda6018ec1
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 -
These APIs are used in amdgpu_smu.c only. Thus these wrappers
are unnecessary.
Change-Id: I7768a84e3a7dfbbfa624ac97d94138de52402827
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 24
drivers/gpu/drm/amd/powerplay/smu_internal.h | 3 ---
2 files
'UVD' is a HW engine name for Vega20 and before ASICs.
For newer ASICs, the similar engine is named as 'VCN'.
Change-Id: I5f1b9500ed5d35e395a5da32b81a78eb87bffc68
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 13 +
Helpful for error diagnostic.
Change-Id: I983ca308a2ee6ed11e16ec59ad97040d98b90512
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 118 +++--
1 file changed, 87 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
Use dev_err/warn/info/dbg instead. They are more MGPU friendly.
Change-Id: I07ad32c11dcf86cb1e3d1da1afa449f1f7dbd645
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 10 ++
Hi Daniel,
On 04/06/2020 10:12, Daniel Vetter wrote:
[...]
> @@ -6910,7 +6910,11 @@ static void amdgpu_dm_commit_planes(struct
> drm_atomic_state *state,
>* explicitly on fences instead
>* and in general should be called for
>* blocking commit to
[AMD Public Use]
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Friday, June 5, 2020 2:26 PM
To: Yang, Stanley ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Chen, Guchun ;
Liu, Monk ; Clements, John ; Li,
Dennis ; Yang, Stanley
Subject:
[AMD Public Use]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Stanley.Yang
> Sent: 2020年6月5日 13:56
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Chen, Guchun
> ; Liu, Monk ; Clements,
> John ; Zhou1, Tao ; Li,
> Dennis ; Yang, Stanley
> Subject: [PATCH V3]
Current 100ms interval makes no sense. User gets outdated
data due to this.
Change-Id: Ie1d950285460443d493f1647463b68cbe4a5ec67
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 +-
2 files changed, 2
Retrieve only those data interested instead of the whole table.
Change-Id: I6008351209be3b8812c547043a532e5fb90dd980
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 +
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 197 +-
2 files changed, 146
Retrieve only those interested metrics data instead of the whole
metrics table. By this, the memory copy can be dropped.
Change-Id: Ice2b2ba4647301119130be0ba65bb587f19d38ae
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 213 --
Retrieve only those data interested instead of the whole table.
Change-Id: I78a3ecce1075e73b96c2ee0b13aacc469bb09021
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 180 --
2 files changed, 127
[AMD Official Use Only - Internal Distribution Only]
Please ignore this patch, will resend.
> -Original Message-
> From: Stanley.Yang
> Sent: Friday, June 5, 2020 1:54 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Chen, Guchun
> ; Liu, Monk ; Clements,
> John ; Zhou1,
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