[AMD Official Use Only - Internal Distribution Only]
adev->serial which is used to hold the final serial number may need to be
enlarged also.
Since it comes with 16 bytes also.
BR,
Evan
-Original Message-
From: Dan Carpenter
Sent: Monday, June 8, 2020 10:18 PM
To: Quan, Evan ; Russell,
[AMD Public Use]
Reported-and-tested-by: Flora Cui
From: Deucher, Alexander
Sent: Monday, June 8, 2020 11:02 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Cui, Flora
Subject: Re: [PATCH] drm/amd/powerplay: move maximum sustainable clock
retrieving to .hw_init
[AMD Public Use]
From: Felix Kuehling
[ Upstream commit 90ca78deb004abe75b5024968a199acb96bb70f9 ]
This fixes an intermittent bug where a root PD clear operation still in
progress could overwrite a PDE update done by the CPU, resulting in a
VM fault.
Fixes: 108b4d928c03 ("drm/amd/amdgpu: Update VM function
From: chen gong
[ Upstream commit cbd2d08c7463e78d625a69e9db27ad3004cbbd99 ]
[Problem description]
1. Boot up picasso platform, launches desktop, Don't do anything (APU enter
into "gfxoff" state)
2. Remote login to platform using SSH, then type the command line:
sudo su -c "echo manual
From: limingyu
[ Upstream commit 6f81b2d047c59eb77cd04795a44245d6a52cdaec ]
For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1),
the amdgpu will expose pp_num_states to the /sys directory.
In this moment, read the pp_num_states file will excute the
amdgpu_get_pp_num_states func. In
From: Christian König
[ Upstream commit 82c416b13cb7d22b96ec0888b296a48dff8a09eb ]
The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.
To fix this refactor the
From: "Leo (Hanghong) Ma"
[ Upstream commit 650e723cecf2738dee828564396f3239829aba83 ]
[Why]
For MST case: when update_config is called to disable a stream,
this clears the settings for all the streams on that link.
We should only clear the settings for the stream that was disabled.
[How]
From: Felix Kuehling
[ Upstream commit 39b3128d7ffd44e400e581e6f49e88cb42bef9a1 ]
Releasing the AMDGPU BO ref directly leads to problems when BOs were
exported as DMA bufs. Releasing the GEM reference makes sure that the
AMDGPU/TTM BO is not freed too early.
Also take a GEM reference when
From: Evan Quan
[ Upstream commit f4fcfa4282c1a1bf51475ebb0ffda623eebf1191 ]
Since gfxoff should be disabled first before trying to access those
GC registers.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Evan Quan
[ Upstream commit 1fe48ec08d9f2e26d893a6c05bd6c99a3490f9ef ]
As this is already properly handled in amdgpu_gfx_off_ctrl(). In fact,
this unnecessary cancel_delayed_work_sync may leave a small time window
for race condition and is dangerous.
Signed-off-by: Evan Quan
From: Roman Li
[ Upstream commit 80797dd6f1a525d1160c463d6a9f9d29af182cbb ]
[Why]
Wait counter is not being reset for each pipe.
[How]
Move counter reset into pipe loop scope.
Signed-off-by: Roman Li
Reviewed-by: Zhan Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Alex Deucher
From: Aurabindo Pillai
[ Upstream commit e6142dd511425cb827b5db869f489eb81f5f994d ]
[why]
During hotplug, a DP port may be connected to the sink through
passive adapter which does not support DPCD reads. Issuing reads
without checking for this condition will result in errors
[how]
Ensure the
From: Tom St Denis
commit 975f543e7522e17b8a4bf34d7daeac44819aee5a upstream.
On my raven1 system (rev c6) with VBIOS 113-RAVEN-114 GFXOFF is
not stable (resulting in large block tiling noise in some applications).
Disabling GFXOFF via the quirk list fixes the problems for me.
Signed-off-by:
From: Simon Ser
commit 626bf90fe03fa080d8df06bb0397c95c53ae8e27 upstream.
This patch adds a basic cursor check when an atomic test-only commit is
performed. The position and size of the cursor plane is checked.
This should fix user-space relying on atomic checks to assign buffers to
planes.
From: Felix Kuehling
[ Upstream commit 90ca78deb004abe75b5024968a199acb96bb70f9 ]
This fixes an intermittent bug where a root PD clear operation still in
progress could overwrite a PDE update done by the CPU, resulting in a
VM fault.
Fixes: 108b4d928c03 ("drm/amd/amdgpu: Update VM function
From: chen gong
[ Upstream commit cbd2d08c7463e78d625a69e9db27ad3004cbbd99 ]
[Problem description]
1. Boot up picasso platform, launches desktop, Don't do anything (APU enter
into "gfxoff" state)
2. Remote login to platform using SSH, then type the command line:
sudo su -c "echo manual
From: Sung Lee
[ Upstream commit 1dfedb39d38f813357885e19badd1971c17f79a7 ]
[WHY]
If mode is not supported, pipe split should not be disabled.
This may cause more modes to fail.
[HOW]
Check for mode support before disabling pipe split.
This commit was previously reverted as it was thought to
From: Paul Hsieh
[ Upstream commit 7fc5c319efceaed1a23b7ef35c333553ce39fecf ]
[Why]
Driver already get display clock from SMU base on MHz, but driver read
again and mutiple 1000 cause wait loop value is overflow.
[How]
remove coding error
Signed-off-by: Paul Hsieh
Reviewed-by: Eric Yang
From: Dale Zhao
[ Upstream commit 2a28fe92220a116735ef45939b7edcfee83cc6b0 ]
[Why]:
Renoir's pipe VM flags are not correctly updated if pipe strategy has
changed during some scenarios. It will result in watermarks mistakenly
calculation, thus underflow and garbage appear.
[How]:
Correctly
From: Alvin Lee
[ Upstream commit a1a0e61f3c43c610f0a3c109348c14ce930c1977 ]
[Why]
New formula + cursor change causing underflow
on certain configs
[How]
Rever to old formula
Signed-off-by: Alvin Lee
Reviewed-by: Yongqiang Sun
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher
From: Christian König
[ Upstream commit 82c416b13cb7d22b96ec0888b296a48dff8a09eb ]
The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.
To fix this refactor the
From: Dmytro Laktyushkin
[ Upstream commit d5bef51f084fccafa984b114ff74a01a64a0e2e3 ]
This prevents dpcd access on virtual links.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: limingyu
[ Upstream commit 6f81b2d047c59eb77cd04795a44245d6a52cdaec ]
For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1),
the amdgpu will expose pp_num_states to the /sys directory.
In this moment, read the pp_num_states file will excute the
amdgpu_get_pp_num_states func. In
From: Joshua Aberback
[ Upstream commit 868149c9a072cbdc22a73ce25a487f9fbfa171ef ]
[Why]
The HUBBUB watermark registers are in an area that cannot be power
gated, but the HUBP copies of the watermark values are in areas that can
be power gated. When we power on a pipe, it will not automatically
On Mon, Jun 8, 2020 at 6:53 AM Evan Quan wrote:
>
> Before counting the OD percent into max power limit margin.
>
> Change-Id: I83b24d614e07fbc5eac41ff7cd668a1c2f33c6b2
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 +++-
From: Sean Paul
Since the logs protected by these checks specifically target syslog,
use the new drm_debug_syslog_enabled() call to avoid triggering
these prints when only trace is enabled.
Signed-off-by: Sean Paul
Changes in v5:
-Added to the set
---
On Mon, Jun 8, 2020 at 10:17 AM Dan Carpenter wrote:
>
> These lines are a part of the if statement and they are supposed to
> be indented one more tab.
>
> Signed-off-by: Dan Carpenter
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
> 1 file
On Fri, Jun 5, 2020 at 7:04 AM Evan Quan wrote:
>
> 'UVD' is a HW engine name for Vega20 and before ASICs.
> For newer ASICs, the similar engine is named as 'VCN'.
>
> Change-Id: I5f1b9500ed5d35e395a5da32b81a78eb87bffc68
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
>
On Fri, Jun 5, 2020 at 7:02 AM Evan Quan wrote:
>
> Helpful for error diagnostic.
>
> Change-Id: I983ca308a2ee6ed11e16ec59ad97040d98b90512
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 118 +++--
> 1 file
On Fri, Jun 5, 2020 at 1:38 PM Denis Efremov wrote:
>
> Use kvfree() instead of kfree() to free coeff in build_regamma()
> because the memory is allocated with kvzalloc().
>
> Fixes: e752058b8671 ("drm/amd/display: Optimize gamma calculations")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Denis
Am 2020-06-08 um 3:41 p.m. schrieb Alex Deucher:
> No need to do it again.
>
> Signed-off-by: Alex Deucher
Acked-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>
On Fri, May 29, 2020 at 12:58 PM John Hubbard wrote:
>
> On 2020-05-28 23:49, Souptick Joarder wrote:
> ...
> >> This is what case 3 was *intended* to cover, but it looks like case 3
> >> needs to
> >> be written a little better. I'll attempt that, and Cc you on the actual
> >> patch
> >> to
Am 08.06.20 um 21:41 schrieb Alex Deucher:
No need to do it again.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
No need to do it again.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1df28b7bf22e..539010798116 100644
---
On Mon, 2020-06-08 at 20:49 +0300, Dan Carpenter wrote:
> On Mon, Jun 08, 2020 at 10:16:27AM -0700, Joe Perches wrote:
> > On Mon, 2020-06-08 at 17:16 +0300, Dan Carpenter wrote:
> > > These lines are a part of the if statement and they are supposed to
> > > be indented one more tab.
> > >
> > >
On Mon, 2020-06-08 at 17:16 +0300, Dan Carpenter wrote:
> These lines are a part of the if statement and they are supposed to
> be indented one more tab.
>
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
> 1 file changed, 3 insertions(+), 3
On Mon, Jun 08, 2020 at 10:16:27AM -0700, Joe Perches wrote:
> On Mon, 2020-06-08 at 17:16 +0300, Dan Carpenter wrote:
> > These lines are a part of the if statement and they are supposed to
> > be indented one more tab.
> >
> > Signed-off-by: Dan Carpenter
> > ---
> >
Eh sorry. It is merged, I was looking at wrong branch.
Regards,
Nirmoy
On 6/8/20 7:13 PM, Nirmoy wrote:
Hi Christian,
I realized we are still missing this patch while reading dmesg of
https://gitlab.freedesktop.org/drm/amd/-/issues/1158
Hi Christian,
I realized we are still missing this patch while reading dmesg of
https://gitlab.freedesktop.org/drm/amd/-/issues/1158
Regards,
Nirmoy
On 2/28/20 4:24 PM, Li, Dennis wrote:
[AMD Public Use]
Looks good to me
Test-by: Dennis Li mailto:dennis...@amd.com>>
Best Regards
[AMD Public Use]
Acked-by: Alex Deucher
From: Quan, Evan
Sent: Monday, June 8, 2020 6:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
; Cui, Flora
Subject: [PATCH] drm/amd/powerplay: move maximum sustainable clock retrieving
to
[AMD Public Use]
Reviewed-by: Alex Deucher
From: Liang, Prike
Sent: Monday, June 8, 2020 3:34 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liang, Prike
Subject: [PATCH] drm/amdgpu/soc15: fix nullptr issue in soc15_read_register()
On Mon, Jun 08, 2020 at 02:57:17AM +0200, Ahmed S. Darwish wrote:
> A sequence counter write side critical section must be protected by some
> form of locking to serialize writers. If the serialization primitive is
> not disabling preemption implicitly, preemption has to be explicitly
> disabled
The comments say that the "sn" buffer is used to hold a 16-digit HEX
string so the buffer needs to be at least 17 characters to hold the
NUL terminator.
Fixes: 81a16241114b ("drm/amdgpu: Add unique_id and serial_number for Arcturus
v3")
Signed-off-by: Dan Carpenter
---
These lines are a part of the if statement and they are supposed to
be indented one more tab.
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Thanks much Alex for responding.
On Thursday, May 28, 2020, 04:29:16 PM EDT, Alex Deucher wrote:
>> I ask because I want to be able to run a system that is sometimes headless
>> and sometimes not. And I'd like to be able to access a current X session
>> (either logged in or at the login
Before counting the OD percent into max power limit margin.
Change-Id: I83b24d614e07fbc5eac41ff7cd668a1c2f33c6b2
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Use the cached max/current power limit and move the input check
to the top layer.
Change-Id: Iefc7a89b871ce20422c2e70b8cd7ac85a0a7beba
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++--
2
Also cache the current and max power limits.
Change-Id: Ida2ce964736bee2e558522441d3505f84c4e00f4
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 49 -
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 +
Instead of hard coding it as SMU_POWER_SOURCE_AC.
Change-Id: I57066b2c206f8e1e2276f959ff2704dcbe6e5d77
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
Minor code cleanup.
Change-Id: I56a56ebe4a86e7fca5de02d41928f533dda4d185
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 --
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 +--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 ---
Use the cached max/current power limit for other cases except
.late_init.
Change-Id: Ia4c063207faf051db27be1956f40554913c31c3b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +++
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 6 +-
Drop unused APIs, variables and argument.
Change-Id: I59c99de30bf3fa0e5ed058aaa8ab95d0a9c748aa
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 4 +--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 20 ---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 35
Since DAL settings come between .hw_init and .late_init of SMU. And
DAL needs to know the maximum sustainable clocks.
Change-Id: I0702b7332a0d7c0b29dfdf4999c18efb588b8862
Signed-off-by: Evan Quan
Reported-by: Flora Cui
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +--
1
Am 08.06.20 um 06:59 schrieb Qingqing Zhuo:
From: Rodrigo Siqueira
When we want to use float point operation on Linux
we need to use within special kernel protection
(`kernel_fpu_{begin,end}()`.), otherwise the kernel
can clobber userspace FPU register state. For detecting
these issues we use
[AMD Official Use Only - Internal Distribution Only]
Regards the gpu info inquire failed during start X, have sent a following fix
for the issue.
drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base
accessing
> -Original Message-
> From: Liang, Prike
> Sent:
The failed case is no SDMA1 IP for Renoir discovery table while in accessing
SDMA1 reg base,
thus need have nullptr test for soc15_read_register invoked in MMR addres space
inqure opt.
Signed-off-by: Prike.Liang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+),
A sequence counter write side critical section must be protected by some
form of locking to serialize writers. If the serialization primitive is
not disabling preemption implicitly, preemption has to be explicitly
disabled before entering the sequence counter write side critical
section.
The
[AMD Official Use Only - Internal Distribution Only]
According to reg_offset assignment in amdgpu_discovery_reg_base_init() the
reg_offset is calculated as IP base address pointer therefore PWR IP base
should be map to adev->reg_offset[SMUIO_HWIP][0] + 1. Moreover, not sure
whether can
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