Re: [PATCH] drm/amd/powerplay: widely share the API for data table retrieving

On Thu, Jul 16, 2020 at 1:12 AM Evan Quan wrote: > > Considering the data table retrieving can be more widely shared, > amdgpu_atombios.c is the right place. > > Change-Id: Id89476c14709b5676bbf043371a27f27b94a58ed > Signed-off-by: Evan Quan Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/a

RE: [PATCH] drm/amdgpu: load asd for sienna cichlid

[AMD Public Use] Reviewed-by: Hawking Zhang Regards, Hawking From: Clements, John Sent: Friday, July 17, 2020 11:04 To: amd-gfx list ; Zhang, Hawking Subject: [PATCH] drm/amdgpu: load asd for sienna cichlid [AMD Public Use] Submitting patch to enable ASD loading for Sienna Cichlid

RE: [PATCH] drm/amdgpu: enable xgmi support for sienna cichlid

[AMD Public Use] Reviewed-by: Hawking Zhang Regards, Hawking From: Clements, John Sent: Friday, July 17, 2020 11:05 To: amd-gfx list ; Zhang, Hawking Subject: [PATCH] drm/amdgpu: enable xgmi support for sienna cichlid [AMD Public Use] Submitting patch to enable XGMI support for Sienna Cich

[PATCH] drm/amdgpu: enable xgmi support for sienna cichlid

[AMD Public Use] Submitting patch to enable XGMI support for Sienna Cichlid 0002-drm-amdgpu-enable-xgmi-support-for-sienna-cichlid.patch Description: 0002-drm-amdgpu-enable-xgmi-support-for-sienna-cichlid.patch ___ amd-gfx mailing list amd-gfx@lists.fr

[PATCH] drm/amdgpu: load asd for sienna cichlid

[AMD Public Use] Submitting patch to enable ASD loading for Sienna Cichlid 0001-drm-amdgpu-load-asd-for-sienna-cichlid.patch Description: 0001-drm-amdgpu-load-asd-for-sienna-cichlid.patch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://l

[PATCH v3 17/27] drm/amd/display: dce_opp: add DCE6 specific macros, functions

[Why] DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register [How] Add DCE6 specific macros definitions for OPP registers and masks DCE6 OPP macros will avoid buidin

[PATCH v3 25/27] drm/amd/display: create plane rotation property for Bonaire and later

[Why] DCE6 chipsets do not support HW rotation [How] rotation property is created for Bonaire and later Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm

[PATCH v3 12/27] drm/amd/display: dce_dmcu: add DCE6 specific macros, functions

[Why] DCE6 has no SMU_INTERRUPT_CONTROL register, but it's used for DCN10 and later [How] Add DCE6 specific macros definitions for DMCU registers and masks DCE6 DMCU macros will avoid buiding errors when using DCE6 headers There is no other change needed in dce_dcmu Signed-off-by: Mauro Rossi --

[PATCH v3 18/27] drm/amd/display: dce_transform: add DCE6 specific macros, functions

[Why] DCE6 has no SCL_MODE and no SCL_{HORZ,VERT}_FILTER_INIT registers DCE6 has no SCL_BOUNDARY_MODE bit in SCL_CONTROL register DCE6 has Line Buffer programming registers (DC_LB_MEMORY_SPLIT,DC_LB_MEM_SIZE) DCE6 DATA_FORMAT register has only INTERLEAVE_EN bit DCE6 has no Out Clamp Control program

[PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific functions

[Why] DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register DCE6 has no CRTC_LEGACY_REQUESTOR_EN bit in CRTC_START_LINE_CONTROL register DCE6 has no CRTC_CRC_CNTL register [How] Modify dce60_timing_generator_enable_advanced_request() function Add dce60_configure_crc() function and dce60_is_tg_ena

[PATCH v3 15/27] drm/amd/display: dce_link_encoder: add DCE6 specific macros, functions

[Why] DCE6 has no DP_DPHY_SCRAM_CNTL register [How] Add DCE6 specific macros definitions for LE registers DCE6 LE macros will avoid buiding errors when using DCE6 headers Add dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2() w/o Scramble Control programming Add dce60_set_dp_phy_pattern_passthro

[PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7)

v7: add SCL_HORZ_FILTER_INIT regs --- .../gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 16 .../amd/include/asic_reg/dce/dce_6_0_sh_mask.h | 12 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/

[PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2)

[Why] hw_factory.c requires changes for DCE6 support [How] DCE6 targets added replicating and adapting existing DCE8 implementation. (v2) changes due to following commit: 91db931 ("drm/amd/display: refactor gpio to allocate hw_container in constructor") Signed-off-by: Mauro Rossi --- driv

[PATCH v3 02/27] drm/amd/display: add asics info for SI parts

[Why] Asic info for SI parts need to be preliminarly added [How] Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL Tree path: ./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h Signed-off-by: Mauro Rossi --- .../gpu/drm/amd/display/include

[PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions

[Why] DCE6 has no bottom_pipe and no Blender HW DCE6 needs 'blank_target' set to false in order to turn on the display DCE6 has a specific dce60_pipe_control_lock() fuction that is a no op [How] Add DCE6 specific functions with needed private dce60_* dependent fuctions Comment DCE6 specific CTRC p

[PATCH v3 16/27] drm/amd/display: dce_mem_input: add DCE6 specific macros, functions

[Why] DCE6 has DPG_PIPE_ARBITRATION_CONTROL3 register for Line Buffer watermark selection DCE6 has STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK mask for Stutter watermark selection DCE6 has NB_PSTATE_CHANGE_WATERMARK_MASK mask for North Bridge watermark selection DCE6 has no GRPH_MICRO_TILE_MODE mas

[PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6)

[Why] With all DCE6 specific macros, register, masks in place dce60_resource.c may use them and become independent from DCE8 headers [How] (v1) Changelog: - use DCE6 headers for registers and masks, remove the DC8 headers - remove 7th Display Controller/Encoder register instances (DCE6 has only 6)

[PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific macros, functions

[Why] DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE register [How] Add DCE6 specific macros definitions for AUD masks DCE6 AUD macros will avoid buiding errors when using DCE6 headers Add dce60_aud_wall_dto_setup() w/o 512*Fs programming Use dce60_aud_wall_dto_setup() i

[PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6)

From: Alex Deucher To help with the DC port. v2: add missing masks, add additional registers v3: more updates v4: fix accidently dropped changes v5: add missing nb pstate mask v6: add vblank, vline masks Signed-off-by: Alex Deucher --- .../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 62 ++

[PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4)

[Why] amdgpu_dm.c requires changes for SI chipsets init and irq handlers registration [How] SI support: load_dmcu_fw(), amdgpu_dm_initialize_drm_device(), dm_early_init() Add DCE6 specific dce60_register_irq_handlers() function (v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is requ

[PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2)

[Why] amdgpu_device.c requires changes for SI chipsets support si.c require changes for Display Manager IP block enabling [How] amdgpu_device.c: add SI families in amdgpu_device_asic_has_dc_support() si.c: changes in si_set_ip_blocks() for Display Manager IP blocks enablement (v1) NOTE: As per Ka

[PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init

[Why] DCE6 has specific SCL_HORZ_FILTER_INIT_{LUMA_RGB,CHROMA} registers In DCE6 h_init_luma and h_init_chroma initialization is required Some DCE6 specific SCL_{HORZ,VERT}_FILTER_CONTROL masks were not listed [How] Add the registers and masks in dce_transform.h Add DCE6 specific struct sclh_ratio

[PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2)

[Why] All DCE6 specific code changes are guarded by CONFIG_DRM_AMD_DC_SI Kconfig option [How] (v1) CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled (v2) Hainan is not supported, description updated accordingly Tested with HD7750 (Cape Verde) and HD7950 (Tahiti)

[PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock

[Why] kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110 [How] DCE6 set .cursor_lock = dce60_pipe_control_lock Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers

[PATCH v3 14/27] drm/amd/display: dce_ipp: add DCE6 specific macros, functions

[Why] DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL register [How] Add DCE6 specific macros definitions for IPP masks DCE6 IPP macros will avoid buiding errors when using DCE6 headers Add dce60_ipp_set_degamma() function w/o Cursor2 Degamma programming Use dce60_ipp_set_degamma()

[PATCH v3 13/27] drm/amd/display: dce_hwseq: add DCE6 specific macros, functions

[Why] DCE6 has no BLND_CONTROL register for Blender HW programming DCE6 has no BLND_V_UPDATE_LOCK register for Pipe Locking [How] Add DCE6 specific macros definitions for HWSEQ registers and masks DCE6 HWSEQ macros will avoid buiding errors when using DCE6 headers Add dce60_pipe_control_lock() stu

[PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2)

(v1) Changelog [Why] After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions" dc/clk_mgr requires these changes to add SI parts support Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */ that would cause kernel freeze [How] Add case statement for FAMILY_SI chipsets (v2)

[PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2)

[Why] resource_parse_asic_id() and dc_create_resource_pool() are missing SI/DCE6 cases [How] SI/DCE6 cases support added using existing DCE8 implementation as a reference (v2) updated due to following kernel 5.2 commit: d9673c9 ("drm/amd/display: Pass init_data into DCN resource creation")

[PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6

[Why] command_table_helper.c requires changes for DCE6 support [How] DCE6 targets added replicating and adapting the existing DCE8 implementation. Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 + .../display/dc/bios/command_table_helper.c| 8 + .../dis

[PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4)

[Why] irq service requires changes for DCE6 support [How] (v1) DCE6 targets are added replicating existing DCE8 implementation. due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks, dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h (v2) DCE6 headers used add

[PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b)

[Why] DCE6 chipsets have a lot in common with DCE8, let's start from this [How] DCE6 targets are added replicating existing DCE8 implementation. NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h initial build prototype due to missing DCE6 macros/registers/masks DCE6 specif

[PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64

[Why] Issue in the Mouse cursor size in Linux Desktop Environments [How] In DCE6 dc->caps.max_cursor_size need to be set as 64 instead of 128 Signed-off-by: Mauro Rossi --- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --

[no subject]

The series adds SI support to AMD DC Changelog: [RFC] Preliminar Proof Of Concept, with DCE8 headers still used in dce60_resources.c [PATCH v2] Rebase on amd-staging-drm-next dated 17-Oct-2018 [PATCH v3] Add support for DCE6 specific headers, ad hoc DCE6 macros, funtions and fixes, rebase on cu

Re: [PATCH v4] drm/amdgpu: fix system hang issue during GPU reset

Hi, Checkpatch complains about the following (ignoring long lines), when your patch is applied with "git am". I suggest fixing "ERROR" types first: "if(" --> "if (", as is the kernel style. $(GIT_CHECKPATCH+=" --ignore LONG_LINE,LONG_LINE_STRING,LONG_LINE_COMMENT"; git am /tmp/\[PATCH\ v4\]\ drm

Re: Failed to find memory space for buffer eviction

Am 2020-07-16 um 2:58 a.m. schrieb Christian König: > Am 15.07.20 um 17:14 schrieb Felix Kuehling: >> Am 2020-07-15 um 5:28 a.m. schrieb Christian König: >>> Am 15.07.20 um 04:49 schrieb Felix Kuehling: Am 2020-07-14 um 4:28 a.m. schrieb Christian König: > Hi Felix, > > yes I alre

[PATCH 2/2] drm/amdgpu/vcn: merge shared memory into vcpu

Merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 18 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 - 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vc

[PATCH 1/2] Revert "drm/amdgpu/vcn: add shared memory restore after wake up from sleep."

This reverts commit 41fd4db3eca29d10222f164cc1d56f60e3da97b8. To merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 28 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 - 2 files changed, 1 insert

Re: [PATCH v6 03/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing)

Hi, Yi, On Mon, Jul 13, 2020 at 08:25:20PM -0700, Liu, Yi L wrote: > > From: Fenghua Yu > > Sent: Tuesday, July 14, 2020 7:48 AM > > From: Ashok Raj Thank you for your comments! But I think we don't need to update this patch because the current text is better than suggested changes. I would ra