[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
-Original Message-
From: Quan, Evan
Sent: Tuesday, August 25, 2020 10:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth
; Quan, Evan
Subject: [PATCH] drm/amd/pm: correct the
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Jiansong Chen
-Original Message-
From: Zhou1, Tao
Sent: Tuesday, August 25, 2020 11:20 AM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Chen, Jiansong (Simon) ; Gui, Jack
Cc: Zhou1, Tao
Subject: [PATCH]
asd is not ready for some ASICs in early stage, and psp->asd_fw is more generic
than ASIC name in the check
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
Do the maths in celsius degree. This can fix the issues caused
by the changes below:
drm/amd/pm: correct Vega20 swctf limit setting
drm/amd/pm: correct Vega12 swctf limit setting
drm/amd/pm: correct Vega10 swctf limit setting
Change-Id: Ia49936240106a3172d10ffc44e51d3c9ba00763d
Signed-off-by:
[AMD Public Use]
amd-gfx-bounces distribution list is not correct. Simply correct to amd-gfx DL
in mail TO line.
Regards,
Guchun
-Original Message-
From: Yang, Stanley
Sent: Tuesday, August 25, 2020 9:53 AM
To: Chen, Guchun ; amd-gfx-boun...@lists.freedesktop.org
Cc: Zhang, Hawking ;
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Jiansong Chen
-Original Message-
From: Wang, Kevin(Yang)
Sent: Monday, August 24, 2020 8:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Deucher, Alexander
; Chen, Jiansong (Simon) ;
Wang, Kevin(Yang) ; Chen,
Applied. Thanks!
Alex
On Mon, Aug 24, 2020 at 5:33 PM Alex Dewar wrote:
>
> Issue identified with Coccinelle.
>
> Signed-off-by: Alex Dewar
> ---
> .../drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git
Issue identified with Coccinelle.
Signed-off-by: Alex Dewar
---
.../drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
On Mon, Aug 24, 2020 at 2:33 PM Alex Deucher wrote:
>
> On Mon, Aug 24, 2020 at 7:57 AM Samuel Pitoiset
> wrote:
> >
> > A trap handler can be used by userspace to catch shader exceptions
> > like divide by zero, memory violations etc.
> >
> > On GFX6-GFX8, the registers used to configure
On Mon, Aug 24, 2020 at 7:57 AM Samuel Pitoiset
wrote:
>
> A trap handler can be used by userspace to catch shader exceptions
> like divide by zero, memory violations etc.
>
> On GFX6-GFX8, the registers used to configure TBA/TMA aren't
> privileged while on GFX9+ they are per VMID and
On Mon, Aug 24, 2020 at 12:38 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
>
> This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
> Newly released sdma fw (51.52) provides a fix for the issue.
>
> Signed-off-by:
On Mon, Aug 24, 2020 at 12:38 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
>
> gfxoff is temporarily disabled for navy_flounder,
> since at present the feature has broken some basic
> amdgpu test.
>
> Signed-off-by: Jiansong Chen
On Mon, Aug 24, 2020 at 12:37 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
>
> This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
> Newly released sdma fw (51.52) provides a fix for the issue.
>
> Signed-off-by:
On Mon, Aug 24, 2020 at 12:37 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
>
> gfxoff is temporarily disabled for navy_flounder,
> since at present the feature has broken some basic
> amdgpu test.
>
> Signed-off-by: Jiansong Chen
On Mon, Aug 24, 2020 at 12:36 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
>
> gfxoff is temporarily disabled for navy_flounder,
> since at present the feature has broken some basic
> amdgpu test.
>
> Signed-off-by: Jiansong Chen
On Mon, Aug 24, 2020 at 12:36 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
>
> This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
> Newly released sdma fw (51.52) provides a fix for the issue.
>
> Signed-off-by:
SET_SH_REG won't work with CP register shadowing. You need to use
WRITE_DATA or WREG32.
Marek
On Mon, Aug 24, 2020 at 7:57 AM Samuel Pitoiset
wrote:
> A trap handler can be used by userspace to catch shader exceptions
> like divide by zero, memory violations etc.
>
> On GFX6-GFX8, the
Series is Acked-by: Nirmoy Das
On 8/24/20 6:15 PM, Alex Deucher wrote:
This allows us to add asic specific workarounds for atom
asic init while keeping the adev specifics out of the
atombios parser code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20
The KFD part looks good to me, other than the SDMA comment that Guchun
pointed out. With that fixed this patch is
Acked-by: Felix Kuehling
Thanks,
Felix
Am 2020-08-24 um 6:33 a.m. schrieb Stanley.Yang:
> The ctx->features are new RAS implementation which
> is only available for Vega20 and
From: Jiansong Chen
[ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
Newly released sdma fw (51.52) provides a fix for the issue.
Signed-off-by: Jiansong Chen
Reviewed-by: Kenneth Feng
Reviewed-by: Tao Zhou
Acked-by:
From: Evan Quan
[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
From: Evan Quan
[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]
Correct the cached smu feature state on pp_features sysfs
setting.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Anthony Koo
[ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ]
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be
From: Jiansong Chen
[ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
Newly released sdma fw (51.52) provides a fix for the issue.
Signed-off-by: Jiansong Chen
Reviewed-by: Kenneth Feng
Reviewed-by: Tao Zhou
Acked-by:
From: Jiansong Chen
[ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.
Signed-off-by: Jiansong Chen
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
Signed-off-by:
From: Guchun Chen
[ Upstream commit 1a68d96f81b8e7eb2a121fbf9abf9e5974e58832 ]
When unloading driver by "modprobe -r amdgpu", one NULL pointer
dereference bug occurs in ras debugfs releasing. The cause is the
duplicated debugfs_remove, as drm debugfs_root dir has been cleaned
up already by
From: Huang Rui
[ Upstream commit 34174b89bfa495bed9cddcc504fb38feca90fab7 ]
Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Felix
From: Jiansong Chen
[ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.
Signed-off-by: Jiansong Chen
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
Signed-off-by:
From: Evan Quan
[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
From: Evan Quan
[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]
Correct the cached smu feature state on pp_features sysfs
setting.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Anthony Koo
[ Upstream commit e4ed4dbbc8383d42a197da8fe7ca6434b0f14def ]
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.
2. We
From: Anthony Koo
[ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ]
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be
From: Jiansong Chen
[ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.
Signed-off-by: Jiansong Chen
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
Signed-off-by:
From: Guchun Chen
[ Upstream commit 1a68d96f81b8e7eb2a121fbf9abf9e5974e58832 ]
When unloading driver by "modprobe -r amdgpu", one NULL pointer
dereference bug occurs in ras debugfs releasing. The cause is the
duplicated debugfs_remove, as drm debugfs_root dir has been cleaned
up already by
From: Huang Rui
[ Upstream commit 34174b89bfa495bed9cddcc504fb38feca90fab7 ]
Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Felix
From: Jiansong Chen
[ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
Newly released sdma fw (51.52) provides a fix for the issue.
Signed-off-by: Jiansong Chen
Reviewed-by: Kenneth Feng
Reviewed-by: Tao Zhou
Acked-by:
From: Anthony Koo
[ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ]
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be
From: Evan Quan
[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
From: Evan Quan
[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]
Correct the cached smu feature state on pp_features sysfs
setting.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Anthony Koo
[ Upstream commit e4ed4dbbc8383d42a197da8fe7ca6434b0f14def ]
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.
2. We
This allows us to add asic specific workarounds for atom
asic init while keeping the adev specifics out of the
atombios parser code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it. It's also DCN, not DCE, so remove it from the
DCE12 header.
No functional change.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
Nothing to do for this family.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 54e941e0db60..33a6d2d5fc16 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
We need to restore some registers prior to running asic
init to work around a firmware bug.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 35 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 2 ++
drivers/gpu/drm/amd/amdgpu/soc15.c| 7 ++
3
Nothing to do for this family.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index eaa2f071b139..455d5e366c69 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
Nothing to do for this family.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 7e71ffbca93d..03ff8bd1fee8 100644
---
This callback can be used by asics that need to
do something special prior to calling atom asic init.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
Nothing to do for this family.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index a92880c67841..9bcd0eebc6d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
On Mon, Aug 24, 2020 at 4:04 AM Evan Quan wrote:
>
> As it is confirmed to have no race condition during hw setup.
>
For patches 1,2 please provide details as to why we know it is safe to
drop these. For patches 3,4:
Reviewed-by: Alex Deucher
> Change-Id:
On 2020-08-24 11:11 a.m., Bhawanpreet Lakha wrote:
dpcs reg are missing for dcn3 link encoder regs list, so add them.
Also remove
DPCSTX_DEBUG_CONFIG and RDPCSTX_DEBUG_CONFIG as they are unused and
cause compile errors for dcn3
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Nicholas
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher
From: Bhawanpreet Lakha
Sent: Monday, August 24, 2020 11:11 AM
To: Deucher, Alexander
Cc: Siqueira, Rodrigo ; Kazlauskas, Nicholas
; amd-gfx@lists.freedesktop.org
; Lakha, Bhawanpreet
dpcs reg are missing for dcn3 link encoder regs list, so add them.
Also remove
DPCSTX_DEBUG_CONFIG and RDPCSTX_DEBUG_CONFIG as they are unused and
cause compile errors for dcn3
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 2 --
Applied. Thanks!
Alex
On Sun, Aug 23, 2020 at 11:00 PM Quan, Evan wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks for fixing this. The patch is reviewed-by: Evan Quan
>
>
> BR
> Evan
> -Original Message-
> From: Randy Dunlap
> Sent: Monday, August 24, 2020
On Sat, Aug 22, 2020 at 5:02 AM Youling Tang wrote:
>
> Remove duplicate semicolons at the end of line.
>
> Signed-off-by: Youling Tang
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
> drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 +-
[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Felix
Kuehling
Sent: Monday, August 24, 2020 10:21 AM
To: amd-gfx@lists.freedesktop.org
Cc: Lin, Amber ; Shikre, Divya
Subject: [PATCH 1/2]
No need to use a function pointer because the implementation is not
ASIC-specific. This fixes missing support due to a missing function
pointer on Arcturus.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 1 -
No need to use a function pointer because the implementation is not
ASIC-specific.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 1 -
From: Kevin Wang
v1:
the C type "unsigned long" size is 32bit on 32bit system,
it will cause code logic error, so replace it with "uint64_t".
v2:
remove duplicate cast operation.
Signed-off-by: Kevin
Suggest-by: Jiansong Chen
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 10
[AMD Official Use Only - Internal Distribution Only]
Indeed, that's not necessary.
thanks.
Best Regards,
Kevin
From: Chen, Jiansong (Simon)
Sent: Monday, August 24, 2020 7:59 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ;
[AMD Official Use Only - Internal Distribution Only]
Good point, but I wonder whether the outmost uint64_t cast is necessary?
Regards,
Jiansong
-Original Message-
From: amd-gfx On Behalf Of Kevin
Sent: Monday, August 24, 2020 4:59 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher,
A trap handler can be used by userspace to catch shader exceptions
like divide by zero, memory violations etc.
On GFX6-GFX8, the registers used to configure TBA/TMA aren't
privileged while on GFX9+ they are per VMID and privileged,
so that only the KMD can configure them.
This introduces a new
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Jiansong Chen
Sent: Monday, August 24, 2020 18:59
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Chen, Jiansong (Simon)
Subject: [PATCH] drm/amdgpu/gfx10: refine mgcg setting
1. enable
1. enable ENABLE_CGTS_LEGACY to fix specviewperf11 random hang.
2. remove obsolete RLC_CGTT_SCLK_OVERRIDE workaround.
Signed-off-by: Jiansong Chen
Change-Id: Id52d45ba48159c5e1c9ecf658c5b52f7fc72eb65
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++
1 file changed, 2 insertions(+), 4
From: Kevin Wang
the C type "unsigned long" size is 32bit on 32bit system,
it will cause code logic error, so replace it with "uint64_t".
Signed-off-by: Kevin
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 9 +++--
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 9
Drop unneeded "ret".
Change-Id: If5eabb1e96153133a833d0e5b1dca9c0f0928891
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 22 +--
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
Either this was already performed in parent API. Or the table is
confirmed to exist.
Change-Id: Ie6778a5035749221e0f9d5ad977a0e56392771dd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 -
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 16
As it is confirmed to have no race condition during hw setup
and baco support checking.
Change-Id: I7078ac26ae71eb6c7cbf918a127adfc2f56acf7d
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 --
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2
As it is confirmed to have no race condition during hw setup.
Change-Id: I096d7ab0855ff59b0ecb56fd9d6d9946b3605fc8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 --
2 files changed, 6 deletions(-)
diff
On Sat, 22 Aug 2020 11:59:26 +0200
Michel Dänzer wrote:
> On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
> > On 2020-08-21 12:57 p.m., Michel Dänzer wrote:
> >> From: Michel Dänzer
> >>
> >> Don't check drm_crtc_state::active for this either, per its
> >> documentation in
From: Randy Dunlap
Fix Documentation errors for amdgpu.rst due to file rename (moved
to another subdirectory).
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -function hwmon
70 matches
Mail list logo
