[AMD Official Use Only - Internal Distribution Only]
Thanks. I just sent out a patch to address this.
BR
Evan
-Original Message-
From: amd-gfx On Behalf Of Dan Carpenter
Sent: Tuesday, August 25, 2020 6:24 PM
To: rex@amd.com
Cc: amd-gfx@lists.freedesktop.org
Subject: [bug report]
Suppress the warning below:
drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.c:274
phm_check_smc_update_required_for_display_configuration()
warn: signedness bug returning '(-22)'
Change-Id: If50e39fe401c16d981d917ef7d8d5ea81d6538df
Reported-by: Dan Carpenter
Signed-off-by: Evan
On 2020-08-25 10:34 a.m., Nirmoy wrote:
>
> On 8/25/20 4:18 PM, Alex Deucher wrote:
>> virtual display is non-atomic so report false to avoid checking
>
> With below nitpick fixed, Acked-by: Nirmoy Das
Another nitpick: "below" is not an adjective. It's a preposition or in
this case as an
Add support for reporting GPU reset events through SMI. KFD
would report both pre and post GPU reset events.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 30
Commit 2e26ccb119bd ("drm/radeon: prefer lower reference dividers")
fixed screen flicker for HP Compaq nx9420 but breaks other laptops like
Asus X50SL.
Turns out we also need to favor lower feedback dividers.
Users confirmed this change fixes the regression and doesn't regress the
original fix.
On Tue, Aug 25, 2020 at 11:53:25AM -0400, Alex Deucher wrote:
> On Tue, Aug 25, 2020 at 7:21 AM Dan Carpenter
> wrote:
> >
> > The values for "se_num" and "sh_num" come from the user in the ioctl.
> > They can be in the 0-255 range but if they're more than
> > AMDGPU_GFX_MAX_SE (4) or
On 2020-08-22 5:59 a.m., Michel Dänzer wrote:
On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
On 2020-08-21 12:57 p.m., Michel Dänzer wrote:
From: Michel Dänzer
Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:
* Hence drivers must
On Tue, Aug 25, 2020 at 7:21 AM Dan Carpenter wrote:
>
> The values for "se_num" and "sh_num" come from the user in the ioctl.
> They can be in the 0-255 range but if they're more than
> AMDGPU_GFX_MAX_SE (4) or AMDGPU_GFX_MAX_SH_PER_SE (2) then it results in
> an out of bounds read.
>
> I split
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 2020-08-24 9:43 a.m., Pekka Paalanen wrote:
> On Sat, 22 Aug 2020 11:59:26 +0200 Michel Dänzer
> wrote:
>> On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
>>> On 2020-08-21 12:57 p.m., Michel Dänzer wrote:
From: Michel Dänzer
On 8/25/20 4:18 PM, Alex Deucher wrote:
virtual display is non-atomic so report false to avoid checking
With below nitpick fixed, Acked-by: Nirmoy Das
virtual --> Virtual
Nirmoy
atomic state and other atomic things at runtime.
v2: squash into the sr-iov check
Signed-off-by: Alex
[AMD Public Use]
Acked-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, August 25, 2020 10:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: report DC not supported if virtual display
virtual display is non-atomic so report false to avoid checking
atomic state and other atomic things at runtime.
v2: squash into the sr-iov check
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
A trap handler can be used by userspace to catch shader exceptions
like divide by zero, memory violations etc.
On GFX6-GFX8, the registers used to configure TBA/TMA aren't
privileged and can be configured from userpace.
On GFX9+ they are per VMID and privileged, only the KMD can
configure them.
[AMD Public Use]
I can do that.
Alex
From: Chen, Guchun
Sent: Tuesday, August 25, 2020 10:13 AM
To: Alex Deucher ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu: report DC not supported if virtual display is
enabled
[AMD Public Use]
Why not merging it to the same line of SRIOV check?
if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display )
return false;
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, August 25, 2020 9:45 PM
To:
virtual display is non-atomic so report false to avoid checking
atomic state and other atomic things at runtime.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
On Tue, Aug 25, 2020 at 3:06 AM Samuel Pitoiset
wrote:
>
>
> On 8/24/20 11:32 PM, Alex Deucher wrote:
> > On Mon, Aug 24, 2020 at 2:33 PM Alex Deucher wrote:
> >> On Mon, Aug 24, 2020 at 7:57 AM Samuel Pitoiset
> >> wrote:
> >>> A trap handler can be used by userspace to catch shader exceptions
The values for "se_num" and "sh_num" come from the user in the ioctl.
They can be in the 0-255 range but if they're more than
AMDGPU_GFX_MAX_SE (4) or AMDGPU_GFX_MAX_SH_PER_SE (2) then it results in
an out of bounds read.
I split this function into to two to make the error handling simpler.
The values for "se_num" and "sh_num" come from the user in the ioctl.
They can be in the 0-255 range but if they're more than
AMDGPU_GFX_MAX_SE (4) or AMDGPU_GFX_MAX_SH_PER_SE (2) then it results in
an out of bounds read.
I split this function into to two to make the error handling simpler.
The values for "se_num" and "sh_num" come from the user in the ioctl.
They can be in the 0-255 range but if they're more than
AMDGPU_GFX_MAX_SE (4) or AMDGPU_GFX_MAX_SH_PER_SE (2) then it results in
an out of bounds read.
I split this function into to two to make the error handling simpler.
Hello Rex Zhu,
The patch 88b8dcbe21fd: "drm/amd/powerplay: add point check to avoid
NULL point hang." from Dec 11, 2015, leads to the following static
checker warning:
drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.c:274
[AMD Public Use]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Jiansong Chen
> Sent: Tuesday, August 25, 2020 3:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao ; Chen, Jiansong (Simon)
>
> Subject: [PATCH] drm/amdgpu: use MODE1 reset for navy_flounder by default
>
>
Switch default gpu reset method to MODE1 for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: I99b2d3ac04352142e288877f3b6c3138d0efd4bc
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
As these operations are performed in hardware setup and there
is actually no race conditions during this period considering:
1. the hardware setup is serial and cannnot be in parallel
2. all other operations can be performed only after hardware
setup complete.
V2: rich the commit log
Drop unneeded "ret".
Change-Id: If5eabb1e96153133a833d0e5b1dca9c0f0928891
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 22 +--
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git
Either this was already performed in parent API. Or the table is
confirmed to exist.
Change-Id: Ie6778a5035749221e0f9d5ad977a0e56392771dd
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 -
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |
As these operations are performed in hardware setup and there
is actually no race conditions during this period considering:
1. the hardware setup is serial and cannnot be in parallel
2. all other operations can be performed only after hardware
setup complete.
V2: rich the commit log
On 8/24/20 11:32 PM, Alex Deucher wrote:
On Mon, Aug 24, 2020 at 2:33 PM Alex Deucher wrote:
On Mon, Aug 24, 2020 at 7:57 AM Samuel Pitoiset
wrote:
A trap handler can be used by userspace to catch shader exceptions
like divide by zero, memory violations etc.
On GFX6-GFX8, the registers
On 8/24/20 8:17 PM, Marek Olšák wrote:
SET_SH_REG won't work with CP register shadowing. You need to use
WRITE_DATA or WREG32.
You are right, will fix.
Marek
On Mon, Aug 24, 2020 at 7:57 AM Samuel Pitoiset
mailto:samuel.pitoi...@gmail.com>> wrote:
A trap handler can be used by
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