[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Huang Rui
Sent: Wednesday, December 23, 2020 10:08 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Su, Jinzhou (Joe)
; Huang, Ray
Subject: [PATCH]
Don't open-code DIV_ROUND_UP() kernel macro.
Signed-off-by: Zheng Yongjun
---
drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 390a9621604a..a3aea5329712 100644
---
In line 24 "_AMDGPU_TRACE_H" is missing an underscore.
Signed-off-by: Chenyang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index
[AMD Public Use]
Hi Simon,
Another interim update: so far to me it looks like this is an issue if there's
fewer than 24 pixels left on the screen when moving the FB outside of the left
edge (e.g. with 300x300 FB size, it repros with X = -280). When this happens,
what looks like a boundary
[AMD Official Use Only - Internal Distribution Only]
Reviewed by Jane Jian
-Original Message-
From: Hawking Zhang
Sent: Tuesday, December 22, 2020 7:11 PM
To: amd-gfx@lists.freedesktop.org; Sierra Guiza, Alejandro (Alex)
; Jian, Jane
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu:
From: Michael Strauss
[ Upstream commit 3abad347c432b9f5904cfad40f417d5cff90300c ]
[Why]
New value breaks VSR on high refresh panels, reverting until a fix is developed
Signed-off-by: Michael Strauss
Signed-off-by: Sung Lee
Reviewed-by: Yongqiang Sun
Acked-by: Eryk Brol
Signed-off-by: Alex
From: Sung Lee
[ Upstream commit 901c1ec05ef277ce9d43cb806a225b28b3efe89a ]
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
does that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode
From: Bokun Zhang
[ Upstream commit de21e4aeb2b26128dcc5be1bcb2fafa73d041e51 ]
- When we are under SRIOV setup, the rev_id cannot be read
properly. Therefore, we will return default value for it
Signed-off-by: Bokun Zhang
Reviewed-by: Monk Liu
Signed-off-by: Alex Deucher
Signed-off-by:
From: Bas Nieuwenhuizen
[ Upstream commit b35ce7b364ec80b54f48a8fdf9fb74667774d2da ]
Silently accepting it could result in corruption.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Hawking Zhang
[ Upstream commit a9f5f98f796ee93a865b9886bf7cb694cf124eb5 ]
in case it is an invalid one
Signed-off-by: Hawking Zhang
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 13 +
1 file
From: Bokun Zhang
[ Upstream commit 3617e579eba427ed1f6b86050fe678623184db74 ]
- Issue:
In the original vcn3.0 code, it assumes that the VCN's
init_status is always 1, even after the MMSCH
updates the header.
This is incorrect since by default, it should be set to 0,
and MMSCH will
From: Bokun Zhang
[ Upstream commit de21e4aeb2b26128dcc5be1bcb2fafa73d041e51 ]
- When we are under SRIOV setup, the rev_id cannot be read
properly. Therefore, we will return default value for it
Signed-off-by: Bokun Zhang
Reviewed-by: Monk Liu
Signed-off-by: Alex Deucher
Signed-off-by:
From: Bokun Zhang
[ Upstream commit 25a35065c066496935217748b1662a7fcf26ed58 ]
- The original logic uses a counter based index assignment,
which is incorrect if we only assign VCN1 to this VF but no VCN0
The doorbell index is absolute, so we can calculate it by
using index variable i and
From: Kevin Wang
[ Upstream commit 71037bfc78bf63a6640792ace925741767fb6bfc ]
add missing clock gating informations in amdgpu_pm_info
1. AMD_CG_SUPPORT_VCN_MGCG
2. AMD_CG_SUPPORT_HDP_DS
3. AMD_CG_SUPPORT_HDP_SD
4. AMD_CG_SUPPORT_IH_CG
5. AMD_CG_SUPPORT_JPEG_MGCG
Signed-off-by: Kevin Wang
From: Marek Olšák
[ Upstream commit 4b60bb0dde1baf347540253f856c54bc908e525c ]
v2: squash in build fix
Acked-by: Alex Deucher
Signed-off-by: Marek Olšák
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 -
1 file changed, 4
From: Jiansong Chen
[ Upstream commit ef3b2987254035f9b869f70151b4220c34f2f133 ]
Toggle on/off gfxoff during video playback to fix gpu hang.
v2: change sequence to be more compatible with original code.
Signed-off-by: Jiansong Chen
Reviewed-by: James Zhu
Reviewed-by: Hawking Zhang
From: Eryk Brol
[ Upstream commit 886876ecf7f46917af8065bb574a669f19302f96 ]
[Why]
We want to trigger atomic check on connector when
DSC debugfs properties are changed. The previous
method was reverted because it accessed connector
properties unsafely and would also heavily
impact performance.
From: Dmytro Laktyushkin
[ Upstream commit 84aef2ab0977199784671295a07043191233d7c7 ]
Recout calculation does not corrrectly handle plane
clip rect that extends beyond the left most border
of stream source rect. This change adds handling by
truncating the invisible clip rect.
Signed-off-by:
From: Hugo Hu
[ Upstream commit 3a372bed1e337efa450d8288bc75cfc9237b7bad ]
[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.
[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink
From: Lewis Huang
[ Upstream commit e748b59fb74e8725c8774a4b0753fabba9de7b97 ]
[Why]
Driver keeps the invalid information cause report the
incorrect monitor which save in remote sink to OS
[How]
When connector type change from MST to non-MST,
stop the topology manager.
Signed-off-by: Lewis
From: Alvin Lee
[ Upstream commit 6f2239ccdfc04938dc35e67dd60191b2c05dfb63 ]
[Why]
When enabling PIP in Heaven, the PIP planes are VSYNC
flip and is also the top-most pipe. In this case GSL
will be disabled because we only check immediate flip
for the top pipe. However, the desktop planes are
From: Isabel Zhang
[ Upstream commit 685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2 ]
[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.
[How]
Any ASIC running DCN21 will by default
From: "Tao.Huang"
[ Upstream commit 585e7cedf304ce76410c922e632bef04fd316ead ]
[Why]
The C standard does not specify whether an enum is signed or unsigned.
In the function prototype, one of the argument is defined as an enum
but its declaration was unit32_t. Fix this by changing the function
From: Bas Nieuwenhuizen
[ Upstream commit b35ce7b364ec80b54f48a8fdf9fb74667774d2da ]
Silently accepting it could result in corruption.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Dennis Li
[ Upstream commit 22503d803dab174b7f038fc9886c225ef30ee95c ]
Instead of saving bad pages in amdgpu_ras_reset_gpu, it will reduce
the unnecessary calling of amdgpu_ras_save_bad_pages.
Signed-off-by: Dennis Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
From: Yifan Zhang
[ Upstream commit 0b08c54bb7a37047a3a006e36c2270ebc62fef7d ]
[Why]
Screen corruption on Navi10 card
[How]
Set system context in DCN only on Renoir
Tested-by: Matt Coffin
Acked-by: Alex Deucher
Signed-off-by: Yifan Zhang
Reviewed-by: Roman Li
Signed-off-by: Alex Deucher
From: Yifan Zhang
[ Upstream commit c0fb85ae02b62bded71110f44e8b0fe34f11260f ]
[why]
display S/G mode fails in Renoir
[how]
Setup system context in dm init.
Signed-off-by: Yifan Zhang
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
PCIE MMIO bar needs to be restored firstly after the reset event
triggers. So it's unable to access the registers to wait for response
from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that
moment.
Signed-off-by: Huang Rui
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 22
On Tue, Dec 22, 2020 at 9:55 PM Kazlauskas, Nicholas
wrote:
>
> On 2020-12-21 10:18 p.m., Zhan Liu wrote:
> > [Why]
> > Driver cannot change amdgpu framebuffer (afb) format while doing
> > page flip. Force system doing so will cause ioctl error, and result in
> > breaking several functionalities
On 2020-12-21 10:18 p.m., Zhan Liu wrote:
[Why]
Driver cannot change amdgpu framebuffer (afb) format while doing
page flip. Force system doing so will cause ioctl error, and result in
breaking several functionalities including FreeSync.
If afb format is forced to change during page flip,
On Fri, Dec 18, 2020 at 5:16 PM Bhawanpreet Lakha
wrote:
>
> From: Joshua Aberback
>
> We need these to support PSR on DCN302
>
> Signed-off-by: Joshua Aberback
> Signed-off-by: Bhawanpreet Lakha
Acked-by: Alex Deucher
> ---
> .../gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 13
On Sun, Dec 20, 2020 at 6:10 AM Markus Elfring wrote:
>
> From: Markus Elfring
> Date: Sat, 19 Dec 2020 18:30:56 +0100
>
> Two update suggestions were taken into account
> from static source code analysis.
>
Applied. Thanks!
Alex
> Markus Elfring (2):
> Return directly after a failed
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Hawking
Zhang
Sent: Tuesday, December 22, 2020 6:10 AM
To: amd-gfx@lists.freedesktop.org ; Sierra
Guiza, Alejandro (Alex) ; Jian, Jane
Cc: Zhang, Hawking
the psp access ih path is not needed in navi
Signed-off-by: Hawking Zhang
Change-Id: Ib68bfb1b13e1cec03ec27bc9a867e2b37fc2fc8a
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git
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