[PATCH 15/16] drm/amd/display: 3.2.131

From: Aric Cyr DC version 3.2.131 brings improvements in multiple areas. In summary, we highlight: -Enhancement for multiple eDP BL control. -Add debug flag to enable eDP ILR by default and debugfs to repress HPD/HPR_RX IRQ. -Fixes for DSC enable sequence,Force vsync flip,hang when psr is ena

[PATCH 16/16] drm/amd/display: [FW Promotion] Release 0.0.61

From: Anthony Koo Signed-off-by: Anthony Koo Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

[PATCH 12/16] drm/amd/display: [FW Promotion] Release 0.0.60

From: Anthony Koo Signed-off-by: Anthony Koo Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

[PATCH 14/16] drm/amd/display: Fix hangs with psr enabled on dcn3.xx

From: Roman Li [Why] SKIP_CRTC_DISABLE bit should be applicable to all dcn asics not only Raven. [How] Replace check for Raven only with check for all DCNs. Signed-off-by: Roman Li Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 + 1 file changed, 1 inser

[PATCH 13/16] drm/amd/display: Added support for multiple eDP BL control

From: Jake Wang [WHY & HOW] Driver currently assumes only 1 eDP is connected. Added support for multiple eDP BL control. Signed-off-by: Jake Wang Acked-by: Bindu Ramamurthy --- .../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 2 ++ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 27 ++

[PATCH 10/16] drm/amd/display: Add debugfs to repress HPD and HPR_RX IRQs

From: Harry Wentland [Why] For debugging reasons it can be beneficial to disable any hotplug and DP shortpulse interrupt handling. [How] Expose a debugfs to set a flag to bypass HPD IRQ handling and skip IRQ handling if flag is set. Signed-off-by: Harry Wentland Acked-by: Bindu Ramamurthy -

[PATCH 11/16] drm/amd/display: wait vblank when stream enabled and update dpp clock

From: Lewis Huang [Why] When boot into OS, seamless boot device won't blank stream. Driver update dpp clock when scanline position in vactive will show garbage on screen. [How] Wait for vblank for seamless boot edp display when driver update dpp clock. The apply seamless boot flag will be clear

[PATCH 09/16] drm/amd/display: Connect clock optimization function to dcn301

From: Mikita Lipski [why/how] Connecting clock optimization functions to dcn301 HWSS to enable power state enter/exit optimization Signed-off-by: Mikita Lipski Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --gi

[PATCH 08/16] drm/amd/display: Remove unused flag from stream state

From: Mikita Lipski [why & how] Removing unused DSC flag which is incorrect and is not used. We are only using stream->timing.flags.DSC for DSC's current state. Stream state as an input parameter and should not contain any past status flags. Signed-off-by: Mikita Lipski Acked-by: Bindu Ramamurt

[PATCH 05/16] drm/amd/display: Fix DML validation of simple vs native 422 modes

From: Nicholas Kazlauskas [Why] We're always validating DML with simple 422 DSC even if native 422 DSC is in use. [How] Use the mode configuration from the timing. Signed-off-by: Nicholas Kazlauskas Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7

[PATCH 07/16] drm/amd/display: Force vsync flip when reconfiguring MPCC

From: Anthony Wang [Why] Underflow observed when disabling PIP overlay in-game when vsync is disabled, due to OTC master lock not working with game pipe which is immediate flip. [How] When performing a full update, override flip_immediate value to false for all planes, so that flip occurs on vsy

[PATCH 03/16] drm/amd/display: Fix DSC enable sequence

From: Mike Hsieh [Why] DSC is enabled before reset link and potentially cause DSC enable fail problem. [How] Enable DSC after link is reseted Signed-off-by: Mike Hsieh Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +++--- drivers/gpu/drm/amd/displa

[PATCH 06/16] drm/amd/display: Set LTTPR mode to non-LTTPR if no repeaters found

From: Wesley Chalmers [WHY] If no repeaters are found, we do not need or want to attempt to link-train repeaters, as this could cause bugs. Signed-off-by: Wesley Chalmers Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++ 1 file changed, 2 insertions(+) d

[PATCH 04/16] drm/amd/display: Remove static property from decide_edp_link_settings

From: Michael Strauss [Why & How] Static cleanup for eDP ILR Support. Signed-off-by: Michael Strauss Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 2 files changed, 5 insertions(+), 1 deletion(

[PATCH 02/16] drm/amd/display: Disable boot optimizations if ILR optimzation is required

From: Michael Strauss [Why] VBIOS currently sets the max link rate found in eDP 1.4 SUPPORTED_LINK_RATES table If eDP fastboot optimizations are enabled, the link rate remains at max after init [How] Determine optimal link rate during boot, disable seamless boot and eDP fastboot optimizations

[PATCH 01/16] drm/amd/display: Add debug flag to enable eDP ILR by default

From: Michael Strauss [Why & How] Allow per-asic enablement of ILR feature with debug flag Signed-off-by: Michael Strauss Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 2 files changed, 2 inserti

[PATCH 00/16] DC Patches April 12, 2021

This DC patchset brings improvements in multiple areas. In summary, we highlight: * Enhancement for multiple eDP BL control. * Add debug flag to enable eDP ILR by default and debugfs to repress HPD/HPR_RX IRQ. * Connect clock optimization,Set LTTPR mode to non-LTTPR, Fix DML validation of simple

[PATCH 2/2] drm/amdkfd: change SVM MTYPEs for Aldebaran's HW requirement

From: Philip Yang Due to changes of HW memory model, we need to change Aldebaran MTYPEs to meet HW changes. Change-Id: I0b566ccd1d406abe93ee84da91216794fc650ed4 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 11 --- 1 file changed, 4

[PATCH 1/2] drm/amdkfd: change MTYPEs for Aldebaran's HW requirement

Due to changes of HW memory model, we need to change Aldebaran MTYPEs to meet HW changes. Signed-off-by: Eric Huang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/

Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13

On Fri, 9 Apr 2021 at 19:07, Christian König wrote: > > Am 08.04.21 um 15:03 schrieb Alex Deucher: > > On Thu, Apr 8, 2021 at 6:28 AM Christian König > > wrote: > >> Am 08.04.21 um 09:13 schrieb Christian König: > >>> Am 07.04.21 um 21:04 schrieb Alex Deucher: > On Wed, Apr 7, 2021 at 3:23 A

Re: [PATCH 0/4] Refine GPU recovery sequence to enhance its stability

On 2021-04-09 12:39 p.m., Christian König wrote: Am 09.04.21 um 17:42 schrieb Andrey Grodzovsky: On 2021-04-09 3:01 a.m., Christian König wrote: Am 09.04.21 um 08:53 schrieb Christian König: Am 08.04.21 um 22:39 schrieb Andrey Grodzovsky: [SNIP] But inserting dmr_dev_enter/exit on the highe

Re: [PATCH 0/4] Refine GPU recovery sequence to enhance its stability

Am 09.04.21 um 17:42 schrieb Andrey Grodzovsky: On 2021-04-09 3:01 a.m., Christian König wrote: Am 09.04.21 um 08:53 schrieb Christian König: Am 08.04.21 um 22:39 schrieb Andrey Grodzovsky: [SNIP] But inserting dmr_dev_enter/exit on the highest level in drm_ioctl is much less effort and less

Re: [PATCH 0/4] Refine GPU recovery sequence to enhance its stability

On 2021-04-09 3:01 a.m., Christian König wrote: Am 09.04.21 um 08:53 schrieb Christian König: Am 08.04.21 um 22:39 schrieb Andrey Grodzovsky: On 2021-04-08 2:58 p.m., Christian König wrote: Am 08.04.21 um 18:08 schrieb Andrey Grodzovsky: On 2021-04-08 4:32 a.m., Christian König wrote: Am 0

[PATCH] drm/amd/pm: Show updated clocks on aldebaran

[AMD Public Use] When GFXCLK range is updated in manual/determinism mode, show the updated min/max clock range. Signed-off-by: Lijo Lazar lijo.la...@amd.com --- .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 52 +++ 1 file changed, 41 insertions(+), 11 d

[PATCH 4/4] Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"

From: Oak Zeng This reverts commit 34a33d4683cba7ba63c894132efb1998c0217631. Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 9 - drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 -- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 21 ++--- drive

[PATCH 3/4] drm/amdgpu: Introduce new SETUP_TMR interface

From: Oak Zeng This new interface passes both virtual and physical address to PSP. It is backward compatible with old interface. v2: use a function to simplify tmr physical address calc (Lijo) Signed-off-by: Oak Zeng Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_p

[PATCH 2/4] drm/amdgpu: Calling address translation functions to simplify codes

From: Oak Zeng Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by: Oak Zeng Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 +-- drivers/gpu/drm/amd/amdgp

[PATCH 1/4] drm/amdgpu: Introduce functions for vram physical addr calculation

From: Oak Zeng Add one function to calculate BO's GPU physical address. And another function to calculate BO's CPU physical address. v2: Use functions vs macros (Christian) Use more proper function names (Christian) Signed-off-by: Oak Zeng Suggested-by: Lijo Lazar Reviewed-by: Christian K

RE: [PATCH 3/4] drm/amdgpu: Introduce new SETUP_TMR interface

[AMD Official Use Only - Internal Distribution Only] Minor typo. See below. With that fixed Reviewed-By: Harish Kasiviswanathan -Original Message- From: amd-gfx On Behalf Of Oak Zeng Sent: Thursday, April 1, 2021 3:37 PM To: amd-gfx@lists.freedesktop.org Cc: Kuehling, Felix ; Lazar, L

Re: amd/display: allow non-linear multi-planar formats

Hi, Can you have a look at this patch? Thanks, Simon On Friday, March 26th, 2021 at 5:59 PM, Simon Ser wrote: > Accept non-linear buffers which use a multi-planar format, as long > as they don't use DCC. > > Tested on GFX9 with NV12. > > Signed-off-by: Simon Ser > Cc: Alex Deucher > Cc: Har

Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13

Am 08.04.21 um 15:03 schrieb Alex Deucher: On Thu, Apr 8, 2021 at 6:28 AM Christian König wrote: Am 08.04.21 um 09:13 schrieb Christian König: Am 07.04.21 um 21:04 schrieb Alex Deucher: On Wed, Apr 7, 2021 at 3:23 AM Dave Airlie wrote: On Wed, 7 Apr 2021 at 06:54, Alex Deucher wrote: On F

RE: [PATCH] drm/amdgpu: page retire over sysfs mechanism

[AMD Public Use] It's ras debugfs change, so please fix all "sysfs" statement in commit message. In addition, please also print out message to inform user the retire_page is only for test/debugging purpose and is in risk to corrupt eeprom data. Other than that, the patch is Reviewed-by: Hawking

[PATCH] drm/amdgpu: page retire over sysfs mechanism

[AMD Official Use Only - Internal Distribution Only] Submitting patch to unit test page retirement feature via ras sysfs interface 0001-drm-amdgpu-page-retire-over-sysfs-mechanism.patch Description: 0001-drm-amdgpu-page-retire-over-sysfs-mechanism.patch __

Re: [PATCH 0/4] Refine GPU recovery sequence to enhance its stability

Am 09.04.21 um 08:53 schrieb Christian König: Am 08.04.21 um 22:39 schrieb Andrey Grodzovsky: On 2021-04-08 2:58 p.m., Christian König wrote: Am 08.04.21 um 18:08 schrieb Andrey Grodzovsky: On 2021-04-08 4:32 a.m., Christian König wrote: Am 08.04.21 um 10:22 schrieb Christian König: [SNIP]