Hi,
I thought it was this[1] the one causing problems[2].
--
Gustavo
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=434fb1e7444a2efc3a4ebd950c7f771ebfcffa31
[2]
https://lore.kernel.org/dri-devel/3eedbe78-1fbd-4763-a7f3-ac5665e76...@xenosoft.de/
On 5/4/21 13:
I had to rebase them and was on sick leave last week.
Changed a few things on patch #1 and pushed the result a minute ago.
Christian.
Am 04.05.21 um 22:23 schrieb Alex Deucher:
Did you push this yet? I don't see it in drm-misc.
Thanks,
Alex
On Wed, Apr 28, 2021 at 5:06 AM Christian König
Move ras_hw_supported into struct amdgpu_dev.
The dependency is:
struct amdgpu_ras <== struct amdgpu_dev <== ASIC,
read as "struct amdgpu_ras depends on struct
amdgpu_dev, which depends on the hardware."
This can be loosely understood as, "if RAS is
supported, which is property of the ASIC (struct
Export the runtime-set "ras_hw_enabled" and
"ras_enabled" to debugfs, for debugging.
Cc: Alexander Deucher
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 --
1 file changed, 4 insertions(+), 2 dele
Classic normalization of a redundant variable.
There is no need to have two variables representing
the same quantity. Move up to the structure which
represents the object which determines their values.
Rename to a consistent name, and export to debugfs
for debugging.
Luben Tuikov (4):
drm/amdgpu
Rename,
ras_hw_supported --> ras_hw_enabled, and
ras_features --> ras_enabled,
to show that ras_enabled is a subset of
ras_hw_enabled, which itself is a subset
of the ASIC capability.
Cc: Alexander Deucher
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
Acked-by: Christ
Remove redundant ras->supported, as this value
is also stored in adev->ras_features.
Use adev->ras_features, as that supercedes "ras",
since the latter is its member.
The dependency goes like this:
ras <== adev->ras_features <== hw_supported,
and is read as "ras depends on ras_features, which
dep
Since Chunming Zhou left AMD last year we are down to only
two maintainers once more. So add Xinhu Pan as another
contact as well.
Signed-off-by: Christian König
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 64ed8b77cfa9..e2cb5a8acdf1 100644
From: Sathishkumar S
enable vcn mgcg flag for picasso.
Signed-off-by: Sathishkumar S
Reviewed-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
[AMD Public Use]
> -Original Message-
> From: Gustavo A. R. Silva
> Sent: Tuesday, May 4, 2021 6:43 PM
> To: Deucher, Alexander ; amd-
> g...@lists.freedesktop.org
> Cc: Gustavo A . R . Silva
> Subject: Re: [PATCH] Revert "drm/radeon/si_dpm: Replace one-element
> array with flexible-arra
Hi,
On 5/5/21 12:33 AM, Limonciello, Mario wrote:
> [AMD Public Use]
>
>> Subject: [PATCH] platform/x86: Add missing LPS0 functions for AMD
>
> Rafael might be willing to fix it up on commit, but if you end up needing to
> re-spin
> I think technically this subsystem prefix to match other stuff
On Wed, May 5, 2021 at 9:10 AM Hans de Goede wrote:
>
> Hi,
>
> On 5/5/21 12:33 AM, Limonciello, Mario wrote:
> > [AMD Public Use]
> >
> >> Subject: [PATCH] platform/x86: Add missing LPS0 functions for AMD
> >
> > Rafael might be willing to fix it up on commit, but if you end up needing
> > to re
On Wed, May 5, 2021 at 7:01 AM Christian König
wrote:
>
> Since Chunming Zhou left AMD last year we are down to only
> two maintainers once more. So add Xinhu Pan as another
> contact as well.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> MAINTAINERS | 1 +
> 1 file cha
Hi,
On 5/5/21 3:11 PM, Alex Deucher wrote:
> On Wed, May 5, 2021 at 9:10 AM Hans de Goede wrote:
>>
>> Hi,
>>
>> On 5/5/21 12:33 AM, Limonciello, Mario wrote:
>>> [AMD Public Use]
>>>
Subject: [PATCH] platform/x86: Add missing LPS0 functions for AMD
>>>
>>> Rafael might be willing to fix it
These are supposedly not required for AMD platforms,
but at least some HP laptops seem to require it to
properly turn off the keyboard backlight.
Based on a patch from Marcin Bachry .
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1230
Reviewed-by: Hans de Goede
Signed-off-by: Alex Deucher
On 2021-05-03 3:34 p.m., Felix Kuehling wrote:
Am 2021-05-03 um 3:27 p.m. schrieb Eric Huang:
On 2021-05-03 3:13 p.m., Felix Kuehling wrote:
Am 2021-05-03 um 10:47 a.m. schrieb Eric Huang:
In NPS4 BIOS we need to find the closest numa node when creating
topology io link between cpu and gpu,
In NPS4 BIOS we need to find the closest numa node when creating
topology io link between cpu and gpu, if PCI driver doesn't set
it.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/drivers/gpu/dr
Ping
Andrey
On 2021-04-30 12:10 p.m., Andrey Grodzovsky wrote:
On 2021-04-30 2:47 a.m., Christian König wrote:
Am 29.04.21 um 19:06 schrieb Andrey Grodzovsky:
On 2021-04-29 3:18 a.m., Christian König wrote:
I need to take another look at this part when I don't have a massive
headache a
Ping
Andrey
On 2021-04-30 1:27 p.m., Andrey Grodzovsky wrote:
On 2021-04-30 6:25 a.m., Daniel Vetter wrote:
On Thu, Apr 29, 2021 at 04:34:55PM -0400, Andrey Grodzovsky wrote:
On 2021-04-29 3:05 p.m., Daniel Vetter wrote:
On Thu, Apr 29, 2021 at 12:04:33PM -0400, Andrey Grodzovsky wrote:
On Tue, May 4, 2021 at 9:22 PM Alex Deucher wrote:
>
> On Wed, Apr 28, 2021 at 5:21 PM Alex Deucher wrote:
> >
> > On Tue, Apr 20, 2021 at 5:25 PM Alex Deucher wrote:
> > >
> > > On Fri, Apr 16, 2021 at 12:29 PM Mario Kleiner
> > > wrote:
> > > >
> > > > Friendly ping to the AMD people. Nichola
On 2021-05-04 1:05 p.m., Felix Kuehling wrote:
Am 2021-04-28 um 11:11 a.m. schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related dependencies before the
group is removed.
v5: Drop IOMMU notifier and switch to lockless call to ttm_tt_unpopulate
Signed-off-by: Andrey Grodzovsky
---
On 5/5/21 08:06, Deucher, Alexander wrote:
> [AMD Public Use]
>
>> -Original Message-
>> From: Gustavo A. R. Silva
>> Sent: Tuesday, May 4, 2021 6:43 PM
>> To: Deucher, Alexander ; amd-
>> g...@lists.freedesktop.org
>> Cc: Gustavo A . R . Silva
>> Subject: Re: [PATCH] Revert "drm/rade
Ping
Andrey
On 2021-05-04 11:43 a.m., Andrey Grodzovsky wrote:
On 2021-05-04 3:03 a.m., Christian König wrote:
Am 03.05.21 um 22:43 schrieb Andrey Grodzovsky:
On 2021-04-29 3:08 a.m., Christian König wrote:
Am 28.04.21 um 17:11 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup rela
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Harish Kasiviswanathan
-Original Message-
From: Quan, Evan
Sent: Tuesday, April 27, 2021 9:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kasiviswanathan, Harish
; Quan, Evan
Subject: [PATCH 2/2] drm/
From: Anthony Wang
[ Upstream commit 56d63782af9bbd1271bff1422a6a013123eade4d ]
[Why]
Underflow observed when disabling PIP overlay in-game when
vsync is disabled, due to OTC master lock not working with
game pipe which is immediate flip.
[How]
When performing a full update, override flip_immed
From: Jinzhou Su
[ Upstream commit 5c88e3b86a88f14efa0a3ddd28641c6ff49fb9c4 ]
The buffer of SA bo will be used by many cases. So it's better
to invalidate the cache of indirect buffer allocated by SA before
commit the IB.
Signed-off-by: Jinzhou Su
Reviewed-by: Christian König
Signed-off-by: A
From: "Dingchen (David) Zhang"
[ Upstream commit 4ccf9446b2a3615615045346c97f8a1e2a16568a ]
[why]
the current implementation of hdcp2 rx id list validation does not
have handler/checker for invalid message status, e.g. HMAC, the V
parameter calculated from PSP not matching the V prime from Rx.
From: Robin Singh
[ Upstream commit 19cc1f3829567e7dca21c1389ea6407b8f5efab4 ]
[why]
During dsc enable, a divide by zero condition triggered the
kernel crash.
[how]
An IGT test, which enable the DSC, was crashing at the time of
restore the default dsc status, becaue of h_totals value
becoming 0
From: Anthony Wang
[ Upstream commit 56d63782af9bbd1271bff1422a6a013123eade4d ]
[Why]
Underflow observed when disabling PIP overlay in-game when
vsync is disabled, due to OTC master lock not working with
game pipe which is immediate flip.
[How]
When performing a full update, override flip_immed
From: Robin Singh
[ Upstream commit 19cc1f3829567e7dca21c1389ea6407b8f5efab4 ]
[why]
During dsc enable, a divide by zero condition triggered the
kernel crash.
[how]
An IGT test, which enable the DSC, was crashing at the time of
restore the default dsc status, becaue of h_totals value
becoming 0
From: "Dingchen (David) Zhang"
[ Upstream commit 4ccf9446b2a3615615045346c97f8a1e2a16568a ]
[why]
the current implementation of hdcp2 rx id list validation does not
have handler/checker for invalid message status, e.g. HMAC, the V
parameter calculated from PSP not matching the V prime from Rx.
From: Jinzhou Su
[ Upstream commit 5c88e3b86a88f14efa0a3ddd28641c6ff49fb9c4 ]
The buffer of SA bo will be used by many cases. So it's better
to invalidate the cache of indirect buffer allocated by SA before
commit the IB.
Signed-off-by: Jinzhou Su
Reviewed-by: Christian König
Signed-off-by: A
From: Anthony Wang
[ Upstream commit 56d63782af9bbd1271bff1422a6a013123eade4d ]
[Why]
Underflow observed when disabling PIP overlay in-game when
vsync is disabled, due to OTC master lock not working with
game pipe which is immediate flip.
[How]
When performing a full update, override flip_immed
From: Robin Singh
[ Upstream commit 19cc1f3829567e7dca21c1389ea6407b8f5efab4 ]
[why]
During dsc enable, a divide by zero condition triggered the
kernel crash.
[how]
An IGT test, which enable the DSC, was crashing at the time of
restore the default dsc status, becaue of h_totals value
becoming 0
From: "Dingchen (David) Zhang"
[ Upstream commit 4ccf9446b2a3615615045346c97f8a1e2a16568a ]
[why]
the current implementation of hdcp2 rx id list validation does not
have handler/checker for invalid message status, e.g. HMAC, the V
parameter calculated from PSP not matching the V prime from Rx.
From: Jinzhou Su
[ Upstream commit 5c88e3b86a88f14efa0a3ddd28641c6ff49fb9c4 ]
The buffer of SA bo will be used by many cases. So it's better
to invalidate the cache of indirect buffer allocated by SA before
commit the IB.
Signed-off-by: Jinzhou Su
Reviewed-by: Christian König
Signed-off-by: A
From: Anthony Wang
[ Upstream commit 56d63782af9bbd1271bff1422a6a013123eade4d ]
[Why]
Underflow observed when disabling PIP overlay in-game when
vsync is disabled, due to OTC master lock not working with
game pipe which is immediate flip.
[How]
When performing a full update, override flip_immed
From: Robin Singh
[ Upstream commit 19cc1f3829567e7dca21c1389ea6407b8f5efab4 ]
[why]
During dsc enable, a divide by zero condition triggered the
kernel crash.
[how]
An IGT test, which enable the DSC, was crashing at the time of
restore the default dsc status, becaue of h_totals value
becoming 0
[AMD Public Use]
Acked-by: Alex Deucher
From: Sundararaju, Sathishkumar
Sent: Tuesday, May 4, 2021 5:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liu, Leo ;
Sundararaju, Sathishkumar
Subject: [PATCH] drm/amdgpu: set vcn mgcg flag for picass
On 2021-04-29 2:10 a.m., Felix Kuehling
wrote:
Am 2021-04-28 um 9:53 p.m. schrieb Philip Yang:
If migration vma setup, but failed before start sdma memory copy, e.g.
process is killed, don't wait for sdma fence done.
I think yo
If migration copy failed because process is killed, or out of VRAM or
system memory, pass error code back to caller to handle error
gracefully.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/driv
After svm range prefetch and migrate to GPU, if GPU has no access or
access in place attribute, add GPU to range access_bitmap to be able to
update GPU page table.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a
GPU retry vm fault on unregistered address, new range is created to
recover the retry vm fault. Instead of setting new range perferred_loc
to GPU, add GPU to new range access_bitmap, to be able to update GPU
page table after new range migrate to VRAM. The new range preferred_loc
is default value KF
Applied. Thanks! Do we need a similar fix for other VCN variants?
Alex
On Tue, May 4, 2021 at 10:14 PM Leo Liu wrote:
>
> Reviewed-and-Tested by: Leo Liu
>
> On 2021-05-04 9:27 p.m., Bas Nieuwenhuizen wrote:
> > Otherwise tiling modes that require the values form this field
> > (In particular
Applied. Thanks!
Alex
On Tue, May 4, 2021 at 11:30 AM Simon Ser wrote:
>
> On Tuesday, May 4th, 2021 at 11:43 AM, Bas Nieuwenhuizen
> wrote:
>
> > The builtin size check isn't really the right thing for AMD
> > modifiers due to a couple of reasons:
> >
> > 1) In the format structs we don't do
On 2021-05-05 2:17 p.m., Alex Deucher wrote:
Applied. Thanks! Do we need a similar fix for other VCN variants?
VCN3 is the only one missing that.
Regards,
Leo
Alex
On Tue, May 4, 2021 at 10:14 PM Leo Liu wrote:
Reviewed-and-Tested by: Leo Liu
On 2021-05-04 9:27 p.m., Bas Nieuwenh
update suspend register settings in Non-DPG mode.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 51a773a
On Mon, 3 May 2021, Alex Deucher wrote:
> On Mon, May 3, 2021 at 11:40 AM Mikulas Patocka wrote:
> >
> > Hi
> >
> > There's a bug with monitor hotplug starting with the kernel 5.7.
> >
> > I have Radeon RX 570. If I boot the system with the monitor unplugged and
> > then plug the monitor via D
[AMD Official Use Only - Internal Distribution Only]
Thanks,
Do we know when those changes will make it back to amd-staging-drm-next ?
From: Christian König
Sent: Wednesday, May 5, 2021 12:27 AM
To: Alex Deucher
Cc: Deng, Emily ; Deucher, Alexander
; amd-gfx li
Reviewed-by: Leo Liu
On 2021-05-04 11:10 a.m., Sathishkumar S wrote:
update suspend register settings in Non-DPG mode.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/
Am 2021-05-05 um 1:56 p.m. schrieb Philip Yang:
> After svm range prefetch and migrate to GPU, if GPU has no access or
> access in place attribute, add GPU to range access_bitmap to be able to
> update GPU page table.
I don't think we should change the bitmap_access, because this is
persistent and
Am 2021-05-05 um 1:56 p.m. schrieb Philip Yang:
> GPU retry vm fault on unregistered address, new range is created to
> recover the retry vm fault. Instead of setting new range perferred_loc
> to GPU, add GPU to new range access_bitmap, to be able to update GPU
> page table after new range migrate
Am 2021-05-05 um 4:01 p.m. schrieb Felix Kuehling:
> Am 2021-05-05 um 1:56 p.m. schrieb Philip Yang:
>> After svm range prefetch and migrate to GPU, if GPU has no access or
>> access in place attribute, add GPU to range access_bitmap to be able to
>> update GPU page table.
> I don't think we shoul
Am 2021-05-05 um 1:55 p.m. schrieb Philip Yang:
> If migration copy failed because process is killed, or out of VRAM or
> system memory, pass error code back to caller to handle error
> gracefully.
>
> Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/k
Am 2021-05-05 um 9:51 a.m. schrieb Eric Huang:
> In NPS4 BIOS we need to find the closest numa node when creating
> topology io link between cpu and gpu, if PCI driver doesn't set
> it.
>
> Signed-off-by: Eric Huang
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 9
pgmap owner member at the svm migrate init could be referenced
to either adev or hive, depending on device topology.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mi
[Why]
svm ranges can have mixed pages from device or system memory.
A good example is, after a prange has been allocated in VRAM and a
copy-on-write is triggered by a fork. This invalidates some pages
inside the prange. Endding up in mixed pages.
[How]
By classifying each page inside a prange, bas
This reference helps hmm to decide if device pages in the range
require to be migrated back to system memory, based if they are or
not in the same memory domain.
In this case, this reference could come from the same memory domain
with devices connected to the same hive.
Signed-off-by: Alex Sierra
On 05/05, Alex Sierra wrote:
> pgmap owner member at the svm migrate init could be referenced
> to either adev or hive, depending on device topology.
>
> Signed-off-by: Alex Sierra
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>
pgmap owner member at the svm migrate init could be referenced
to either adev or hive, depending on device topology.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mi
[Why]
svm ranges can have mixed pages from device or system memory.
A good example is, after a prange has been allocated in VRAM and a
copy-on-write is triggered by a fork. This invalidates some pages
inside the prange. Endding up in mixed pages.
[How]
By classifying each page inside a prange, bas
This reference helps hmm to decide if device pages in the range
require to be migrated back to system memory, based if they are or
not in the same memory domain.
In this case, this reference could come from the same memory domain
with devices connected to the same hive.
Signed-off-by: Alex Sierra
Am 2021-05-05 um 6:59 p.m. schrieb Alex Sierra:
> pgmap owner member at the svm migrate init could be referenced
> to either adev or hive, depending on device topology.
>
> Signed-off-by: Alex Sierra
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 +++---
> 1 file changed, 3 insertions(+),
This patch fixes the interactive--to the point of
unusability--slowdown when RAS is enabled on Vega 20 server
boards--which support full RAS.
Luben Tuikov (1):
drm/amdgpu: Poll of RAS errors asynchronously
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
When using Vega 20 with RAS support and RAS is
enabled, the system interactivity is extremely
slow, to the point of being unusable. After
debugging, it was determined that this is due to
the polling loop performed for
AMDGPU_CTX_OP_QUERY_STATE2 under
amdgpu_ctx_ioctl(), which seems to be executed o
Am 2021-05-05 um 6:59 p.m. schrieb Alex Sierra:
> This reference helps hmm to decide if device pages in the range
> require to be migrated back to system memory, based if they are or
> not in the same memory domain.
> In this case, this reference could come from the same memory domain
> with device
On Wed, Apr 28, 2021 at 11:22 PM Alex Deucher wrote:
>
> On Tue, Apr 20, 2021 at 5:25 PM Alex Deucher wrote:
> >
> > On Fri, Apr 16, 2021 at 12:29 PM Mario Kleiner
> > wrote:
> > >
> > > Friendly ping to the AMD people. Nicholas, Harry, Alex, any feedback?
> > > Would be great to get this in soo
Am 2021-05-05 um 6:59 p.m. schrieb Alex Sierra:
> [Why]
> svm ranges can have mixed pages from device or system memory.
> A good example is, after a prange has been allocated in VRAM and a
> copy-on-write is triggered by a fork. This invalidates some pages
> inside the prange. Endding up in mixed
[AMD Public Use]
Series is reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Saturday, May 1, 2021 12:43 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 2/2] drm/amdgpu/pm: add documentation for
> pp_od_clo
Hi Dave, Daniel,
Fixes for 5.13.
The following changes since commit a1a1ca70deb3ec600eeabb21de7f3f48aaae5695:
Merge tag 'drm-misc-next-fixes-2021-04-22' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2021-04-23 13:53:07
+1000)
are available in the Git repository at:
https:/
On Sat, Mar 20, 2021 at 04:09:47AM +0200, Ville Syrjälä wrote:
> On Fri, Mar 19, 2021 at 10:45:10PM +0100, Mario Kleiner wrote:
> > On Fri, Mar 19, 2021 at 10:16 PM Ville Syrjälä
> > wrote:
> > >
> > > On Fri, Mar 19, 2021 at 10:03:13PM +0100, Mario Kleiner wrote:
> > > > These are 16 bits per col
71 matches
Mail list logo
