From: Victor Zhao
save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
MP0_SMN_C2PMSG_102 reg
Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
Signed-off-by: Victor Zhao
Signed-off-by: Jingwen Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amd
Signed-off-by: Shiwu Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 2d876e1eaa7c..e9f8701fd046 100644
--- a/drivers/gpu/drm/amd/
Fix function name in sdma_v5_2.c kernel-doc comment
to remove a warning found by clang_w1.
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:528: warning: expecting prototype
for sdma_v_0_ctx_switch_enable(). Prototype was for
sdma_v5_2_ctx_switch_enable() instead.
Reported-by: Abaci Robot
Signed-off-by: Y
On Tue, May 25, 2021 at 10:56 PM Yang Li wrote:
>
> Fix function name in sdma_v5_2.c kernel-doc comment
> to remove a warning found by clang_w1.
>
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:528: warning: expecting prototype
> for sdma_v_0_ctx_switch_enable(). Prototype was for
> sdma_v5_2_ctx_switch
They are global ACPI methods, so maybe the structures
global in the driver. This simplified a number of things
in the handling of these methods.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 285 ---
Path should be NULL when we already have the handle
to the object.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
ind
Although the kfd_ioctl_get_dmabuf_info() still fail it will indicate
the caller right metadat_size useful for the same kfd ioctl next time.
Signed-off-by: Shiwu Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/g
[AMD Official Use Only - Internal Distribution Only]
Thanks for the comments! I'll separate it into two patches.
--Brs,
Morris Zhang
MLSE Linux ML SRDC
Ext. 25147
-Original Message-
From: Das, Nirmoy
Sent: Tuesday, May 25, 2021 8:15 PM
To: Zhang, Morris ; amd-gfx@lists.freedesktop.org
Applied. Thanks!
Alex
On Tue, May 25, 2021 at 3:51 AM Shaokun Zhang
wrote:
>
> Function 'r300_mc_wait_for_idle' and 'r600_mc_wait_for_idle'
> are declared twice, remove the repeated declaration.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Signed-off-by: Shaokun Zhang
> ---
> drivers/gpu/
On Tue, May 25, 2021 at 8:33 AM Shaokun Zhang
wrote:
>
> Function 'evergreen_print_gpu_status_regs' is declared twice, remove
> the repeated declaration.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Signed-off-by: Shaokun Zhang
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/radeon/evergre
On Tue, May 25, 2021 at 6:51 AM Shaokun Zhang
wrote:
>
> Function 'dc_power_down_on_boot' is declared twice, remove the
> repeated declaration.
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Signed-off-by: Shaokun Zhang
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/d
On Context Query2 IOCTL return the correctable and
uncorrectable errors in O(1) fashion, from cached
values, and schedule a delayed work function to
calculate and cache them for the next such IOCTL.
v2: Cancel pending delayed work at ras_fini().
Cc: Alexander Deucher
Cc: Christian König
Cc: Joh
On QUERY2 IOCTL don't query counts of correctable
and uncorrectable errors, since when RAS is
enabled and supported on Vega20 server boards,
this takes insurmountably long time, in O(n^3),
which slows the system down to the point of it
being unusable when we have GUI up.
Fixes: ae363a212b14 ("drm/
The correctable and uncorrectable errors
are calculated at each invocation of this
function. Therefore, it is highly inefficient to
return just one of them based on a Boolean
input. If the caller wants both, twice the work
would be done. (And this work is O(n^3) on
Vega20.)
Fix this "interface" to
On 2021-05-25 6:03 p.m., Alex Deucher wrote:
> On Fri, May 21, 2021 at 5:19 PM Luben Tuikov wrote:
>> On Context Query2 IOCTL return the correctable and
>> uncorrectable errors in O(1) fashion, from cached
>> values, and schedule a delayed work function to
>> calculate and cache them for the next
On Fri, May 21, 2021 at 5:19 PM Luben Tuikov wrote:
>
> On Context Query2 IOCTL return the correctable and
> uncorrectable errors in O(1) fashion, from cached
> values, and schedule a delayed work function to
> calculate and cache them for the next such IOCTL.
Patches 1, 2, are:
Reviewed-by: Alex
While clearing GCEA error status, do not clear the bits
set by RAS TA.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v
On 2021-05-25 14:05, Alex Deucher wrote:
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
Good Evening,
I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
Th
Am 2021-05-25 um 8:47 a.m. schrieb Dan Carpenter:
> If amdgpu_gem_prime_export() fails, then this code accidentally
> returns zero/success instead of a negative error code.
>
> Fixes: 190f2d7696c8 ("drm/amdgpu: Add DMA mapping of GTT BOs")
> Signed-off-by: Dan Carpenter
Thank you for catching the
Thanks!
I've just created: https://gitlab.freedesktop.org/drm/amd/-/issues/1606
Regards,
Luis
On Tue, May 25, 2021 at 3:02 PM Christian König
wrote:
>
> Hi Luis,
>
> adding Daniel as well.
>
> first of all can you please create a bug report for this here:
> https://gitlab.freedesktop.org/drm/am
Similar to a recent fix by Philip Yang 76e08b37d0aa ("drm/amdgpu: flush
TLB if valid PDE turns into PTE"), there needs to be a conditional TLB
flush after map, if any PDEs were unmapped and turned into PTEs in the
process. This is currently returned by amdgpu_vm_bo_update_mapping in
the "table_free
Problem:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:332:1: warning: unused label 'exit'
[-Wunused-label]
exit:
^
Fix: Put #ifdef CONFIG_64BIT around exit
Reported-by: kernel test robot
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed,
With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Signed-off-by: Eric Huang
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index ac45d9c7a4e9..aefb3d2927d5 100644
--- a/drivers/gpu/
It it to optimize memory allocation latency.
Signed-off-by: Eric Huang
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 960913a35ee4..ab73741edb97 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_c
Most of these changes are due to Van Gogh having a different naming scheme than
the rest. Just to confirm, let me know if this translation is what you're
referring to with the below defines for Van Gogh:
THROTTLER_STATUS_BIT_SPL-> SMU_THROTTLER_SPL_BIT
THROTTLER_STATUS_BIT_F
On Tue, May 25, 2021 at 11:27 AM Christian König
wrote:
>
> Am 24.05.21 um 20:48 schrieb Alex Deucher:
> > Applied. Thanks!
>
> Ok, that's unfortunate.
>
> IIRC we added the code because of a different compiler warning.
>
I can revert it.
Alex
> Christian.
>
> >
> > Alex
> >
> > On Mon, May 24
Am 24.05.21 um 20:48 schrieb Alex Deucher:
Applied. Thanks!
Ok, that's unfortunate.
IIRC we added the code because of a different compiler warning.
Christian.
Alex
On Mon, May 24, 2021 at 6:47 AM Jiapeng Chong
wrote:
In the function amdgpu_uvd_cs_msg(), every branch in the switch
state
+Rohit
-Original Message-
From: Zhou, Peng Ju
Sent: Wednesday, May 19, 2021 10:34 AM
To: Zhou, Peng Ju ; Alex Deucher ;
amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Ming, Davis ; Chang,
HaiJun
Subject: RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12
sriov
[AM
Something I forgot to add is that patches 1 to 4 already have a
Reviewed-by: Christian König
Am 25.05.21 um 17:10 schrieb Thomas Zimmermann:
Implement mmap via struct drm_gem_object_functions.mmap in amdgpu,
radeon and nouveau. This allows for using common DRM helpers for
the mmap-related
The function ttm_bo_mmap is unused. Remove it and it's helpers; including
the verify_access callback in struct ttm_device_funcs.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo_vm.c | 53 -
include/drm/ttm/ttm_bo_api.h
Vmwgfx is the only user of the TTM's verify_access callback. Inline
the call and avoid the indirection through the function pointer.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Zack Rusin
---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 9 -
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
Moving the driver-specific mmap code into a GEM object function allows
for using DRM helpers for various mmap callbacks.
This change also allows to support prime-based mmap via DRM's helper
drm_gem_prime_mmap().
Permission checks are implemented by drm_gem_mmap(), with an additional
check for rad
Moving the driver-specific mmap code into a GEM object function allows
for using DRM helpers for various mmap callbacks.
This change resolves several inconsistencies between regular mmap and
prime-based mmap. The vm_ops field in vma is now set for all mmap'ed
areas. Previously it way only set for
Moving the driver-specific mmap code into a GEM object function allows
for using DRM helpers for various mmap callbacks.
The GEM object function is provided by GEM TTM helpers. Nouveau's
implementation of verify_access is unused and has been removed. Access
permissions are validated by the DRM hel
The vmwgfx driver is the only remaining user of ttm_bo_mmap(). Inline
the code. The internal helper ttm_bo_vm_lookup() is now also part of
vmwgfx as vmw_bo_vm_lookup().
v2:
* replace pr_err() with drm_err() (Zack)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Zack Rusin
---
drivers/gpu
Implement mmap via struct drm_gem_object_functions.mmap in amdgpu,
radeon and nouveau. This allows for using common DRM helpers for
the mmap-related callbacks in struct file_operations and struct
drm_driver. The drivers have their own vm_ops, which are now set
automatically by the DRM core function
Drivers may want to set their own callbacks for a VM area. Only set
TTM's callbacks if the vm_ops field is clear.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ttm/ttm_bo_vm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drive
Am 25.05.21 um 16:19 schrieb Peter Geis:
On Tue, May 25, 2021 at 10:08 AM Christian König
wrote:
Hi Peter,
some comment additionally what Alex said.
Am 25.05.21 um 04:34 schrieb Peter Geis:
[SNIP]
Memory at 30090 (64-bit, non-prefetchable) [size=128K]
This here...
[SNI
On Tue, May 25, 2021 at 10:08 AM Christian König
wrote:
>
> Hi Peter,
>
> some comment additionally what Alex said.
>
> Am 25.05.21 um 04:34 schrieb Peter Geis:
> > Good Evening,
> >
> > I am stress testing the pcie controller on the rk3566-quartz64 prototype
> > SBC.
> > This device has 1GB avai
Am 25.05.21 um 12:40 schrieb Jiapeng Chong:
In the function amdgpu_uvd_cs_msg(), every branch in the switch
statement will have a return, so the code below the switch statement
will not be executed.
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_c
Hi Peter,
some comment additionally what Alex said.
Am 25.05.21 um 04:34 schrieb Peter Geis:
Good Evening,
I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
This device has 1GB available at <0x3 0x> for the PCIe
controller, which makes a dGPU theoretically p
Hi Luis,
adding Daniel as well.
first of all can you please create a bug report for this here:
https://gitlab.freedesktop.org/drm/amd/-/issues This way we can better
track issues.
Then what seems to happen is that somebody is using the TTM pages in a
way they are not supposed to be used.
On 2021-05-23 1:10 p.m., Christian
König wrote:
Am
21.05.21 um 21:28 schrieb philip yang:
This simply the logic, several comments inline.
Thanks,
Philip
On Tue, May 25, 2021 at 6:30 AM Peng Ju Zhou wrote:
>
> To enable PSP program IH_RB_CNTL,
> the PSP IP should be initialized before IH IP, otherwise,
> it will hit psp NULL pointer.
>
> Signed-off-by: Peng Ju Zhou
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++--
On Tue, May 25, 2021 at 9:05 AM Alex Deucher wrote:
>
> On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
> >
> > On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
> > >
> > > On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
> > > >
> > > > Good Evening,
> > > >
> > > > I am stress testing t
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
>
> On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
> >
> > On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
> > >
> > > Good Evening,
> > >
> > > I am stress testing the pcie controller on the rk3566-quartz64 prototype
> > > SBC.
> > > Thi
On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
>
> On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
> >
> > Good Evening,
> >
> > I am stress testing the pcie controller on the rk3566-quartz64 prototype
> > SBC.
> > This device has 1GB available at <0x3 0x> for the PCIe
> > control
If amdgpu_gem_prime_export() fails, then this code accidentally
returns zero/success instead of a negative error code.
Fixes: 190f2d7696c8 ("drm/amdgpu: Add DMA mapping of GTT BOs")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +++-
1 file changed, 3 inse
On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
>
> Good Evening,
>
> I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
> This device has 1GB available at <0x3 0x> for the PCIe
> controller, which makes a dGPU theoretically possible.
> While attempting to ligh
The amdgpu_bo_unreserve() has to be done on the error path as well.
Fixes: b4f0f97b8f5f ("drm/amdgpu: Move kfd_mem_attach outside reservation")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/
Function 'dc_power_down_on_boot' is declared twice, remove the
repeated declaration.
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Signed-off-by: Shaokun Zhang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/
Function 'r300_mc_wait_for_idle' and 'r600_mc_wait_for_idle'
are declared twice, remove the repeated declaration.
Cc: Alex Deucher
Cc: "Christian König"
Signed-off-by: Shaokun Zhang
---
drivers/gpu/drm/radeon/radeon_asic.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/ra
In the function amdgpu_uvd_cs_msg(), every branch in the switch
statement will have a return, so the code below the switch statement
will not be executed.
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_cs_msg() warn:
ignoring unreachable code.
Reporte
Good Evening,
I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
This device has 1GB available at <0x3 0x> for the PCIe
controller, which makes a dGPU theoretically possible.
While attempting to light off a HD7570 card I manage to get a modeset
console, but ring0
Function 'evergreen_print_gpu_status_regs' is declared twice, remove
the repeated declaration.
Cc: Alex Deucher
Cc: "Christian König"
Signed-off-by: Shaokun Zhang
---
drivers/gpu/drm/radeon/evergreen.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.h
b/dri
On 5/24/21 1:52 PM, Shiwu Zhang wrote:
Although the kfd_ioctl_get_dmabuf_info() still fail it will indicate
the caller right metadat_size useful for the same kfd ioctl next time.
v2: free the metadata buffer for sg type when to destroy BOs.
Signed-off-by: Shiwu Zhang
---
drivers/gpu/drm/am
To enable PSP program IH_RB_CNTL,
the PSP IP should be initialized before IH IP, otherwise,
it will hit psp NULL pointer.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b
Reviewed-by: Jack Gui
-Original Message-
From: amd-gfx On Behalf Of Chen,
Jiansong (Simon)
Sent: Tuesday, May 25, 2021 4:07 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info
I think we still could keep them to be mor
I think we still could keep them to be more informative for the moment.
Regards,
Jiansong
-Original Message-
From: Chen, Guchun
Sent: Tuesday, May 25, 2021 3:47 PM
To: Chen, Jiansong (Simon) ;
amd-gfx@lists.freedesktop.org
Cc: Chen, Jiansong (Simon)
Subject: RE: [PATCH] drm/amdgpu: ref
[AMD Public Use]
+ len = size;
/* Serial number should only be 16 characters. Any more,
* and something could be wrong. Cap it at 16 to be safe
*/
- if (size > 16) {
+ if (len >= sizeof(adev->serial)) {
DRM_WARN("FRU Serial Number is larg
[AMD Public Use]
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Asher Song
Sent: Tuesday, May 25, 2021 12:03 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Song, Asher
Subject: [PATCH] drm/amdgpu: add judgement for dc support
Drop DC ini
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