With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
table_freed will be always true when mapping a memory with size
bigger than 2MB. The problem is page table's entries are always
existed, but existing mapping depends on page talbe's bo, so
using a check of page table's bo existed will resolve the issue.
Signed-off-by: Eric Huang
---
[Public]
>< > The limits are not limited to sample window. There are limits like APU
>only limit, platform limit and totally obscure ones like PPT0/PPT1 etc.
>It's better that the new enum takes care of those as well in case there is a
>need to make them available through sysfs.
I think you
Am 31.05.21 um 17:51 schrieb Eric Huang:
With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Well that's closer to what I had in mind, but not 100% correct.
See the code in amdgpu_ib_schedule() as well:
#ifdef CONFIG_X86_64
if
Am 31.05.21 um 16:30 schrieb Eric Huang:
On 2021-05-31 10:08 a.m., Christian König wrote:
Am 30.05.21 um 20:29 schrieb Eric Huang:
On 2021-05-30 12:54 p.m., Christian König wrote:
Am 30.05.21 um 00:51 schrieb Eric Huang:
table_freed will be always true when mapping a memory with size
Am 19.05.21 um 15:49 schrieb Ville Syrjälä:
> On Wed, May 19, 2021 at 12:34:05PM +0300, Pekka Paalanen wrote:
>> On Wed, 12 May 2021 16:04:16 +0300
>> Ville Syrjälä wrote:
>>
>>> On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
Hello,
In addition to the existing "max
Am 12.05.21 um 19:59 schrieb Alex Deucher:
> On Wed, May 12, 2021 at 9:04 AM Ville Syrjälä
> wrote:
>> On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
>>> Hello,
>>>
>>> In addition to the existing "max bpc", and "Broadcast RGB/output_csc" drm
>>> properties I propose 4 new
With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 3 +++
3 files
On 2021-05-31 10:08 a.m., Christian König wrote:
Am 30.05.21 um 20:29 schrieb Eric Huang:
On 2021-05-30 12:54 p.m., Christian König wrote:
Am 30.05.21 um 00:51 schrieb Eric Huang:
table_freed will be always true when mapping a memory with size
bigger than 2MB. The problem is page table's
[AMD Official Use Only]
Hi Mario,
The following commit causes a display regression on my Carrizo when booting
linux into a console (e.g. no WM). When the driver inits the display goes
green and is unusable. The commit prior to this one on amd-staging-drm-next
results in a clean init.
Am 30.05.21 um 20:29 schrieb Eric Huang:
On 2021-05-30 12:54 p.m., Christian König wrote:
Am 30.05.21 um 00:51 schrieb Eric Huang:
table_freed will be always true when mapping a memory with size
bigger than 2MB. The problem is page table's entries are always
existed, but existing mapping
That's fair, I wasn't sure if adding a lookup table for the bitmapping of each
ASIC was necessarily wanted, but it would definitely result in less runtime
overhead.
This way we can also make use of the for_each_set_bit() macro in bitops.h. I'll
make the change and fix the padding and resubmit.
On 2021-05-28 12:39 p.m., Eric Huang
wrote:
On 2021-05-28 11:23 a.m., Christian
König wrote:
Am 27.05.21 um 16:05 schrieb philip
yang:
On
[AMD Official Use Only]
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, May 31, 2021 7:55 PM
>To: Yu, Lang ; amd-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Thomas Hellströ ; Olsak, Marek
>; Huang, Ray ; Deucher,
>Alexander
>Subject: Re: [PATCH v2
[AMD Official Use Only]
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, May 31, 2021 8:49 PM
>To: Yu, Lang ; amd-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Thomas Hellströ ; Olsak, Marek
>; Huang, Ray ; Deucher,
>Alexander
>Subject: Re: [PATCH v2
enable smart shift on dGPU if it is part of HG system and
the platform supports ATCS method to handle power shift.
V2: avoid psc updates in baco enter and exit (Lijo)
fix alignment (Shashank)
V3: rebased on unified ATCS handling. (Alex)
V4: check for return value and warn on failed update
On which branch are you working? I have problems applying that one to
amd-staging-drm-next.
Christian.
Am 31.05.21 um 10:22 schrieb Lang Yu:
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under
On 5/31/21 2:02 PM, Christian König wrote:
Am 31.05.21 um 13:19 schrieb Thomas Hellström (Intel):
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström
Am 31.05.21 um 13:19 schrieb Thomas Hellström (Intel):
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu,
Am 31.05.21 um 13:30 schrieb Lang Yu:
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
v2: move the check outside of for loop
Signed-off-by: Lang Yu
In general those patches now have my rb, but let me add some more
documentation to them to better explain
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
v2: move the check outside of for loop
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and add
TTM_PL_FLAG_TEMPORARY flag for temporary
GTT
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and add
TTM_PL_FLAG_TEMPORARY flag for temporary
GTT allocation use.
GTT is a driver private acronym,
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and add
TTM_PL_FLAG_TEMPORARY flag for temporary
GTT allocation use.
GTT is a driver private acronym, right? And it doesn't look like
TTM_PL_FLAG_TEMPORARY will
Re-adjust the function return order to avoid empty sdma version in the
sriov environment. (read amdgpu_firmware_info)
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Am 31.05.21 um 10:22 schrieb Lang Yu:
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c
the memset() and snprintf() is not necessary.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under GTT memory pressure we can't do buffer migration
between VRAM and SYSTEM domain. But in some cases we really need that.
Eespecially when
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c32a37d0a460..80c8cb2c3f31 100644
Cleanup and just make TTM_PL_FLAG_* start from zero.
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under GTT memory pressure we can't do buffer migration
between VRAM and SYSTEM domain. But in
[Public]
>Hi,
>On 5/27/21 3:30 AM, Lang Yu wrote:
>> Make TTM_PL_FLAG_* start from zero and add
>> TTM_PL_FLAG_TEMPORARY flag for temporary
>> GTT allocation use.
>GTT is a driver private acronym, right? And it doesn't look like
>TTM_PL_FLAG_TEMPORARY will be used in core TTM, so should we
Hello,
on 5.13-rc3 with a 4650U (Renoir, ChipID = 0x1636) I am able to
reliably get the GPU to reset under X11/Xorg with the amdgpu driver
(current from git) and having persistent problems afterwards. I
achieve this in the following way (using ROOT (root.cern.ch) to draw a
histogram):
$ root
#
Hello,
> on 5.13-rc3 with a 4650U (Renoir, ChipID = 0x1636) I am able to
> reliably get the GPU to reset under X11/Xorg with the amdgpu driver
> (current from git) and having persistent problems afterwards. I
> achieve this in the following way (using ROOT (root.cern.ch) to draw a
> histogram):
apply_dsc_policy_for_stream() will only be used if
'CONFIG_DRM_AMD_DC_DCN' is enabled, thus the function can be
declared inside the ifdefine marco.
Fix gcc warning:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5577:11: warning:
variable ‘link_bandwidth_kbps’ set but not used
[AMD Official Use Only]
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: amd-gfx on behalf of Sathishkumar
S
Sent: Thursday, May 27, 2021 12:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Sundararaju, Sathishkumar
; Sharma, Shashank
[Public]
Reviewed-by: Lijo Lazar
-Original Message-
From: amd-gfx On Behalf Of Sathishkumar
S
Sent: Thursday, May 27, 2021 9:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Sundararaju, Sathishkumar
; Sharma, Shashank
Subject: [PATCH] drm/amd/pm: use attr_update if
[Public]
-Original Message-
From: Powell, Darren
Sent: Saturday, May 29, 2021 4:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren
Subject: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature
add two new powerplay enums (limit_level, sample_window) add
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