Am 15.06.21 um 00:07 schrieb Felix Kuehling:
This should fix a kernel LOCKDEP warning on Vega10:
[ 149.416604]
[ 149.420877] WARNING: inconsistent lock state
[ 149.425152] 5.11.0-kfd-fkuehlin #517 Not tainted
[ 149.429770]
[ 1
Rename update_table_header() to
write_table_header() as this function is actually
writing it to EEPROM.
Use kernel types; use u8 to carry around the
checksum, in order to take advantage of arithmetic
modulo 8-bits (256).
Tidy up to 80 columns.
When updating the checksum, just recalculate the
who
Add "ras_eeprom_size" file in debugfs, which
reports the maximum size allocated to the RAS
table in EEROM, as the number of bytes and the
number of records it could store. For instance,
$cat /sys/kernel/debug/dri/0/ras/ras_eeprom_size
262144 bytes or 10921 records
$_
Add "ras_eeprom_table" file i
The I2C address is kept as a 16-bit quantity in
the kernel. The I2C_TAR::I2C_TAR field is 10-bit
wide.
Fix the width of the I2C address for Vega20 from 8
bits to 16 bits to accommodate the full spectrum
of I2C address space.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo
Debugfs RAS EEPROM files are available when
the ASIC supports RAS, and when the debugfs is
enabled, an also when "ras_enable" module
parameter is set to 0. However in this case,
we get a kernel oops when accessing some of
the "ras_..." controls in debugfs. The reason
for this is that struct amdgpu_
On long transfers to the EEPROM device,
i.e. write, it is observed that the driver aborts
the transfer.
The reason for this is that the driver isn't
patient enough--the IC_STATUS register's contents
is 0x27, which is MST_ACTIVITY | TFE | TFNF |
ACTIVITY. That is, while the transmission FIFO is
emp
In smu_v11_0_i2c_transmit() use a single loop to
transmit bytes, instead of two nested loops.
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Signed-off-by: Luben Tuikov
Reviewed-by: Alexander Deucher
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 72 ++
1 file changed, 34 i
No need to account for the 2 bytes of EEPROM
address--this is now well abstracted away by
the fixes the the lower layers.
Cc: Andrey Grodzovsky
Cc: Alexander Deucher
Signed-off-by: Luben Tuikov
Acked-by: Alexander Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +-
1 file chang
Convert RAS and FRU code to use the 19-bit I2C
memory address and remove all "slave_addr", as
this is now absolved into the 19-bit address.
Cc: Jean Delvare
Cc: John Clements
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Luben T
Read and write the table in one go, then using a
separate stage to decode or encode the data and
reading/writing the table, as opposed to on the
fly, which keeps the I2C bus busy. Use a single
read/write to read/write the table or at most two
if the number of records we're reading/writing
wraps aro
Wrap amdgpu_ras_eeprom_xfer(..., bool write),
into amdgpu_ras_eeprom_read() and
amdgpu_ras_eeprom_write(), as that makes reading
and understanding the code clearer.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: L
In amdgpu_ras_eeprom.c--the interface from RAS to
EEPROM, rename macros from EEPROM to RAS, to
indicate that the quantities and objects are RAS
specific, not EEPROM. We can decrease the RAS
table, or put it in different offset of EEPROM as
needed in the future.
Remove EEPROM_ADDRESS_SIZE macro def
* When reading from the EEPROM device, there is no
device limitation on the number of bytes
read--they're simply sequenced out. Thus, read
the whole data requested in one go.
* When writing to the EEPROM device, there is a
256-byte page limit to write to before having to
generate a STOP
The low level EEPROM write method, doesn't return
1, but the number of bytes written. Thus do not
compare to 1, instead, compare to greater than 0
for success.
Other cleanup: if the lower layers returned
-errno, then return that, as opposed to
overwriting the error code with one-fits-all
-EINVAL.
Instead of fixing the spelling in
amdgpu_ras_eeprom_process_recods(),
rename it to,
amdgpu_ras_eeprom_xfer(),
to look similar to other I2C and protocol
transfer (read/write) functions.
Also to keep the column span to within reason by
using a shorter name.
Change the "num" function parameter f
From: Andrey Grodzovsky
Drop i > 0 restriction for issuing RESTART.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Luben Tuikov
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/
From: Andrey Grodzovsky
Fix from number of processed bytes to number of
processed I2C messages.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Luben Tuikov
Reviewed-by: Luben T
RAS_MAX_RECORD_NUM may mean the maximum record
number, as in the maximum house number on your
street, or it may mean the maximum number of
records, as in the count of records, which is also
a number. To make this distinction whether the
number is ordinal (index) or cardinal (count),
rename this mac
From: Andrey Grodzovsky
EEPROM spec requests this.
v2: Only to be done for write data transactions.
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 15 +++
1 file changed, 15 insertions(+)
d
* "eeprom_addr" is now 32-bit wide.
* Remove "slave_addr" from the I2C EEPROM driver
interface. The I2C EEPROM Device Type Identifier
is fixed at 1010b, and the rest of the bits
of the Device Address Byte/Device Select Code,
are memory address bits, where the first three
of those bits are
Set the auto-discoverable class of I2C bus to
HWMON. Remove SPD.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
Reviewed-by: Alexander Deucher
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
From: Andrey Grodzovsky
Let's just ignore the I2C_M_STOP hint from upper
layer for SMU I2C code as there is no clean
mapping between single per I2C message STOP flag
at the kernel I2C layer and the SMU, per each byte
STOP flag. We will just by default set it at the
end of the SMU I2C message.
Cc
Add explicit amdgpu_eeprom_read() and
amdgpu_eeprom_write() for clarity.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
Acked-by: Alexander Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
From: Andrey Grodzovsky
To be used by kernel clients of the adapter.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Andrey Grodzovsky
Suggested-by: Lazar Lijo
Signed-off-by: Luben Tuikov
Reviewed-by: Luben Tu
Now that we have an I2C quirk table for
SMU-managed I2C controllers, the I2C core does the
checks for us, so we don't need to do them, and so
simplify the managed I2C transfer functions.
Also, for Arcturus and Navi10, fix setting the
command type from "cmd->CmdConfig" to "cmd->Cmd".
The latter is
From: Andrey Grodzovsky
Also generilize the code to accept and translate to
HW bits any I2C relvent flags both for read and write.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Andrey Grodzovsky
Signed-off-by:
From: Alex Deucher
Make it generic so we can support more than just EEPROMs.
v2: fix restart handling between transactions.
v3: handle 7 to 8 bit addr conversion
v4: Fix &req --> req. (Luben T)
Signed-off-by: Alex Deucher
Signed-off-by: Luben Tuikov
Reviewed-by: Luben Tuikov
---
.../gpu/drm
Consult the i2c_adapter.quirks table for
the maximum read/write data length per bus
transaction. Do not exceed this transaction
limit.
Cc: Jean Delvare
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Lijo Lazar
Cc: Stanley Yang
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
---
drivers/gpu/
Teach Vega20 I2C to be agnostic. Allow addressing
different devices while the master holds the bus.
Set STOP as per the controller's specification.
v2: Qualify generating ReSTART before the 1st byte
of the message, when set by the caller, as
those functions are separated, as caught by
From: Alex Deucher
Convert from 8 bit to 7 bit.
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/driv
Extend the I2C quirk table for SMU access
controlled I2C adapters. Let the kernel I2C layer
check that the messages all have the same address,
and that their combined size doesn't exceed the
maximum size of a SMU software I2C request.
Suggested-by: Jean Delvare
Cc: Jean Delvare
Cc: Alexander Deu
Fix the size of the EEPROM from 256000 bytes
to 262144 bytes (256 KiB).
Fix a couple or wrap around bugs. If a valid
value/address is 0 <= addr < size, the inverse of
this inequality (barring negative values which
make no sense here) is addr >= size. Fix this in
the RAS code.
Cc: Jean Delvare
Cc
From: Alex Deucher
So we lock software as well as hardware access to the bus.
v2: fix mutex handling.
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 19 +--
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h| 1 +
2 files chan
From: Alex Deucher
Not sure how the firmware interprets these.
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_ci
I2C fixes from various people. Some RAS touch-ups too.
A rebased tree can also be found here:
https://gitlab.freedesktop.org/ltuikov/linux/-/commits/i2c-rework-luben
Tested on Vega20 and Sienna Cichlid.
This first revision includes acks, squashes rev 1 patch 33 by
absolving it into earlier comm
From: Alex Deucher
Encapsulates the i2c protocol handling so other parts of the
driver can just tell it the offset and size of data to write.
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.
From: Alex Deucher
And handle more than just EEPROMs.
v2: fix restart handling between transactions.
v3: handle 7 to 8 bit addr conversion
v4: Fix &req --> req. (Luben T)
Signed-off-by: Alex Deucher
Signed-off-by: Luben Tuikov
Reviewed-by: Luben Tuikov
---
.../gpu/drm/amd/pm/swsmu/smu11/nav
From: Aaron Rice
Handle things besides EEPROMS.
Signed-off-by: Aaron Rice
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 47 +-
1 file changed, 9 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
From: Alex Deucher
Use the new helper rather than doing i2c transfers directly.
v2: fix typo
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 22 +--
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/driver
From: Alex Deucher
Use the new helper rather than doing i2c transfers directly.
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 86 ++-
1 file changed, 28 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Alex Deucher
Make it generic so we can support more than just EEPROMs.
v2: fix restart handling between transactions.
v3: handle 7 to 8 bit addr conversion
v4: Fix &req --> req. (Luben T)
Signed-off-by: Alex Deucher
Signed-off-by: Luben Tuikov
Reviewed-by: Luben Tuikov
---
.../amd/pm/
From: Alex Deucher
Not sure that this really matters that much, but these could
have various other hwmon chips on them.
Signed-off-by: Alex Deucher
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
On 6/14/2021 7:10 PM, Christian König wrote:
Am 14.06.21 um 16:32 schrieb Nirmoy Das:
Make provision to pass different ttm BO destroy callback
while creating a amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
1 file changed,
Am 14.06.21 um 16:32 schrieb Nirmoy Das:
Make provision to pass different ttm BO destroy callback
while creating a amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git
On Mon, Jun 14, 2021 at 3:27 PM Nirmoy Das wrote:
>
> Make provision to pass different ttm BO destroy callback
> while creating a amdgpu_bo.
>
> v2: pass destroy callback using amdgpu_bo_param.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 52
Am 2021-06-09 um 3:23 p.m. schrieb Matthew Wilcox:
> On Mon, Jun 07, 2021 at 03:42:19PM -0500, Alex Sierra wrote:
>> +++ b/include/linux/dax.h
>> @@ -243,6 +243,16 @@ static inline bool dax_mapping(struct address_space
>> *mapping)
>> return mapping->host && IS_DAX(mapping->host);
>> }
>>
On 6/14/2021 4:32 PM, Nirmoy Das wrote:
Make provision to pass different ttm BO destroy callback
while creating a amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/d
Use different ttm destroy callback for different type of amdgpu BO.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 47 --
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/
Move shadow_list to struct amdgpu_bo_vm as shadow BOs
are part of PT/PD BOs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 13 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 6 ++
drivers/gpu/drm
Make provision to pass different ttm BO destroy callback
while creating a amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/
On 2021-06-11 12:51 a.m., Alex Sierra
wrote:
[Why]
Avoid duplicated memory allocation for address ranges
that have been already allocated by either
ioctl_alloc_memory_of_gpu or SVM mechanisms first.
[How]
For SVM first allocations
Check if the address range
Drop the workaround and instead implement a better solution.
Basically we are now chaining all submissions using a dma_fence_chain
container and adding them as exclusive fence to the dma_resv object.
This way other drivers can still sync to the single exclusive fence
while amdgpu only sync to fen
Unwrap the explicit fence if it is a dma_fence_chain and
sync to the first fence not matching the owner rules.
Signed-off-by: Christian König
Acked-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 118 +--
1 file changed, 68 insertions(+), 50 deletions(-)
di
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p
60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI),
1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD
Am 11.06.21 um 16:55 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 04:53:11PM +0200, Christian König wrote:
Am 11.06.21 um 16:47 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 02:02:57PM +0200, Christian König wrote:
As the name implies if testing all fences is requested we
should indeed tes
Page table entries are now in embedded in VM BO, so
we do not need struct amdgpu_vm_pt. This patch replaces
struct amdgpu_vm_pt with struct amdgpu_vm_bo_base.
v2: change "!(cursor->level < AMDGPU_VM_PTB)" --> "(cursor->level ==
AMDGPU_VM_PTB)"
Signed-off-by: Nirmoy Das
---
.../gpu/drm/amd/amdg
Am 10.06.21 um 19:24 schrieb Nirmoy Das:
Page table entries are now in embedded in VM BO, so
we do not need struct amdgpu_vm_pt. This patch replaces
struct amdgpu_vm_pt with struct amdgpu_vm_bo_base.
Even struct amdgpu_vm_bo_base should be removed at some point, but for
now that's ok.
Sign
On Thu, Jun 10, 2021 at 9:55 AM Pekka Paalanen wrote:
>
> On Tue, 8 Jun 2021 19:43:15 +0200
> Werner Sembach wrote:
>
> > Add a new general drm property "active bpc" which can be used by graphic
> > drivers
> > to report the applied bit depth per pixel back to userspace.
> >
Maybe "bit depth p
ping.
On 6/10/2021 7:24 PM, Nirmoy Das wrote:
Page table entries are now in embedded in VM BO, so
we do not need struct amdgpu_vm_pt. This patch replaces
struct amdgpu_vm_pt with struct amdgpu_vm_bo_base.
Signed-off-by: Nirmoy Das
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 26 +--
hmm I see, thanks for the heads up, I'll double check why it uses
google email for sending.
wrt the assignment in the if clauses, are those typically frowned upon?
Thanks!
On Fri, Jun 11, 2021 at 4:17 PM Alex Deucher wrote:
>
> Just a heads up, your sender email and your signed-off-by don't match
On Mon, Jun 14, 2021 at 10:49 AM Mark Yacoub wrote:
>
> hmm I see, thanks for the heads up, I'll double check why it uses
> google email for sending.
> wrt the assignment in the if clauses, are those typically frowned upon?
Yes, checkpatch complains about them.
Alex
> Thanks!
>
> On Fri, Jun 1
On Sat, 12 Jun 2021 08:42:27 -0700
Joe Perches wrote:
> The __assign_str macro has an unusual ending semicolon but the vast
> majority of uses of the macro already have semicolon termination.
>
> $ git grep -P '\b__assign_str\b' | wc -l
> 551
> $ git grep -P '\b__assign_str\b.*;' | wc -l
> 480
>
The __assign_str macro has an unusual ending semicolon but the vast
majority of uses of the macro already have semicolon termination.
$ git grep -P '\b__assign_str\b' | wc -l
551
$ git grep -P '\b__assign_str\b.*;' | wc -l
480
Add semicolons to the __assign_str() uses without semicolon terminatio
Commit cb1c81467af3 ("drm/ttm: flip the switch for driver
allocated resources v2") changed few ttm_resource pointer names.
The corresponding kernel doc comments were not updated, which
produces few kernel doc build warnings of the type:
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:193: warning: E
Am 11.06.21 um 17:18 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 12:09:19PM +0200, Christian König wrote:
Am 11.06.21 um 11:07 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:17:59AM +0200, Christian König wrote:
Unwrap a the explicit fence if it is a dma_fence_chain and
sync to the first
65 matches
Mail list logo
