Direct IB submission should be exclusive. So use write lock.
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_deb
alloc extra msg from direct IB pool.
Signed-off-by: xinhui pan
---
change from v1:
let addr align up to gpu page boundary.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27 -
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu
alloc extra msg from direct IB pool.
Reviewed-by: Christian König
Signed-off-by: xinhui pan
---
change from v1:
let addr align up to gpu page boundary.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 97 +++--
1 file changed, 44 insertions(+), 53 deletions(-)
diff --git a/dri
move BO allocation in sw_init.
Signed-off-by: xinhui pan
---
change from v2:
use reservation trylock for direct IB test.
change from v1:
only use pre-allocated BO for direct IB submission.
and take its reservation lock to avoid any potential race.
better safe than sorry.
---
drivers/gpu/drm/amd/
These bits are de-facto part of the uAPI, so declare them in a uAPI header.
Signed-off-by: Felix Kuehling
---
MAINTAINERS | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 46 +
include/uapi/linux/kfd_sysfs.h| 108 ++
3 fi
On 2021-09-10 11:15 a.m., shaoyunl wrote:
The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies
to all
associated VFs. so guest driver can not directly enable the atomicOps for VF, it
depends on PF to enable it. In current design, amdgpu driver will get the
enabled
atom
Yeah, that indeed sounds buggy. Probably easiest to just down write the
reset sem.
Christian.
Am 10.09.21 um 13:48 schrieb Pan, Xinhui:
[AMD Official Use Only]
looks like amdgpu_debugfs_test_ib_show use direct IB submission too.
It parks the ring scheduler thread, and down read the reset_sem
This patch allows panel orientation quirks from DRM core to be
used. They attach a DRM connector property "panel orientation"
which indicates in which direction the panel has been mounted.
Some machines have the internal screen mounted with a rotation.
Since the panel orientation quirks need the n
The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies
to all
associated VFs. so guest driver can not directly enable the atomicOps for VF, it
depends on PF to enable it. In current design, amdgpu driver will get the
enabled
atomicOps bits through private pf2vf data
Signe
Yeah, but that IB test should use the indirect submission through the
scheduler as well.
Otherwise you have IB test and scheduler writing both to the ring buffer
at the same time and potentially corrupting it.
Christian.
Am 10.09.21 um 12:10 schrieb Pan, Xinhui:
[AMD Official Use Only]
we
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p
60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI),
1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD
[Public]
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
old mode 100644
new mode 100755
Please don't modify the file mode.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of shaoyunl
Sent: Friday, September 10, 2021 10:2
Am 2021-09-10 um 10:26 a.m. schrieb shaoyunl:
> The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies
> to all
> associated VFs. so guest driver can not directly enable the atomicOps for VF,
> it
> depends on PF to enable it. In current design, amdgpu driver will get the
The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies
to all
associated VFs. so guest driver can not directly enable the atomicOps for VF, it
depends on PF to enable it. In current design, amdgpu driver will get the
enabled
atomicOps bits through private pf2vf data
Signe
[AMD Official Use Only]
Good catch . my editor seems has auto complete feature and I just select the
first one . ☹
Thanks
Shaoyun.liu
-Original Message-
From: Kuehling, Felix
Sent: Friday, September 10, 2021 10:19 AM
To: amd-gfx@lists.freedesktop.org; Liu, Shaoyun
Subject: Re: [P
Am 2021-09-10 um 10:04 a.m. schrieb shaoyunl:
> The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies
> to all
> associated VFs. so guest driver can not directly enable the atomicOps for VF,
> it
> depends on PF to enable it. In current design, amdgpu driver will get the
The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies
to all
associated VFs. so guest driver can not directly enable the atomicOps for VF, it
depends on PF to enable it. In current design, amdgpu driver will get the
enabled
atomicOps bits through private pf2vf data
Signe
*sigh* yeah, you are probably right. Wouldn't be to simple if this would
be easy, doesn't it?
In this case you can also skip taking the reservation lock for the
pre-allocated BO, since there should absolutely be only one user at a time.
Christian.
Am 10.09.21 um 11:42 schrieb Pan, Xinhui:
[
[AMD Official Use Only]
Looks good to me .
Reviewed by Shaoyun.liu < shaoyun@amd.com>
-Original Message-
From: Kuehling, Felix
Sent: Friday, September 10, 2021 1:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: Re: [PATCH v3 1/1] drm/amdkfd: make needs_pcie_atomic
It should not unless we are OOM which should not happen during driver
initialization.
But there is another problem I'm thinking about: Do we still use UVD IB
submissions to forcefully tear down UVD sessions when a process crashes?
If yes that stuff could easily deadlock with an IB test execut
move BO allocation in sw_init.
Signed-off-by: xinhui pan
---
change from v1:
only use pre-allocated BO for direct IB submission.
and take its reservation lock to avoid any potential race.
better safe than sorry.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 103 +---
drivers/
alloc extra msg from direct IB pool.
Signed-off-by: xinhui pan
---
change from v1:
let addr align up to gpu page boundary.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27 -
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu
alloc extra msg from direct IB pool.
Reviewed-by: Christian König
Signed-off-by: xinhui pan
---
change from v1:
let addr align up to gpu page boundary.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 97 +++--
1 file changed, 44 insertions(+), 53 deletions(-)
diff --git a/dri
[AMD Official Use Only]
looks like amdgpu_debugfs_test_ib_show use direct IB submission too.
It parks the ring scheduler thread, and down read the reset_sem to avoid race
with gpu reset.
BUT, amdgpu_debugfs_test_ib_show itself could be called in parrel. Need fix it.
_
[AMD Official Use Only]
we need take this lock.
IB test can be triggered through debugfs. Recent days I usually test it by cat
gpu recovery and amdgpu_test_ib in debugfs.
发件人: Koenig, Christian
发送时间: 2021年9月10日 18:02
收件人: Pan, Xinhui; amd-gfx@lists.free
Vendor will define their own memory types on top of TTM_PL_PRIV,
but call ttm_set_driver_manager directly without checking mem_type
value when setting up memory manager. So add such check to aware
the case when array bounds.
v2: lower check level to WARN_ON
Signed-off-by: Leslie Shi
Signed-off-b
Remove all TA binary structures and add the specific binary
structure in struct ta_context.
Signed-off-by: Candice Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 23 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 122 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 23
[AMD Official Use Only]
oh, god. uvd free handler submit delayed msg which depends on scheduler with
reservation lock hold.
This is not allowed as commit c8e42d57859d "drm/amdgpu: implement more ib pools
(v2)" says
Any jobs which schedule IBs without dependence on gpu scheduler should use
DIREC
Add manual sclk/vddc setting supoort via pp_od_clk_voltage sysfs
to maintain consistency with other asics. As cyan skillfish doesn't
support DPM, there is only a single frequency and voltage to adjust.
v2: maintain consistency and add command guide.
v3: adjust user settings storage and coding styl
Add print_clk_levels and read_sensor pptable funcs for
cyan skilfish.
v2: keep consitency and add get_gpu_metrics callback.
v3: use sysfs_emit_at() in sysfs show function.
Signed-off-by: Lang Yu
Reviewed-by: Huang Rui
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 347 ++
Add SmuMetrics_t definition for cyan skilfish.
v2: update SmuMetrics_t definition.
v3: cleanup and rearrange the order of fields.
Signed-off-by: Lang Yu
Reviewed-by: Huang Rui
---
.../pm/inc/smu11_driver_if_cyan_skillfish.h | 86 ---
1 file changed, 35 insertions(+), 51 delet
Add some PPSMC MSGs for cyan skilfish.
Signed-off-by: Lang Yu
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/pm/inc/smu_v11_8_ppsmc.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_8_ppsmc.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_8_
Tested-by: Pierre-Eric Pelloux-Prayer
Thanks!
On 10/09/2021 05:17, Evan Quan wrote:
Current RUNPM mechanism relies on PMFW to master the timing for BACO
in/exit. And that needs cooperation from sound driver for dstate
change notification for function 1(audio). Otherwise(on sound driver
missing
[Public]
Hi Christian and Xinhui,
Thanks for your suggestion. The cause is I saw data corruption in several
proprietary use cases. BUILD_BUG_ON will have build variation per gcc
difference?
Anyway, WARN_ON is fine to me, and I will send a new patch set soon to address
this.
Regards,
Guchun
[AMD Official Use Only]
I am wondering if amdgpu_bo_pin would change BO's placement in the futrue.
For now, the new placement is calculated by new = old ∩ new.
发件人: Koenig, Christian
发送时间: 2021年9月10日 14:24
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄
Try that plugin here https://github.com/vivien/vim-linux-coding-style
I'm using it for years and it really helpful.
Christian.
Am 10.09.21 um 09:53 schrieb Pan, Xinhui:
[AMD Official Use Only]
I am using vim with
set tabstop=8
set shiftwidth=8
set softtabstop=8
__
[AMD Official Use Only]
I am using vim with
set tabstop=8
set shiftwidth=8
set softtabstop=8
发件人: Koenig, Christian
发送时间: 2021年9月10日 14:33
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander
主题: Re: [PATCH 4/4] drm/amdgpu: VCN avoid mem
On Wed, Sep 8, 2021 at 10:59 PM Christoph Hellwig wrote:
>
> While we're at it, with -Werror something like this is really futile:
Yeah, I'm thinking we could do
-Wno-error=cpp
to at least allow the cpp warnings to come through without being fatal.
Because while they can be annoying too, they
On Thu, Sep 9, 2021 at 4:43 AM Marco Elver wrote:
>
> Sure, but the reality is that the real stack size is already doubled
> for KASAN. And that should be reflected in Wframe-larger-than.
I don't think that's true.
Quite the reverse, in fact.
Yes, the *dynamic* stack size is doubled due to KASA
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