Re: [PATCH 2/3] drm/amd/pm: Fix incorrect power limit readback in smu11 if POWER_SOURCE_DC

2021-10-02 Thread Nils Wallménius
Hi, sorry for the drive-by comment but limit_param |= 0 << 24; Doesn't do anything. Best regards Nils Den sön 3 okt. 2021 06:47Darren Powell skrev: > when smu->adev->pm.ac_power == 0, message parameter with bit 16 set is > saved > to smu->current_power_limit. > > Fixes: 0cb4c62125a9 ("drm/

[PATCH 2/3] drm/amd/pm: Fix incorrect power limit readback in smu11 if POWER_SOURCE_DC

2021-10-02 Thread Darren Powell
when smu->adev->pm.ac_power == 0, message parameter with bit 16 set is saved to smu->current_power_limit. Fixes: 0cb4c62125a9 ("drm/amd/pm: correct power limit setting for SMU V11)" Signed-off-by: Darren Powell --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 9 + 1 file changed,

[PATCH 3/3] drm/amd/pm: explicitly initialize cached power limits in smu struct

2021-10-02 Thread Darren Powell
Code appears to initialize values but macro will exit without error or initializing value if function is not implmented Signed-off-by: Darren Powell --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/

[PATCH 0/3] Add limit_type to (pptable_funcs)->set_power_limit signature

2021-10-02 Thread Darren Powell
=== Description === Add limit_type to (pptable_funcs)->set_power_limit signature plus two small patches Fix for incorrect power limit readback in smu11 if POWER_SOURCE_DC Explicit initialization of cached power limits in smu struct === Test System === * DESKTOP(AMD FX-8350 + NAVI10(731F/ca)

[PATCH 1/3] amdgpu/pm: add limit_type to (pptable_funcs)->set_power_limit signature

2021-10-02 Thread Darren Powell
modify (pptable_funcs)->set_power_limit signature modify smu11 set_power_limit signature (arcturus, navi10, sienna_cichlid) modify smu13 set_power_limit signature (aldabaran) modify vangogh_set_power_limit signature (vangogh) === Test === sudo bash AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Disp

Re: [Intel-gfx] [PATCH v2 00/17] drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers where possible

2021-10-02 Thread Fernando Ramos
On 21/10/02 09:13AM, Fernando Ramos wrote: > > Sean, could you revert the whole patch series? I'll have a deeper look into > the > patch set and come up with a v3 where all these issues will be addressed. > Hi Sean, I now understand the nature of the issue that caused the problem with i915 and

Re: [Intel-gfx] [PATCH v2 00/17] drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers where possible

2021-10-02 Thread Fernando Ramos
On 21/10/02 09:13AM, Fernando Ramos wrote: > On 21/10/02 05:30AM, Ville Syrjälä wrote: > > On Sat, Oct 02, 2021 at 01:05:47AM +0300, Ville Syrjälä wrote: > > > On Fri, Oct 01, 2021 at 04:48:15PM -0400, Sean Paul wrote: > > > > On Fri, Oct 01, 2021 at 10:00:50PM +0300, Ville Syrjälä wrote: > > > > >

RE: [PATCH] drm/amdgpu: add missed write lock for pci detected state pci_channel_io_normal

2021-10-02 Thread Chen, Guchun
[Public] Hi Andrey, A new patch with subject "drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume" has been sent, pls review it. Thanks. Regards, Guchun -Original Message- From: Chen, Guchun Sent: Friday, October 1, 2021 11:21 PM To: Grodzovsky, Andrey ; am

[PATCH] drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume

2021-10-02 Thread Guchun Chen
In current code, when a PCI error state pci_channel_io_normal is detectd, it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI driver will continue the execution of PCI resume callback report_resume by pci_walk_bridge, and the callback will go into amdgpu_pci_resume finally, wher

Re: [PATCH 1/2] drm: Add Gamma and Degamma LUT sizes props to drm_crtc to validate.

2021-10-02 Thread Sean Paul
On Fri, Oct 01, 2021 at 04:34:34PM -0400, Sean Paul wrote: > On Wed, Sep 29, 2021 at 03:39:25PM -0400, Mark Yacoub wrote: > > From: Mark Yacoub > > > > [Why] > > 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma > > or Degamma props in the new CRTC state, allowing any inv

how to help pinpoint ring 0 stalling on resuming from suspend only when ShadowPrimary is disabled?

2021-10-02 Thread Paul Dufresne
Hi! I am a unsure how this message is appropriate here as most messages are patches. I have temporary access (while helping the computer with a full disk situation), to test a computer with RS780C GPU, where when resuming with default ShadowPrimary off, ring 0 stalled happens on almost each

Re: [Intel-gfx] [PATCH v2 00/17] drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers where possible

2021-10-02 Thread Fernando Ramos
On 21/10/02 05:30AM, Ville Syrjälä wrote: > On Sat, Oct 02, 2021 at 01:05:47AM +0300, Ville Syrjälä wrote: > > On Fri, Oct 01, 2021 at 04:48:15PM -0400, Sean Paul wrote: > > > On Fri, Oct 01, 2021 at 10:00:50PM +0300, Ville Syrjälä wrote: > > > > On Fri, Oct 01, 2021 at 02:36:55PM -0400, Sean Paul