[PATCH] mm/migrate.c: Remove MIGRATE_PFN_LOCKED

MIGRATE_PFN_LOCKED is used to indicate to migrate_vma_prepare() that a source page was already locked during migrate_vma_collect(). If it wasn't then the a second attempt is made to lock the page. However if the first attempt failed it's unlikely a second attempt will succeed, and the retry adds

Re: [PATCH] drm/amd/amdgpu: fix potential bad job hw_fence underflow

On 2021/10/23 上午4:41, Andrey Grodzovsky wrote: > > What do you mean by underflow in this case ? You mean use after free because > of extra dma_fence_put() ? yes > > On 2021-10-22 4:14 a.m., JingWen Chen wrote: >> ping >> >> On 2021/10/22 AM11:33, Jingwen Chen wrote: >>> [Why] >>> In advance tdr

RE: [PATCH] drm/amdgpu: Update TA version output in driver

[AMD Official Use Only] Reviewed-by: John Clements -Original Message- From: Li, Candice Sent: Monday, October 25, 2021 10:31 AM To: amd-gfx@lists.freedesktop.org Cc: Clements, John ; Li, Candice Subject: [PATCH] drm/amdgpu: Update TA version output in driver TA version should only

[PATCH] drm/amdgpu: Update TA version output in driver

TA version should only be displayed in firmware version column. Signed-off-by: Candice Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 14 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 ++--

[PATCH 33/33] drm/amd/display: move FPU associated DCN301 code to DML folder

From: Qingqing Zhuo [Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN301 to DML, where all FPU code should locate. Cc: Christian König Cc: Harry Wentland Cc: Rodrigo Siqueira Tested-by: Zhan Liu

[PATCH 30/33] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings

From: Wenjing Liu [why] As DP features expands, we have encountered many situations where we must configure a different DPCD lane setting from hw lane settings we output. The change is to decouple hw lane settings from dpcd lane settings to provide flexibility to configure dpcd and hw

[PATCH 25/33] drm/amd/display: Add workaround flag for EDID read on certain docks

From: Jimmy Kizito [Why] Certain docks appear to NAK I2C writes to the segment pointer with the MOT (middle of transaction) bit clear. This behaviour can cause EDID reads from higher segments to fail. [How] Add workaround flag for links which connect to docks exhibiting this issue. Cc: Wayne

[PATCH 31/33] drm/amd/display: add two lane settings training options

From: Wenjing Liu [why] option 1: disallow different lanes to have different lane settings option 2: dpcd lane settings will always use the same hw lane settings even if it doesn't match requested lane adjust Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Wenjing Liu ---

[PATCH 27/33] drm/amd/display: FEC configuration for dpia links in MST mode

From: Meenakshikumar Somasundaram [Why] To fix the check condition for fec enable for dpia links in MST mode. [How] dc_link_should_enable_fec() to be used to check whether fec should be enabled in MST mode. Cc: Wayne Lin Reviewed-by: Jimmy Kizito Acked-by: Rodrigo Siqueira Signed-off-by:

[PATCH 32/33] drm/amd/display: fix link training regression for 1 or 2 lane

From: Wenjing Liu [why] We have a regression that cause maximize lane settings to use uninitialized data from unused lanes. This will cause link training to fail for 1 or 2 lanes because the lane adjust is populated incorrectly sometimes. Reviewed-by: Eric Yang Acked-by: Rodrigo Siqueira

[PATCH 29/33] drm/amd/display: implement decide lane settings

From: Wenjing Liu [why] Decouple lane settings decision logic all to its own function. The function takes in lane adjust array and link training settings and decide what hw lane setting and dpcd lane setting should be used. Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by:

[PATCH 24/33] drm/amd/display: Set phy_mux_sel bit in dmub scratch register

From: Hansen [Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin

[PATCH 26/33] drm/amd/display: FEC configuration for dpia links

From: Meenakshikumar Somasundaram [Why] To fix the check condition for fec enable for dpia links. [How] dc_link_should_enable_fec() to be used to check whether fec should be enabled. Cc: Wayne Lin Reviewed-by: Jimmy Kizito Acked-by: Rodrigo Siqueira Signed-off-by: Meenakshikumar

[PATCH 18/33] drm/amd/display: set Layout properly for 8ch audio at timing validation

From: "Guo, Bing" Why: For audio packet type 0x02, there are 2 Layouts: Layout = 0 for 2 channels and Layout = 1 for > 2 channels. Layout will affect bandwidth check. Currently, for HDMI FRL, Layout field isn't set and has a default value of 0, so theoretically only 2-channel audio for audio

[PATCH 20/33] drm/amd/display: Remove unused macros

From: Anson Jacob fixed16_to_double & fixed16_to_double_to_cpu are not used. Reviewed-by: Rodrigo Siqueira Acked-by: Agustin Gutierrez Signed-off-by: Anson Jacob --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 3 ---

[PATCH 28/33] drm/amd/display: adopt DP2.0 LT SCR revision 8

From: Wenjing Liu [how] revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment in one 5 byte write aux transaction. It specifies to read aux rd interval value as soon as we turn on TPS1 pattern. Cc: Wayne Lin Acked-by: Rodrigo Siqueira Signed-off-by: Wenjing Liu ---

[PATCH 23/33] drm/amd/display: Manually adjust strobe for DCN303

From: Martin Leung why: DCN303's 4 channel SOC BB causes problems at strobe how: workaround to manually adjust strobe calculation using FCLK restrict. Reviewed-by: Jun Lei Acked-by: Agustin Gutierrez Signed-off-by: Martin Leung --- .../drm/amd/display/dc/dcn303/dcn303_resource.c| 14

[PATCH 22/33] drm/amd/display: 3.2.159

From: Aric Cyr This new DC version brings improvements in the following areas: - Improvements for USB4; - Isolate FPU code for DCN20, DCN301, and DSC; - Fixes on Linking training; - Refactoring some parts of the code, such as PSR; Acked-by: Agustin Gutierrez Signed-off-by: Aric Cyr ---

[PATCH 17/33] drm/amd/display: Fix 3DLUT skipped programming

From: Aric Cyr This reverts commit 3ae5ca4b92a5c230c3fe25956996ae4bf1875422. We found a compilation error that we thought was caused by the 3DLUT patch; later on, we figured out the root cause of the problem, but we already applied the revert in the wrong patch. This commit brings it back the

[PATCH 21/33] drm/amd/display: [FW Promotion] Release 0.0.90

From: Anthony Koo Acked-by: Agustin Gutierrez Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

[PATCH 16/33] drm/amd/display: 3.2.158

From: Aric Cyr Acked-by: Agustin Gutierrez Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 23977de4811b..4cd04a78f926 100644 ---

[PATCH 19/33] drm/amd/display: allow windowed mpo + odm

From: Dmytro Laktyushkin This change adds a config flag to allow non fullscreen MPO during ODM. Scaling calculation will still fail configurations where video is only one one side of the screen. Reviewed-by: Aric Cyr Acked-by: Agustin Gutierrez Signed-off-by: Dmytro Laktyushkin ---

[PATCH 13/33] drm/amd/display: Add comment for preferred_training_settings

From: George Shen [Why] Currently the naming of preferred_training_settings is ambiguous and has caused confusion regarding its purpose and usage. [How] Add comment to clarify the intention. Reviewed-by: Wenjing Liu Acked-by: Agustin Gutierrez Signed-off-by: George Shen ---

[PATCH 14/33] drm/amd/display: Handle I2C-over-AUX write channel status update

From: Aric Cyr [Why] When writing long AUX commands some sinks will respond will write status update requiring source to read status. [How] When a write request is replied with data (AUX_ACK_M), retry a read of write status to determine when the write is completed. Reviewed-by: Martin Leung

[PATCH 15/33] drm/amd/display: [FW Promotion] Release 0.0.89

From: Anthony Koo - Add flag to control root clock gating in init_hw - Add flag to indicate a diags environment is being used Acked-by: Agustin Gutierrez Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++--- 1 file changed, 6 insertions(+), 3

[PATCH 11/33] drm/amd/display: restyle dcn31 resource header inline with other asics

From: Dmytro Laktyushkin Style change for better consistency across codebase Reviewed-by: Nicholas Kazlauskas Acked-by: Agustin Gutierrez Signed-off-by: Dmytro Laktyushkin --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--

[PATCH 10/33] drm/amd/display: clean up dcn31 revision check

From: Dmytro Laktyushkin This is unnecessary in clk_mgr Reviewed-by: Nicholas Kazlauskas Acked-by: Agustin Gutierrez Signed-off-by: Dmytro Laktyushkin --- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git

[PATCH 12/33] drm/amd/display: Implement fixed DP drive settings

From: George Shen [Why] Currently there are use cases that require DP link to maintain fixed VS and PE in HW regardless of what the sink requests. BIOS integrated info table will specify whether we need to use the fixed drive settings, and the drive settings to use. [How] Implement changes to

[PATCH 07/33] drm/amd/display: fix a crash on USB4 over C20 PHY

From: Ahmad Othman [Why] Crash when USB4 is connected. [How] Added an ASIC specific code guard. Reviewed-by: Nikola Cornij Reviewed-by: Wenjing Liu Acked-by: Agustin Gutierrez Signed-off-by: Ahmad Othman --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 25 +++ 1 file

[PATCH 06/33] drm/amd/display: move FPU associated DSC code to DML folder

From: Qingqing Zhuo [Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König

[PATCH 08/33] drm/amd/display: Set i2c memory to light sleep during hw init

From: Michael Strauss [WHY] i2c memory doesn't get set to light sleep on hw init as intended [HOW] Set i2c to light sleep after reg gets zeroed, ensuring memory power control doesn't get disabled for any other DIO memory Reviewed-by: Haonan Wang Acked-by: Agustin Gutierrez Signed-off-by:

[PATCH 09/33] drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate

From: Michael Strauss [WHY] Every other CM LUT power down sequence is deferred to next vupdate as memory powerdown updates immediately while selecting LUTs is double buffered. Previous update to defer LUT power down missed GAMCOR and DSCL, causing some visible flicker when entering/exiting

[PATCH 03/33] drm/amd/display: Get ceiling for v_total calc

From: "Guo, Bing" Updating certain variable blanking calculations to use ceiling function. Reviewed-by: Chris Park Acked-by: Agustin Gutierrez Signed-off-by: Bing Guo --- .../drm/amd/display/modules/freesync/freesync.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-)

[PATCH 04/33] drm/amd/display: dc_link_set_psr_allow_active refactoring

From: Robin Chen [Why] To expose new power optimization flags to PSR interface. It allows the PSR related power features can be enabled separately base on different use scenarios. Reviewed-by: Anthony Koo Acked-by: Agustin Gutierrez Signed-off-by: Robin Chen ---

[PATCH 05/33] drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1

From: Ahmad Othman [Why] Created new fields that matches new B0 structs On DCN31 the mapping of DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this new mapping needed to be handled. [How] Mapped new structure based on new structs Added logic for mapping over A0 and B0 boards

[PATCH 02/33] drm/amd/display: dcn20_resource_construct reduce scope of FPU enabled

From: Anson Jacob Limit when FPU is enabled to only functions that does FPU operations for dcn20_resource_construct, which gets called during driver initialization. Enabling FPU operation disables preemption. Sleeping functions(mutex (un)lock, memory allocation using GFP_KERNEL, etc.) should

[PATCH 01/33] drm/amd/display: Align bw context with hw config when system resume

From: Lewis Huang [Why] When the vbios config and driver config are different, if we update clock to lower before call program_timing and program_pixel_clk, garbage appear. [How] Align bw context with hw config when system resume Reviewed-by: Anthony Koo Acked-by: Agustin Gutierrez

[PATCH 00/33] DC Patches October 24, 2020

This new DC version brings improvements in the following areas: - Improvements for USB4; - Isolate FPU code for DCN20, DCN301, and DSC; - Fixes on Linking training; - Refactoring some parts of the code, such as PSR; Thanks Ahmad Othman (2): drm/amd/display: Add support for USB4 on C20 PHY for