Am 25.11.21 um 02:56 schrieb Felix Kuehling:
Am 2021-11-24 um 5:58 p.m. schrieb Philip Yang:
[SNIP]
#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev),
(ih))
#define amdgpu_ih_decode_iv(adev, iv) \
(adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
+#define
Am 24.11.21 um 23:52 schrieb philip yang:
On 2021-11-24 10:33 a.m., Christian König wrote:
Am 24.11.21 um 16:23 schrieb philip yang:
[SNIP]
+/**
+ * amdgpu_ih_process1 - interrupt handler work for IH ring1
+ *
+ * @adev: amdgpu_device pointer
+ * @ih: ih ring to process
+ *
+ *
Am 24.11.21 um 21:20 schrieb Felix Kuehling:
Am 2021-11-24 um 10:23 a.m. schrieb philip yang:
#define amdgpu_ih_get_wptr(adev, ih)
(adev)->irq.ih_funcs->get_wptr((adev), (ih))
#define amdgpu_ih_decode_iv(adev, iv) \
(adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
+#define
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error. Currently,we just always do asic reset in the
amdgpu resume until sort out the PM abort case.
v2: Remove incomplete PM abort flag
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Wednesday, November 24, 2021 9:30 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
>
> Subject: Re: [PATCH v2] drm/amdgpu: reset asic after system-wide suspend
> aborted (v2)
>
>
>
> On
[Public]
I guess you need to add this IP version in nv_query_video_codecs as well.
With above clarified/fixed, this patch is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Jane Jian
Sent: Thursday, November 25, 2021 11:15 AM
To: Deucher, Alexander ; Chen, Guchun
[WHY]
for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia
bandwidth feature),
which will be mismatched with original vcn0 revision
[HOW]
add new version check for vcn0 disabled revision(3, 0, 192), typically modified
under
sriov mode
Signed-off-by: Jane Jian
Change-Id:
[Public]
A typo.
It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 2)?
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 192):
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
if (!amdgpu_sriov_vf(adev))
After modifying navi10 in previous commit, extend the changes so all
implementations of
pp_hwmgr_func->get_power_profile_mode and
pptable_funcs->get_power_profile_mode use
amdgpu_pp_profile_name
== Test ==
LOGFILE=pp_profile_strings.test.log
AMDGPU_PCI_ADDR=`lspci -nn | grep
== Description ==
All the power profile modes use the same strings (or a subset of)
Creating a public array of the strings will allow sharing rather than
duplicating for each chip
First patch only implements change for navi10, followup with other chips
== Changes ==
Create a declaration of
== Description ==
All the power profile modes use the same strings (or a subset of)
Creating a public array of the strings will allow sharing rather than
duplicating for each chip
First patch only implements change for navi10
Second patch extends the changes to all other implementations of
[Public]
It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 192)?
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 192):
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
if (!amdgpu_sriov_vf(adev))
Am 2021-11-15 um 2:30 p.m. schrieb Alex Sierra:
> Device Coherent type uses device memory that is coherently accesible by
> the CPU. This could be shown as SP (special purpose) memory range
> at the BIOS-e820 memory enumeration. If no SP memory is supported in
> system, this could be faked by
Am 2021-11-24 um 5:58 p.m. schrieb Philip Yang:
> IH ring1 is used to process GPU retry fault, overflow is enabled to
> drain retry fault because we want receive other interrupts while
> handling retry fault to recover range. There is no overflow flag set
> when wptr pass rptr. Use timestamp of
IH ring1 is used to process GPU retry fault, overflow is enabled to
drain retry fault because we want receive other interrupts while
handling retry fault to recover range. There is no overflow flag set
when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow
and drain retry fault.
On 2021-11-24 10:33 a.m., Christian
König wrote:
Am 24.11.21 um 16:23 schrieb philip yang:
[SNIP]
+/**
+ * amdgpu_ih_process1 - interrupt handler work for IH ring1
On 2021-11-24 12:28 p.m., Fangzhi Zuo wrote:
1. Parse DSC caps from PCON DPCD
2. Determine policy if decoding DSC at PCON
3. Enable/disable DSC at PCON
Signed-off-by: Fangzhi Zuo
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
On 11/24/21 8:36 AM, Alex Deucher wrote:
Use do_div.
Fixes: c34f1652a18c4b ("drm/amd/display: fixed an error related to 4:2:0/4:2:2
DSC")
Reported-by: kernel test robot
Reported-by: Randy Dunlap
Cc: Bing Guo
Signed-off-by: Alex Deucher
Acked-by: Randy Dunlap # build-tested
Thanks.
Hi Dave, Daniel,
Fixes for 5.16.
The following changes since commit 136057256686de39cc3a07c2e39ef6bc43003ff6:
Linux 5.16-rc2 (2021-11-21 13:47:39 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.16-2021-11-24
for you to
Am 2021-11-24 um 10:23 a.m. schrieb philip yang:
>>> #define amdgpu_ih_get_wptr(adev, ih)
>>> (adev)->irq.ih_funcs->get_wptr((adev), (ih))
>>> #define amdgpu_ih_decode_iv(adev, iv) \
>>> (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
>>> +#define amdgpu_ih_decode_iv_ts(adev, ih,
Hi all,
TL;DR - git bisection points to
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.4=61d861cf478576d85d6032f864360a34b26084b1
as causing an issue when changing power state after idle.
Since 5.15.0 I have had intermittent issues with my GPU failing to
On 2021-11-24 5:20 a.m., Jiapeng Chong wrote:
Fix the following coccicheck warning:
./drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c:96:14-15: WARNING
comparing pointer to 0.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
On 2021-11-24 13:55, Alex Deucher wrote:
> On Wed, Nov 24, 2021 at 1:52 PM Harry Wentland wrote:
>>
>> On 2021-11-24 11:36, Alex Deucher wrote:
>>> Update the bios scratch register when updating the backlight
>>> level. Some platforms apparently read this scratch register
>>> and do
On Wed, Nov 24, 2021 at 1:52 PM Harry Wentland wrote:
>
> On 2021-11-24 11:36, Alex Deucher wrote:
> > Update the bios scratch register when updating the backlight
> > level. Some platforms apparently read this scratch register
> > and do additional operations in their hotkey handlers.
> >
> >
On 2021-11-24 11:36, Alex Deucher wrote:
> Update the bios scratch register when updating the backlight
> level. Some platforms apparently read this scratch register
> and do additional operations in their hotkey handlers.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518
>
[AMD Official Use Only]
Reviewed-by: Bing Guo <
-Original Message-
From: Deucher, Alexander
Sent: Wednesday, November 24, 2021 11:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; kernel test robot
; Randy Dunlap ; Guo, Bing
Subject: [PATCH] drm/amd/display: fix 64
1. Parse DSC caps from PCON DPCD
2. Determine policy if decoding DSC at PCON
3. Enable/disable DSC at PCON
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 +-
2 files changed, 44
Use do_div.
Fixes: c34f1652a18c4b ("drm/amd/display: fixed an error related to 4:2:0/4:2:2
DSC")
Reported-by: kernel test robot
Reported-by: Randy Dunlap
Cc: Bing Guo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 ---
1 file changed, 4
Update the bios scratch register when updating the backlight
level. Some platforms apparently read this scratch register
and do additional operations in their hotkey handlers.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518
Signed-off-by: Alex Deucher
---
On 11/23/21 9:16 PM, Stephen Rothwell wrote:
Hi all,
Changes since 20211123:
on i386:
ld: drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.o: in function
`dscc_compute_dsc_parameters':
rc_calc_dpi.c:(.text+0x31f): undefined reference to `__udivdi3'
--
~Randy
Am 24.11.21 um 16:23 schrieb philip yang:
[SNIP]
+/**
+ * amdgpu_ih_process1 - interrupt handler work for IH ring1
+ *
+ * @adev: amdgpu_device pointer
+ * @ih: ih ring to process
+ *
+ * Interrupt handler of IH ring1, walk the IH ring1.
+ * Returns irq process return code.
+ */
+int
On 2021-11-24 4:37 a.m., Christian
König wrote:
Am
23.11.21 um 20:22 schrieb Philip Yang:
IH ring1 is used to process GPU retry
fault, overflow is enabled to
drain retry fault because we want receive other interrupts
Hello Yang Li,
This is a semi-automatic email about new static checker warnings.
The patch a689e8d1f800: "drm/amd/display: check top_pipe_to_program
pointer" from Nov 15, 2021, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3064
[AMD Official Use Only]
Series is:
Reviewed-by: Alex Deucher
From: Cui, Flora
Sent: Tuesday, November 23, 2021 9:43 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org
; Deucher, Alexander
Cc: Cui, Flora ; Alex Deucher
Subject: [PATCH 3/3] drm/amdgpu: check
On Wed, Nov 24, 2021 at 9:20 AM Jane Jian wrote:
>
> [WHY]
> for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia
> bandwidth feature),
> which will be mismatched with original vcn0 revision
>
> [HOW]
> add new version check for vcn0 disabled revision(3, 0, 192), typically
>
[WHY]
for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia
bandwidth feature),
which will be mismatched with original vcn0 revision
[HOW]
add new version check for vcn0 disabled revision(3, 0, 192), typically modified
under
sriov mode
Signed-off-by: Jane Jian
Change-Id:
On Wed, Nov 24, 2021 at 4:54 AM Jane Jian wrote:
>
> [WHY]
> for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia
> bandwidth feature),
> which will be mismatched with original vcn0 revision
>
> [HOW]
> add new version check for vcn0 disabled revision
>
> Signed-off-by: Jane
Fix the following coccicheck warning:
./drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c:96:14-15: WARNING
comparing pointer to 0.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Lv Ruyi
Both of split and merge are pointers, not arrays.
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
---
drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
On 11/24/2021 6:13 PM, Prike Liang wrote:
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error. Currently,we just always do asic reset in the
amdgpu resume until sort out the PM
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error. Currently,we just always do asic reset in the
amdgpu resume until sort out the PM abort case.
v2: Remove incomplete PM abort flag
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, November 24, 2021 19:35
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Pawar, Ashish
; Deucher, Alexander
Subject: [PATCH] drm/amdgpu: Skip ASPM
There is no need for additional programming, keep the default settings.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index
On 23/11/2021 22:39, Arunpravin wrote:
On 18/11/21 12:09 am, Matthew Auld wrote:
On 16/11/2021 20:18, Arunpravin wrote:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the
[WHY]
for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia
bandwidth feature),
which will be mismatched with original vcn0 revision
[HOW]
add new version check for vcn0 disabled revision
Signed-off-by: Jane Jian
Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58
---
Am 23.11.21 um 20:22 schrieb Philip Yang:
IH ring1 is used to process GPU retry fault, overflow is enabled to
drain retry fault because we want receive other interrupts while
handling retry fault to recover range. There is no overflow flag set
when wptr pass rptr. Use timestamp of rptr and wptr
46 matches
Mail list logo
