this is a workaround due to get ecc info failed during gpu recovery
[ 700.236122] amdgpu :09:00.0: amdgpu: Failed to export SMU ecc table!
[ 700.236128] amdgpu :09:00.0: amdgpu: GPU reset begin!
[ 704.331171] amdgpu: qcm fence wait loop timeout expired
[ 704.331194] amdgpu: The cp migh
Am 01.12.21 um 17:39 schrieb Arunpravin:
Move the base i915 buddy allocator code into drm
- Move i915_buddy.h to include/drm
- Move i915_buddy.c to drm root folder
- Rename "i915" string with "drm" string wherever applicable
- Rename "I915" string with "DRM" string wherever applicable
- Fix heade
Am 02.12.21 um 05:55 schrieb xinhui pan:
TTM want bo->resource to be valid during BO's life.
But ttm_bo_mem_space might fail and bo->resource point to NULL. Many code
touch bo->resource and hit panic then.
As old and new mem might overlap, move ttm_resource_free after
ttm_bo_mem_space is not an
145:
navi10IP_VERSION(10, 1, 10)
navi12IP_VERSION(10, 1, 2)
navi14IP_VERSION(10, 1, 1)
92:
sienna_cichlidIP_VERSION(10, 3, 0)
navy_flounder IP_VERSION(10, 3, 2)
vangogh IP_VERSION(10, 3, 1)
dimgrey_cavefish IP_VERSION(10, 3, 4)
beige_goby
Am 01.12.21 um 22:35 schrieb Alex Deucher:
For SR-IOV, the IP discovery revision number encodes
additional information. Handle that case here.
v2: drop additional IP versions
Signed-off-by: Alex Deucher
I was already wondering why SRIOV needs special handling for the
revision, going to kee
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Stanley.Yang
Sent: Thursday, December 2, 2021 16:02
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Clements, John ; Zhou1, Tao ; Li,
Candice ; Chai, Thomas
Cc: Yang, Stanley
Subject: [
[AMD Official Use Only]
>-Original Message-
>From: Grodzovsky, Andrey
>Sent: Thursday, December 2, 2021 12:01 AM
>To: Christian König ; Yu, Lang
>; Koenig, Christian ; amd-
>g...@lists.freedesktop.org
>Cc: Deucher, Alexander ; Lazar, Lijo
>; Huang, Ray
>Subject: Re: [PATCH] drm/amdgpu:
dm_check_crtc_cursor() doesn't take into account plane transforms when
calculating plane scaling, this can result in false positives.
For example, if there's an output with resolution 3840x2160 and the
output is rotated 90 degrees, CRTC_W and CRTC_H will be 3840 and 2160,
respectively, but SRC_W a
Have you tested this? I have a similar patch, but the cursor position was off
when I tried it.
On 12/2/21 14:21, Simon Ser wrote:
Have you tested this? I have a similar patch, but the cursor position was off
when I tried it.
Works fine on my machine with RX 5700 XT.
Cheers,
vlad
On Thu, 25 Nov 2021 at 20:42, Felix Kuehling wrote:
>
> OK. Dealing with processed timestamp rather than decoded timestamp fixes
> the race condition where drain would have returned before the last fault
> was processed. But we're still assuming that each interrupt has a unique
> timestamp. We hav
dm_check_crtc_cursor() doesn't take into account plane transforms when
calculating plane scaling, this can result in false positives.
For example, if there's an output with resolution 3840x2160 and the
output is rotated 90 degrees, CRTC_W and CRTC_H will be 3840 and 2160,
respectively, but SRC_W a
[AMD Official Use Only]
> From: chen gong
> Sent: Thursday, December 2, 2021 3:56 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Sider, Graham ; Gong, Curry
>
> Subject: [PATCH] drm/amdkfd: Correct the value of the
> no_atomic_fw_version variable
>
> 145:
> navi10IP_VERSION(10, 1, 10)
On 12/2/2021 8:39 AM, Evan Quan wrote:
Those APIs are used only by legacy ASICs(si/kv). They cannot be
shared by other ASICs. So, we create a new holder for them.
Signed-off-by: Evan Quan
Change-Id: I555dfa37e783a267b1d3b3a7db5c87fcc3f1556f
--
v1->v2:
- rename amdgpu_pm_compute_clocks as
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of chen gong
Sent: Thursday, December 2, 2021 3:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Sider, Graham ; Gong, Curry
Subject: [PATCH] drm/amdkfd: Correct the value of the no_atomic_fw_version
variabl
On 12/2/2021 8:39 AM, Evan Quan wrote:
Drop cross callings and multi-function APIs. Also avoid exposing
internal implementations details.
Signed-off-by: Evan Quan
Change-Id: I55e5ab3da6a70482f5f5d8c256eed2f754feae20
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 2 +-
drivers/gpu/d
On 2021-12-02 7:52 a.m., Vlad Zahorodnii wrote:
dm_check_crtc_cursor() doesn't take into account plane transforms when
calculating plane scaling, this can result in false positives.
For example, if there's an output with resolution 3840x2160 and the
output is rotated 90 degrees, CRTC_W and CRTC_
On 12/2/2021 8:39 AM, Evan Quan wrote:
Avoid cross callings which make lock protection enforcement
on amdgpu_dpm_force_performance_level() impossible.
Signed-off-by: Evan Quan
Change-Id: Ie658140f40ab906ce2ec47576a086062b61076a6
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 29 ++
On 2021-12-02 7:43 a.m., Mike Lothian
wrote:
On Thu, 25 Nov 2021 at 20:42, Felix Kuehling wrote:
OK. Dealing with processed timestamp rather than decoded timestamp fixes
the race condition where drain would have returned before the last faul
Display Core (DC) is one of the components under amdgpu, and it has
multiple features directly related to the KMS API. Unfortunately, we
don't have enough documentation about DC in the upstream, which makes
the life of some external contributors a little bit more challenging.
For these reasons, thi
Display core provides a feature that makes it easy for users to debug
Multiple planes by enabling a visual notification at the bottom of each
plane. This commit introduces how to use such a feature.
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 34 ++
Display core documentation is not well organized, and it is hard to find
information due to the lack of sections. This commit reorganizes the
documentation layout, and it is preparation work for future changes.
Changes since V1:
- Christian: Group amdgpu documentation together.
- Daniel: Drop redu
Display core provides a feature that makes it easy for users to debug
Pipe Split. This commit introduces how to use such a debug option.
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 28 +--
1 file changed, 26 insertions(+), 2 deletions(-)
d
Introduce how to collect DTN log from debugfs.
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst
b/Documentation/gpu/amdgpu/display/dc-debug.rst
i
In the DC driver, we have multiple acronyms that are not obvious most of
the time; the same idea is valid for amdgpu. This commit introduces a DC
and amdgpu glossary in order to make it easier to navigate through our
driver.
Changes since V1:
- Yann: Divide glossary based on driver context.
- Al
This commit describes how DCN works by providing high-level diagrams
with an explanation of each component. In particular, it details the
Global Sync signals.
Signed-off-by: Rodrigo Siqueira
---
.../gpu/amdgpu/display/config_example.svg | 414 ++
.../amdgpu/display/dc_pipeline_overview.
Applied. Thanks!
Alex
On Thu, Dec 2, 2021 at 11:17 AM Zhou Qingyang wrote:
>
> In amdgpu_connector_lcd_native_mode(), the return value of
> drm_mode_duplicate() is assigned to mode, and there is a dereference
> of it in amdgpu_connector_lcd_native_mode(), which will lead to a NULL
> pointer der
Applied. thanks!
Alex
On Thu, Dec 2, 2021 at 10:09 AM Kazlauskas, Nicholas
wrote:
>
> On 2021-12-02 7:52 a.m., Vlad Zahorodnii wrote:
> > dm_check_crtc_cursor() doesn't take into account plane transforms when
> > calculating plane scaling, this can result in false positives.
> >
> > For example
Applied. Thanks!
Alex
On Wed, Dec 1, 2021 at 10:16 AM Christian König
wrote:
>
> Am 01.12.21 um 16:13 schrieb Zhou Qingyang:
> > In radeon_driver_open_kms(), radeon_vm_bo_add() is assigned to
> > vm->ib_bo_va and passes and used in radeon_vm_bo_set_addr(). In
> > radeon_vm_bo_set_addr(), there
On 12/2/21 16:54, Kazlauskas, Nicholas wrote:
On 2021-12-02 7:52 a.m., Vlad Zahorodnii wrote:
dm_check_crtc_cursor() doesn't take into account plane transforms when
calculating plane scaling, this can result in false positives.
For example, if there's an output with resolution 3840x2160 and the
Hi Dave, Daniel,
New stuff for 5.17.
The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:
Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-next-5.17-2021-12-02
for you to
This adds a new IOCTL currently used to implement querying
and setting the stable power state for GPU profiling. The
stable pstates use fixed clocks and disable certain power
features in order to get accurate pipeline profiling.
Currently this is handled via sysfs, and that is still
available, bu
So mesa and tools know when this is available.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0e27f9673f8f..b50c
To support better memory access performance on non-Large BAR devices, use
SDMA copies instead of MM access.
SDMA access is restricted to PAGE_SIZE'd access to account for the PTRACED
process memory r/w operation use case. Any other access size will use
MMIO.
Failure to do an SDMA copy will resul
TTM want bo->resource to be valid during BO's life.
But ttm_bo_mem_space might fail and bo->resource point to NULL. Many code
touch bo->resource and hit panic then.
As old and new mem might overlap, move ttm_resource_free after
ttm_bo_mem_space is not an option.
Lets create BO in CPU domain first
[AMD Official Use Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, December 2, 2021 10:45 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Feng, Kenneth
> Subject: Re: [PATCH V3 09/17] drm/amd/pm: optimize the
> amdgpu
[AMD Official Use Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, December 2, 2021 11:38 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Feng, Kenneth
> Subject: Re: [PATCH V3 16/17] drm/amd/pm: revise the performanc
Those implementation details(whether swsmu supported, some ppt_funcs supported,
accessing internal statistics ...)should be kept internally. It's not a good
practice and even error prone to expose implementation details.
Signed-off-by: Evan Quan
Change-Id: Ibca3462ceaa26a27a9145282b60c6ce5deca775
amdgpu_pm.c holds all the user sysfs/hwmon interfaces. It's another
client of our power APIs. It's not proper to spike into power
implementation details there.
Signed-off-by: Evan Quan
Change-Id: I397853ddb13eacfce841366de2a623535422df9a
--
v1->v2:
- drop unneeded "return;" in amdgpu_dpm_get_cu
Display is another client of our power APIs. It's not proper to spike
into power implementation details there.
Signed-off-by: Evan Quan
Change-Id: Ic897131e16473ed29d3d7586d822a55c64e6574a
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c |
Move them to amdgpu_dpm.c instead.
Signed-off-by: Evan Quan
Change-Id: I59fe0efcb47c18ec7254f3624db7a2eb78d91b8c
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 25 +++--
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 23 ---
2 files changed, 23 insertions(+), 25
Move it to kv_dpm.c instead.
Signed-off-by: Evan Quan
Change-Id: I554332b386491a79b7913f72786f1e2cb1f8165b
--
v1->v2:
- rename the API with "kv_" prefix(Alex)
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 23 -
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 --
drivers/gp
Move them to si_dpm.c instead.
Signed-off-by: Evan Quan
Change-Id: I288205cfd7c6ba09cfb22626ff70360d61ff0c67
--
v1->v2:
- rename the API with "si_" prefix(Alex)
v2->v3:
- rename other data structures used only in si_dpm.c(Lijo)
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 25 -
drive
As it lables an internal pm state and amdgpu_pm structure is the more
proper place than amdgpu_device structure for it.
Signed-off-by: Evan Quan
Change-Id: I7890e8fe7af2ecd8591d30442340deb8773bacc3
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 6 +++
Those APIs are used only by legacy ASICs(si/kv). They cannot be
shared by other ASICs. So, we create a new holder for them.
Signed-off-by: Evan Quan
Change-Id: I555dfa37e783a267b1d3b3a7db5c87fcc3f1556f
--
v1->v2:
- rename amdgpu_pm_compute_clocks as amdgpu_dpm_compute_clocks(Lijo)
v2->v3:
- a
Instead of putting them in amdgpu_dpm.c.
Signed-off-by: Evan Quan
Change-Id: Ieb7ed5fb6140401a7692b401c5a42dc53da92af8
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c| 14 --
drivers/gpu/drm/amd/pm/inc/hwmgr.h | 3 ---
.../gpu/drm/amd/pm/powerplay/hwmgr/smu8_
Drop cross callings and multi-function APIs. Also avoid exposing
internal implementations details.
Signed-off-by: Evan Quan
Change-Id: I55e5ab3da6a70482f5f5d8c256eed2f754feae20
--
v1->v2:
- add back the adev->pm.dpm_enabled check(Lijo)
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 2 +-
We should avoid having multi-function APIs. It should be up to the caller
to determine when or whether to call amdgpu_dpm_dispatch_task().
Signed-off-by: Evan Quan
Change-Id: I78ec4eb8ceb6e526a4734113d213d15a5fbaa8a4
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 18 ++
drivers/gpu/dr
Drop those unused APIs and data structures.
Signed-off-by: Evan Quan
Change-Id: I57d2a03dcda02d0b5d9c5ffbdd37bffe49945407
---
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 49 -
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4 ++
2 files changed, 4 insertions(+), 49 deletions(-)
This can cover the power implementation details. And as what did for
powerplay framework, we hook the smu_context to adev->powerplay.pp_handle.
Signed-off-by: Evan Quan
Change-Id: I3969c9f62a8b63dc6e4321a488d8f15022ffeb3d
--
v1->v2:
- drop smu_ppt_limit_type used internally from kgd_pp_interfac
Those gfxoff controls added for some specific ASICs are unnecessary.
The functionalities are not affected without them. Also to align with
other ASICs, they should also be dropped.
Signed-off-by: Evan Quan
Change-Id: Ia8475ef9e97635441aca5e0a7693e2a515498523
---
drivers/gpu/drm/amd/pm/swsmu/amdg
Instead of centralizing all headers in the same folder. Separate them into
different folders and place them among those source files those who really
need them.
Signed-off-by: Evan Quan
Change-Id: Id74cb4c7006327ca7ecd22daf17321e417c4aa71
---
drivers/gpu/drm/amd/pm/Makefile | 10 ++
As the only entry point, it's now safe and reasonable to
enforce the lock protections in amdgpu_dpm.c. And with
this, we can drop other internal used power locks.
Signed-off-by: Evan Quan
Change-Id: Iad228cad0b3d8c41927def08965a52525f3f51d3
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c| 719 ++
Avoid cross callings which make lock protection enforcement
on amdgpu_dpm_force_performance_level() impossible.
Signed-off-by: Evan Quan
Change-Id: Ie658140f40ab906ce2ec47576a086062b61076a6
--
v1->v2:
- drop unused enable_umd_pstate callback(Lijo)
---
drivers/gpu/drm/amd/include/amd_shared.h
skip get ecc info for aldebarn through check ip version
do not affect other asic type
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgp
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Stanley.Yang
Sent: Friday, December 3, 2021 13:30
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Clements, John ; Zhou1, Tao ; Li,
Candice ; Chai, Thomas
Cc: Yang, Stanley
Subject: [PA
The general hw fini sequence is SMU-> ... ->SDMA-> ...
We need to send power gate message to power off SDMA(in SDMA hw_fini())
afer dpm is disabled(in SMU hw_fini()). Allow that for APU.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
1 file changed, 1 insertion(+),
Currently, we don't find some neccesities to power on/off
SDMA in SMU hw_init/fini(). It makes more sense in SDMA
hw_init/fini().
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
Well NAK.
We already discussed this and decided to not use any hardware
acceleration for the debug access.
Apart from that you implementation is absolutely horrible and won't work
in all cases.
Regards,
Christian.
Am 02.12.21 um 22:43 schrieb Jonathan Kim:
To support better memory access
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