[AMD Official Use Only]
I think you need to describe more details on why the hive reset on guest side
is not necessary and how host and guest driver will work together to handle
the hive reset . You should have 2 patches together as a serials to handle
the FLR and mode 1 reset on XGMI co
From: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a43c008bd0f2..7d87a
From: Aric Cyr
Reduce stack usage by moving an unnecessary structure copy to a pointer.
Reviewed-by: Joshua Aberback
Acked-by: Pavle Kotarac
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/driver
From: Nicholas Kazlauskas
[Why]
To avoid hanging RDPCSPIPE when INTERCEPTB isn't set.
DMCUB owns control of that bit so DMCUB should manage returning the
information driver needs for link encoder control.
[How]
Add a new DMCUB command to return dp alt disable and dp4 information.
Reviewed-by:
From: Wenjing Liu
[why]
A debug option is needed to temporarily force dp2 new link training
fallback method for debugging purpose.
Reviewed-by: George Shen
Acked-by: Pavle Kotarac
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++---
drivers/gpu/drm/a
From: Anthony Koo
Acked-by: Pavle Kotarac
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
in
From: Oliver Logush
[why]
Need to fix the code so it does not use reserved keywords
[how]
Change the total_length member of the cea struct
Reviewed-by: Anthony Koo
Acked-by: Pavle Kotarac
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/
From: Meenakshikumar Somasundaram
[Why]
Need to have dpia debug bits for configuring hpd delay.
[How]
Added hpd_delay_in_ms variable in dpia_debug_options.
Reviewed-by: Jimmy Kizito
Acked-by: Pavle Kotarac
Signed-off-by: meenakshikumar somasundaram
---
drivers/gpu/drm/amd/display/dc/dc.h |
From: Jude Shih
[Why]
We shouldn't be accessing res_pool funcs from DM level,
therefore, we should create API and let the flow
be done in DC level.
[How]
We create new interface dp_get_link_enc to access and get the correct link_enc
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Kotarac
S
From: Wayne Lin
[Why]
crc_rd_wrk shouldn't be null in crc_win_update_set(). Current programming
logic is inconsistent in crc_win_update_set().
[How]
Initially, return if crc_rd_wrk is NULL. Later on, we can use member of
crc_rd_wrk safely.
Reported-by: kernel test robot
Reported-by: Dan Carpen
From: Mikita Lipski
[why/how]
The function can be called on boot or after suspend when
links are not initialized, to prevent it guard it with
NULL pointer check
Reviewed-by: Nicholas Kazlauskas
Acked-by: Pavle Kotarac
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/dc/dc_link.h
From: Jarif Aftab
[WHY]
-To ensure dc->res_pool has been initialized
[HOW]
-Check if dc->res_pool is true in
the if statement
Reviewed-by: Martin Leung
Acked-by: Pavle Kotarac
Signed-off-by: Jarif Aftab
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 d
From: Wyatt Wood
[Why]
When HPD IRQ occurs, it triggers a PSR disable and reenable
directly through dc layer.
Since it does not pass through the power layer, the layer
that tracks whether PSR is enabled or disabled and which
masks are set, this layer is now out of sync with the real
PSR state in
From: Nicholas Kazlauskas
[Why]
The HW interrupt gets disabled after S3/S4/reset so we don't receive
notifications for HPD or AUX from DMUB - leading to timeout and
black screen with (or without) DPIA links connected.
[How]
Re-enable the interrupt after S3/S4/reset like we do for the other
DC in
From: George Shen
[Why]
Certain LTTPR require output VS/PE to be explicitly
set during PHY test automation.
[How]
Add vendor-specific sequence to set LTTPR
output VS/PE.
Reviewed-by: Jun Lei
Acked-by: Pavle Kotarac
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c
From: George Shen
[Why]
Some of the vendor-specific workarounds added for transparent mode
also need to be applied to non-transparent mode in order to succeed
link training consistently.
[How]
Remove transparent mode check for the required workarounds.
Reviewed-by: Jun Lei
Acked-by: Pavle Kota
This new DC version brings improvements in the following areas:
- Improvements for USB4;
- Isolate FPU code for DCN20, DCN301, and DSC;
- Fixes on Linking training;
- Refactoring some parts of the code, such as PSR;
For sriov vf hang, vf flr will be triggered. Hive reset is not needed.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amd
> De: "Rodrigo Siqueira"
> Objet: [PATCH v2 5/6] Documentation/gpu: Add basic overview of DC pipeline
>
> This commit describes how DCN works by providing high-level diagrams
> with an explanation of each component. In particular, it details the
> Global Sync signals.
>
> Signed-off-by: Rodrigo
On Fri, Dec 3, 2021 at 7:15 AM Christian König
wrote:
>
> Am 02.12.21 um 20:19 schrieb Alex Deucher:
> > This adds a new IOCTL currently used to implement querying
> > and setting the stable power state for GPU profiling. The
> > stable pstates use fixed clocks and disable certain power
> > featu
On Fri, Dec 3, 2021 at 7:07 AM Lazar, Lijo wrote:
>
>
>
> On 12/3/2021 12:49 AM, Alex Deucher wrote:
> > This adds a new IOCTL currently used to implement querying
> > and setting the stable power state for GPU profiling. The
> > stable pstates use fixed clocks and disable certain power
> > featu
Fix following coccicheck warning:
./drivers/gpu/drm/amd/amdkfd/kfd_svm.c:2193:16-17: WARNING opportunity
for max().
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Thursday, December 2, 2021 3:39 AM
> To: Limonciello, Mario
> Cc: Liang, Prike ; amd-gfx list g...@lists.freedesktop.org>; Deucher, Alexander
> ; Lazar, Lijo ; Huang,
> Ray
> Subject: Re: [v3] drm/amdgpu: reset asic after syste
Am 02.12.21 um 20:19 schrieb Alex Deucher:
This adds a new IOCTL currently used to implement querying
and setting the stable power state for GPU profiling. The
stable pstates use fixed clocks and disable certain power
features in order to get accurate pipeline profiling.
Currently this is handl
On 12/3/2021 12:49 AM, Alex Deucher wrote:
This adds a new IOCTL currently used to implement querying
and setting the stable power state for GPU profiling. The
stable pstates use fixed clocks and disable certain power
features in order to get accurate pipeline profiling.
Currently this is ha
On 12/3/2021 12:24 PM, Lang Yu wrote:
The general hw fini sequence is SMU-> ... ->SDMA-> ...
We need to send power gate message to power off SDMA(in SDMA hw_fini())
afer dpm is disabled(in SMU hw_fini()). Allow that for APU.
This message is not right. In APUs there is no message provided by
On Fri, Dec 03, 2021 at 05:31:53PM +0800, Jiapeng Chong wrote:
> Fix following coccicheck warning:
>
> ./drivers/gpu/drm/amd/amdkfd/kfd_svm.c:2193:16-17: WARNING opportunity
> for max().
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_svm.c |
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