Re: [PATCH 1/2] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

On 1/24/2022 12:13 PM, Lang Yu wrote: Some clients(e.g., kfd) query sclk/mclk through this function. Before this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 0Mhz After this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency:

Re: [PATCH 2/2] drm/amd/pm: use existing fini_smc_tables function for cyan skillfish

On Mon, Jan 24, 2022 at 02:43:42PM +0800, Yu, Lang wrote: > Remove redundant code and use general smu_v11_0_fini_smc_tables function. > > Signed-off-by: Lang Yu Reviewed-by: Huang Rui > --- > .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c| 18 +- > 1 file changed, 1 insertion

Re: [PATCH 1/2] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

On Mon, Jan 24, 2022 at 02:43:41PM +0800, Yu, Lang wrote: > Some clients(e.g., kfd) query sclk/mclk through this function. > > Before this patch: > # /opt/rocm/opencl/bin/clinfo > > Max clock frequency: 0Mhz > > After this patch: > # /opt/rocm/opencl/bin/clinfo > >

Re: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

On Mon, Jan 24, 2022 at 11:20:42AM +0800, Huang, Tim wrote: > Use IP versions rather than asic_type to differentiate IP version specific > features. > > Signed-off-by: Tim Huang > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +--- > 1 file changed, 5 insertions(+), 7 del

Re: [PATCH 2/3] drm/amdgpu: convert to UVD IP version checking

On Mon, Jan 24, 2022 at 11:20:41AM +0800, Huang, Tim wrote: > Use IP versions rather than asic_type to differentiate IP version specific > features. > > Signed-off-by: Tim Huang Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++-- > 1 file changed, 7 insertion

Re: [PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

On Mon, Jan 24, 2022 at 11:20:40AM +0800, Huang, Tim wrote: > Use IP versions rather than asic_type to differentiate IP version specific > features. > > Signed-off-by: Tim Huang Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++ > 1 file ch

Re: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler

Am 21.01.22 um 21:34 schrieb Sharma, Shashank: From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001 From: Somalapuram Amaranath Date: Fri, 21 Jan 2022 14:19:42 +0530 Subject: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler This patch adds a GPU reset handler for Navi

Re: [PATCH 2/4] drm/amdgpu: add work function for GPU reset

Am 21.01.22 um 21:37 schrieb Sharma, Shashank: From c598dd586dd15fc5ae0a883a2e6f4094ec024085 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 21 Jan 2022 17:33:10 +0100 Subject: [PATCH 2/4] drm/amdgpu: add work function for GPU reset This patch adds a new work function, which will get

Re: [PATCH 3/4] drm/amdgpu: add reset register trace dump function

Am 21.01.22 um 21:34 schrieb Sharma, Shashank: From 1c5c552eeddaffd9fb3e7d45ece1b2b28fccc575 Mon Sep 17 00:00:00 2001 From: Somalapuram Amaranath Date: Fri, 21 Jan 2022 14:19:10 +0530 Subject: [PATCH 3/4] drm/amdgpu: add reset register trace dump function for  gfx_v10_0 Implementation of regi

[PATCH] drm/amdgpu: add determine passthrough under arm64

add determine for passthrough mode under arm64 by reading CurrentEL register Signed-off-by: Victor Zhao --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index c5

[PATCH 2/2] drm/amd/pm: use existing fini_smc_tables function for cyan skillfish

Remove redundant code and use general smu_v11_0_fini_smc_tables function. Signed-off-by: Lang Yu --- .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c| 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/dr

[PATCH 1/2] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

Some clients(e.g., kfd) query sclk/mclk through this function. Before this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 0Mhz After this patch: # /opt/rocm/opencl/bin/clinfo Max clock frequency: 1500Mhz Signed-off-by: Lang Yu

RE: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[AMD Official Use Only] Tim， Please remove TAB in the beginning of an empty line and the SPACE in the end of a line. With this fixed, series is: Reviewed-by: Aaron Liu aaron@amd.com -- Best Regards Aaron Liu > -Original Message- > From: Huang, Tim

RE: [PATCH 1/5] drm/amdgpu: set APU flag based on IP discovery table

[AMD Official Use Only] Reviewed-by: Aaron Liu -- Best Regards Aaron Liu > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Saturday, January 22, 2022 4:22 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH 1/5] drm/amdgpu: set APU

Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported' member of smu_feature structure

On 1/24/2022 9:51 AM, Quan, Evan wrote: [AMD Official Use Only] -Original Message- From: Lazar, Lijo Sent: Friday, January 21, 2022 5:37 PM To: Quan, Evan ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Chen, Guchun ; Huang, Ray Subject: Re: [PATCH 3/7] drm/amd/pm: drop

RE: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported' member of smu_feature structure

[AMD Official Use Only] > -Original Message- > From: Lazar, Lijo > Sent: Friday, January 21, 2022 5:37 PM > To: Quan, Evan ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Chen, Guchun > ; Huang, Ray > Subject: Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported' > memb

RE: [PATCH 4/5] drm/amdgpu: handle BACO synchronization with secondary funcs

[AMD Official Use Only] > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Saturday, January 22, 2022 4:22 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH 4/5] drm/amdgpu: handle BACO synchronization with > secondary funcs > > Ex

RE: [PATCH] drm/amdgpu/pm/smu7: drop message about VI performance levels

[AMD Official Use Only] Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Saturday, January 22, 2022 4:22 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/pm/smu7: drop message about VI > perform

[PATCH 3/3] drm/amd/display: convert to DCE IP version checking

Use IP versions rather than asic_type to differentiate IP version specific features. Signed-off-by: Tim Huang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

[PATCH 2/3] drm/amdgpu: convert to UVD IP version checking

Use IP versions rather than asic_type to differentiate IP version specific features. Signed-off-by: Tim Huang --- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amd

[PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

Use IP versions rather than asic_type to differentiate IP version specific features. Signed-off-by: Tim Huang --- drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++ 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/dri

RE: [PATCH v2 0/3] Implement parallel sysfs_emit solution for navi10

[AMD Official Use Only] The whole idea seems fine to me. Just some nitpicks for patch1 and patch3. BR Evan > -Original Message- > From: Powell, Darren > Sent: Saturday, January 22, 2022 11:47 AM > To: amd-gfx@lists.freedesktop.org > Cc: Powell, Darren > Subject: [PATCH v2 0/3] Implement

RE: [PATCH 3/3] amdgpu/pm: Add Error Handling to emit_clocks stack

[AMD Official Use Only] It seems this patch should be combined with patch1. Rather than as a separate patch. BR Evan > -Original Message- > From: Powell, Darren > Sent: Saturday, January 22, 2022 11:47 AM > To: amd-gfx@lists.freedesktop.org > Cc: Powell, Darren > Subject: [PATCH 3/3] a

RE: [PATCH 1/3] amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset

[AMD Official Use Only] > -Original Message- > From: Powell, Darren > Sent: Saturday, January 22, 2022 11:47 AM > To: amd-gfx@lists.freedesktop.org > Cc: Powell, Darren > Subject: [PATCH 1/3] amdgpu/pm: Implement new API function "emit" that > accepts buffer base and write offset > >

[PATCH 1/2] drm/amd/display: Fix FP start/end for dcn30_internal_validate_bw.

It calls populate_dml_pipes which uses doubles to initialize the scale_ratio_depth params. Mirrors the dcn20 logic. Signed-off-by: Bas Nieuwenhuizen --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/a

[PATCH 2/2] drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU.

Mirrors the logic for dcn30. Cue lots of WARNs and some kernel panics without this fix. Signed-off-by: Bas Nieuwenhuizen --- .../gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 11 +++ .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c| 2 +- .../gpu/drm/amd/display/dc/dml/dcn30

Re: [RFC PATCH v3 1/3] drm: introduce fb_modifiers_not_supported flag in mode_config

Hello Esaki-san, On Fri, Jan 14, 2022 at 07:17:51PM +0900, Tomohito Esaki wrote: > If only linear modifier is advertised, since there are many drivers that > only linear supported, the DRM core should handle this rather than > open-coding in every driver. However, there are legacy drivers such as

Re: [RFC PATCH v3 3/3] drm: remove allow_fb_modifiers

Hello Esaki-san, Thank you for the patch. On Fri, Jan 14, 2022 at 07:17:53PM +0900, Tomohito Esaki wrote: > The allow_fb_modifiers flag is unnecessary since it has been replaced > with cannot_support_modifiers flag. The new flag is fb_modifiers_not_supported, not cannot_support_modifiers. > Sig

Re: [RFC PATCH v3 2/3] drm: add support modifiers for drivers whose planes only support linear layout

Hello Esaki-san, Thank you for the patch. On Fri, Jan 14, 2022 at 07:17:52PM +0900, Tomohito Esaki wrote: > The LINEAR modifier is advertised as default if a driver doesn't specify > modifiers. > > Signed-off-by: Tomohito Esaki > --- > drivers/gpu/drm/drm_plane.c | 15 --- > includ

[PATCH 19/24] drm/amd/display: Remove unnecessary function definition

From: Aric Cyr Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 - drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +- 3 files changed, 1 insertion(+), 9 deletion

[PATCH 21/24] drm/amd/display: Fix disabling dccg clocks

From: David Galiffi [How & Why] Updated procedure to match hardware programming guide. Reviewed-by: Eric Yang Acked-by: Rodrigo Siqueira Signed-off-by: David Galiffi --- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 7 +++ .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 44 ---

[PATCH 24/24] drm/amd/display: add debug option for z9 disable interface

From: Eric Yang [Why] To help triage issues and coordinate driver/bios release dependency [How] Only enable the new Z9 interface when debug option is set, otherwise treat Z10 only support case as Zstate disallowed. Reviewed-by: Nicholas Kazlauskas Acked-by: Rodrigo Siqueira Signed-off-by: Eri

[PATCH 23/24] drm/amd/display: fix zstate allow interface to PMFW

From: Eric Yang [Why] psr_feature_enabled flag is dynamically updated, and sometimes when zstate allow status is determined the flag has not been set to true yet even on PSR enabled config, lid off/on is such a case, which will result in zstate disabled even though PSR is supported. [How] Check

[PATCH 20/24] drm/amd/display: allow set dp drive setting when stream is not present

From: Wenjing Liu [why] There is a change previously to disallow DM to set dp drive setings when stream is not present. The logic might not work well with DP PHY complaince scenario with a PHY test fixture attachment. We need to make the method allow DP link drive settings changes even without st

[PATCH 18/24] drm/amd/display: 3.2.170

From: Aric Cyr This version brings along the following fixes: - Z9 improvements - Clocks management adjustments - Code cleanup - Improve DSC and MST code Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 delet

[PATCH 22/24] drm/amd/display: Disable physym clock

From: David Galiffi [How & Why] Disable physym clock when it's not in use. Reviewed-by: Eric Yang Acked-by: Rodrigo Siqueira Signed-off-by: David Galiffi --- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 8 ++- .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 62 --- .../gp

[PATCH 17/24] drm/amd/display: Reset preferred training settings immediately

From: Wayne Lin [Why & How] In order to easily test ilr by immediately reset the preferred training settings, fix the code to disable skip_immediate_retrain. Reviewed-by: Solomon Chiu Acked-by: Rodrigo Siqueira Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_deb

[PATCH 15/24] drm/amd/display: Update VSC HDR infoPacket on TF change

From: Reza Amini [why] OnSetSourceContentAttribute it does not trigger an update for the VSC with TF change. [how] In this call, create a new VSC infoPacket based on the new config, and allow DisplayTarget decide if an update and pursuant passive flip is necessary Reviewed-by: Krunoslav Kovac

[PATCH 14/24] drm/amd/display: remove PHY repeater count check for LTTPR mode

From: Sung Joon Kim [why] Due to bad hardware, the PHY repeater count in LTTPR cap is read as 0xFF in some monitors while the LTTPR is actually present. [how] Remove PHY repeater counter check when configuring LTTPR mode. Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Sung Joo

[PATCH 13/24] drm/amd/display: Basic support with device ID

From: Oliver Logush [why] Need to add Cyan Skillfish support by adding the correct Device ID Reviewed-by: Charlene Liu Acked-by: Rodrigo Siqueira Signed-off-by: Oliver Logush --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2

[PATCH 12/24] drm/amd/display: Support synchronized indirect reg access

From: Roy Chan [Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to trace. [How] Using cgs service, which provide a sync indirect reg access api. Reviewed-by: Aric Cyr Acked-by: Rodrigo Siqueira Signed-off

[PATCH 11/24] drm/amd/display: Add DSC Enable for Synaptics Hub

From: Fangzhi Zuo DSC sequence for non virtual dpcd synaptics hub Reviewed-by: Hersen Wu Acked-by: Rodrigo Siqueira Signed-off-by: Fangzhi Zuo --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 48 +++ .../amd/display/include/ddc_service_types.h | 3 ++ 2 files changed, 5

[PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.101.0

From: Anthony Koo - Add Scr8 for GPINT messaging between driver and fw Acked-by: Rodrigo Siqueira Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dm

[PATCH 04/24] drm/amd/display: Change error to warning when hpd remains low for eDP

From: Varone [WHY?] SKUs that contain an unused eDP connector will throw an error when no display is connected. [HOW?] Change error to a warning. Reviewed-by: Martin Leung Acked-by: Rodrigo Siqueira Signed-off-by: Dillon Varone --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

[PATCH 09/24] drm/amd/display: Add Synaptics Fifo Reset Workaround

From: Fangzhi Zuo Sequence to reset synaptics SDP fifo before enabling first stream Reviewed-by: Hersen Wu Acked-by: Rodrigo Siqueira Signed-off-by: Fangzhi Zuo --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 133 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-

[PATCH 10/24] drm/amd/display: Retrieve MST Downstream Port Status

From: Fangzhi Zuo Determine if DFP present and the type of downstream device based on dsc_aux Reviewed-by: Hersen Wu Acked-by: Rodrigo Siqueira Signed-off-by: Fangzhi Zuo --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 23

[PATCH 08/24] drm/amd/display: Add Cable ID support for native DP

From: "Shen, George" [Why/How] We need to handle cable capabilities for cables that support cable ID. The cable attributes are intersected with the verified link caps to determine appropriate max link rate. After determining cable attributes we update the DP receiver. Reviewed-by: Wenjing Liu A

[PATCH 07/24] drm/amd/display: Use PSR version selected during set_psr_caps

From: Nicholas Kazlauskas [Why] If the DPCD caps specifies a PSR version newer than PSR_VERSION_1 then we fallback to using PSR_VERSION_1 in amdgpu_dm_set_psr_caps. This gets overriden with the raw DPCD value in amdgpu_dm_link_setup_psr, which can result in DMCUB hanging if we pass in an unsuppo

[PATCH 06/24] drm/amd/display: Change return type of dm_helpers_dp_mst_stop_top_mgr

From: Ian Chen Prepare for future dm can have different implementation depends on the return value. Reviewed-by: Wenjing Liu Acked-by: Rodrigo Siqueira Signed-off-by: Ian Chen --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 --- drivers/gpu/drm/amd/display/dc/core/dc_l

[PATCH 03/24] drm/amd/display: Driver support for MCLK query tool

From: Alvin Lee Implement handling for escape call to query the MCLK switch support for the current display config. Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee --- .../drm/amd/display/dc/dml/display_mode_vba.c | 24 +++ .../drm/amd/display/dc/dml/

[PATCH 05/24] drm/amd/display: Only set PSR version when valid

From: Nicholas Kazlauskas [Why] DMCUB will hang if we send a PSR unsupported set version command. This can occur if we fall-through into the default case in the switch statement for PSR version. [How] Add an unsupported check after the switch statement. Reviewed-by: Anthony Koo Acked-by: Rodr

[PATCH 02/24] drm/amd/display: do not compare integers of different widths

From: Josip Pavic [Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by: Anthony Koo Acked-by: Rodrigo Siqueira Signed-off-by: Josip Pavic --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletio

[PATCH 01/24] drm/amd/display: add protection in link encoder matching logic

From: Martin Tsai [Why] Link encoders are created based on its engine ID. The position of a link encoder in an array could be null since it didn't be allocated. Current matching logic didn't consider this situation and could get null encoder. [How] To add null encoder check to make the matching

[PATCH 00/24] DC Patches Jan 23, 2022

This DC patchset brings improvements in multiple areas. In summary, we have: - Z9 improvements - Clocks management adjustments - Code cleanup - Improve DSC and MST code Thanks Siqueira Alvin Lee (1): drm/amd/display: Driver support for MCLK query tool Anthony Koo (1): drm/amd/display: [F

RE: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval

[Public] Series is: Reviewed-by: Guchun Chen guchun.c...@amd.com Regards, Guchun From: Deucher, Alexander Sent: Saturday, January 22, 2022 1:00 AM To: Chen, Guchun ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in d