Fix two coverity warning's double free and and an uninitialized pointer
read. Both tmp and new are pointing at same address and both are freed
which leads to double free. Freeing tmp in the condition after new is
assigned with new address fixes the double free issue. new is not
initialized to null
On the GC 10.3.7 platform the initial MEC release version #3 can support
atomic operation,so need correct and set its MEC atomic support version to #3.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd
[AMD Official Use Only - General]
Reviewed-by: Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of Prike
> Liang
> Sent: Monday, July 11, 2022 4:55 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> ; Huang, Ray
> Subject: [PATCH] drm/amdkfd: corre
That would be redundant. GDS handling has always worked in the way that
the storage is thrown away after an IB.
My LRU patch set should have helped with GDS out of memory errors, but
I'm not sure how far along we are with rebasing amd-staging-drm-next.
Christian.
Am 08.07.22 um 16:58 schrieb
Am 09.07.22 um 04:31 schrieb Mr. B34r:
From: Vannoonnoo
divide error: [#1] SMP PTI
CPU: 3 PID: 78925 Comm: tee Not tainted 5.15.50-1-lts #1
5c320a339f0e397222fdfc9449eff04c0b12ea83
Hardware name: MSI MS-7A59/Z270 SLI PLUS (MS-7A59), BIOS 1.90 01/30/2018
RIP: 0010:smu_v11_0_set_fan_speed_r
On 07.07.22 21:03, Alex Sierra wrote:
> From: Alistair Popple
>
> Currently any attempts to pin a device coherent page will fail. This is
> because device coherent pages need to be managed by a device driver, and
> pinning them would prevent a driver from migrating them off the device.
>
> Howev
On 07.07.22 21:03, Alex Sierra wrote:
> From: Alistair Popple
>
> migrate_vma_setup() checks that a valid vma is passed so that the page
> tables can be walked to find the pfns associated with a given address
> range. However in some cases the pfns are already known, such as when
> migrating devi
SMU is always alive, so it's fine to skip SMU FW reloading
when runpm resumed from BACO, this can avoid some race issues
when resuming SMU FW.
Suggested-by: Evan Quan
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a
SMU will perform dpm disablement when entering BACO,
and enable them later on, so talking to SMU to get
enabled features in runpm cycle as BACO support check
is not reliable. Hence, use a cached value to fix it.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +++
From: Michel Dänzer
Requires enabling the vblank machinery for them.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2030
Signed-off-by: Michel Dänzer
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 43 +--
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a
On 08.07.22 23:25, Felix Kuehling wrote:
> On 2022-07-08 07:28, David Hildenbrand wrote:
>> On 07.07.22 21:03, Alex Sierra wrote:
>>> [WHY]
>>> Have a cleaner way to expose all page zone helpers in one header
>> What exactly is a "page zone"? Do you mean a buddy zone as in
>> include/linux/mmzone.h
On 11.07.22 16:00, Matthew Wilcox wrote:
> On Mon, Jul 11, 2022 at 03:35:42PM +0200, David Hildenbrand wrote:
>>> + /*
>>> +* Device coherent pages are managed by a driver and should not
>>> +* be pinned indefinitely as it prevents the driver moving the
>>> +
On Mon, Jul 11, 2022 at 03:35:42PM +0200, David Hildenbrand wrote:
> > + /*
> > +* Device coherent pages are managed by a driver and should not
> > +* be pinned indefinitely as it prevents the driver moving the
> > +* page. So when trying to pin with FO
On Mon, Jul 11, 2022 at 9:58 AM Guchun Chen wrote:
>
> SMU is always alive, so it's fine to skip SMU FW reloading
> when runpm resumed from BACO, this can avoid some race issues
> when resuming SMU FW.
>
> Suggested-by: Evan Quan
> Signed-off-by: Guchun Chen
> ---
> drivers/gpu/drm/amd/amdgpu/a
On Mon, Jul 11, 2022 at 9:58 AM Guchun Chen wrote:
>
> SMU will perform dpm disablement when entering BACO,
> and enable them later on, so talking to SMU to get
> enabled features in runpm cycle as BACO support check
> is not reliable. Hence, use a cached value to fix it.
>
> Signed-off-by: Guchun
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U
Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
Sapphire Pulse RX5700XT
Reference AMD RX6800
Engineering board with Ryzen 9 5900H
These systems were tested on the following displ
Various DCE versions had trouble with 36 bpp lb depth, requiring fixes,
last time in commit 353ca0fa5630 ("drm/amd/display: Fix 10bit 4K display
on CIK GPUs") for DCE-8. So far >= DCE-11.2 was considered ok, but now I
found out that on DCE-11.2 it causes dithering when there shouldn't be
any, so id
On 7/8/22 14:56, Aurabindo Pillai wrote:
From: Samson Tam
[Why]
When playing NV12 1080p MPO video, it is pipe splitting so
we see two pipes in fullscreen and four pipes in windowed
mode. Pipe split is happening because we are setting
MaximumMPCCombine = 1
[How]
Algorithm for MaximumMPCCombin
To expose unified memory for ctx save/resotre area feature
availablity to libhsakmt.
Signed-off-by: Eric Huang
---
include/uapi/linux/kfd_ioctl.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 7a423855a8
It is to add new option for always keeping gpu mapping
and bump KFD version for the feature of unified save
restore memory.
Signed-off-by: Eric Huang
Change-Id: Iebee35e6de4d52fa29f82dd19f6bbf5640249492
---
include/linux/kfd_ioctl.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
dif
To improve performance on queue preemption, allocate ctx s/r
area in VRAM instead of system memory, and migrate it back
to system memory when VRAM is full.
Signed-off-by: Eric Huang
Change-Id: If775782027188dbe84b6868260e429373675434c
---
include/hsakmttypes.h | 1 +
src/queues.c |
On 2022-07-11 14:41, Eric Huang wrote:
To expose unified memory for ctx save/resotre area feature
availablity to libhsakmt.
Signed-off-by: Eric Huang
Reviewed-by: Felix Kuehling
---
include/uapi/linux/kfd_ioctl.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/inc
On 2022-07-07 17:23, Philip Yang wrote:
Move process queues cleanup to deferred work kfd_process_wq_release, to
avoid potential deadlock circular locking warning:
WARNING: possible circular locking dependency detected
the existing dependency chain (in reverse order) is:
Add register values to access GFXOFF data for vangogh GPU.
Signed-off-by: André Almeida
---
.../pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h
b/drivers/gpu/drm
This patchset adds support to get current status of GFXOFF in vangogh.
Given that the rest of the interface is already implemented, we just
need to plug one function.
This is implemented just for vangogh and not for all smu11 devices given
that this is specific for this device, and not to all the
Implement function to get current GFXOFF status for vangogh.
Signed-off-by: André Almeida
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/sm
On Mon, Jul 11, 2022 at 3:20 PM André Almeida wrote:
>
> Add register values to access GFXOFF data for vangogh GPU.
>
> Signed-off-by: André Almeida
> ---
> .../pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h | 12
> 1 file changed, 12 insertions(+)
>
> diff --git
> a/drivers/gpu/
Implement function to get current GFXOFF status for vangogh.
Signed-off-by: André Almeida
---
Changes from v1:
- Squash commits in a single one
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 +++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu
From: Fangzhi Zuo
[why]
The first MST sideband message returns AUX_RET_ERROR_HPD_DISCON on
a certain Intel platform. Aux transaction is considered a failure if HPD
unexpectedly pulled low. The actual aux transaction success in such
case, hence do not return an error. Several Dell Intel-based Prec
On 7/11/2022 16:52, Rodrigo Siqueira wrote:
From: Fangzhi Zuo
[why]
The first MST sideband message returns AUX_RET_ERROR_HPD_DISCON on
a certain Intel platform. Aux transaction is considered a failure if HPD
unexpectedly pulled low. The actual aux transaction success in such
case, hence do not
From: Fangzhi Zuo
[why]
The first MST sideband message returns AUX_RET_ERROR_HPD_DISCON on
a certain Intel platform. Aux transaction is considered a failure if HPD
unexpectedly pulled low. The actual aux transaction success in such
case, hence do not return an error. Several Dell Intel-based Prec
On 7/11/2022 17:10, Rodrigo Siqueira wrote:
From: Fangzhi Zuo
[why]
The first MST sideband message returns AUX_RET_ERROR_HPD_DISCON on
a certain Intel platform. Aux transaction is considered a failure if HPD
unexpectedly pulled low. The actual aux transaction success in such
case, hence do not
From: Leo Li
When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain when pinning.
For example, this can happen if the user requests to create a BO in GTT
domain for di
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4112a8699ae2eac797415b9be1d7901b3f79e772 Add linux-next specific
files for 20220711
Error/Warning reports:
https://lore.kernel.org/llvm/202207090100.acxdj79h-...@intel.com
https
From: Yefim Barashkin
divide error: [#1] SMP PTI
CPU: 3 PID: 78925 Comm: tee Not tainted 5.15.50-1-lts #1
Hardware name: MSI MS-7A59/Z270 SLI PLUS (MS-7A59), BIOS 1.90 01/30/2018
RIP: 0010:smu_v11_0_set_fan_speed_rpm+0x11/0x110 [amdgpu]
Speed is user-configurable through a file.
I accident
TTM used to track the "acc_size" of all BOs internally. We needed to
keep track of it in our memory reservation to avoid TTM running out
of memory in its own accounting. However, that "acc_size" accounting
has since been removed from TTM. Therefore we don't really need to
track it any more.
Signed
This keeps track of kfd system mem used and kfd ttm mem used.
Signed-off-by: Alex Sierra
Reviewed-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 3 +++
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 19 +++
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c |
[WHY]
Unified memory with xnack off should be tracked, as userptr mappings
and legacy allocations do. To avoid oversuscribe system memory when
xnack off.
[How]
Exposing functions reserve_mem_limit and unreserve_mem_limit to SVM
API and call them on every prange creation and free.
Signed-off-by: Al
divide error: [#1] SMP PTI
CPU: 3 PID: 78925 Comm: tee Not tainted 5.15.50-1-lts #1
Hardware name: MSI MS-7A59/Z270 SLI PLUS (MS-7A59), BIOS 1.90 01/30/2018
RIP: 0010:smu_v11_0_set_fan_speed_rpm+0x11/0x110 [amdgpu]
Speed is user-configurable through a file.
I accidentally set it to zero, and
From: Le Ma
Allocate and enable aggregated doorbell.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 58 -
3 files changed, 70 insertions(+), 6 dele
From: Le Ma
Ring aggregated doorbel to make unmapped queue scheduled in mes firmware.
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 82 +
drivers/gpu/d
Allocate and enable aggregated doorbell.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 58 +-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 8dbce
Port aggregated doorbell support to gfx11.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 82 ++
1 file changed, 71 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 9
Port aggregated doorbell support to sdma6.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 80 ++
1 file changed, 57 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 8
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Jack Xiao
Sent: Tuesday, July 12, 2022 10:55
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack
Subject: [PATCH 5/5] drm/amdgpu/sdma6: add aggregated doo
On 21/06/2022 11:42, Luben Tuikov wrote:
This reverts commit e68efb27647f2106d6b545667f35b2ea39746b57.
We see that the bo validate list gets corrupted, in
amdgpu_cs_list_validate(), the lobj->tv.bo is NULL. Then getting usermm on
the next line, references a NULL bo and we get a koops.
Bisecting
On 2022-07-11 23:22, Tales Lelo da Aparecida wrote:
> On 21/06/2022 11:42, Luben Tuikov wrote:
>> This reverts commit e68efb27647f2106d6b545667f35b2ea39746b57.
>>
>> We see that the bo validate list gets corrupted, in
>> amdgpu_cs_list_validate(), the lobj->tv.bo is NULL. Then getting usermm on
>>
Good point. We should limit it in BACO only once an ASIC supports BOCO and BACO
together.
Regards,
Guchun
-Original Message-
From: Alex Deucher
Sent: Monday, July 11, 2022 11:29 PM
To: Chen, Guchun
Cc: amd-gfx list ; Deucher, Alexander
; Zhang, Hawking ; Lazar,
Lijo ; Quan, Evan ; F
[AMD Official Use Only - General]
Thanks for the fix! Patch is reviewed-by: Evan Quan
BR
Evan
> -Original Message-
> From: amd-gfx On Behalf Of
> Yefim Barashkin
> Sent: Tuesday, July 12, 2022 10:01 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yefim Barashkin
> Subject: [PATCH] drm/amd
Re: Do we need to handle this differently for BOCO?
No. feature mask applies both for BOCO and BACO.
I have a discussion with Evan, we shall focus on BACO bit instead of the whole
feature mask to simply this patch. So will try to update it.
Regards,
Guchun
-Original Message-
From: Alex
[AMD Official Use Only - General]
Acked-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> André Almeida
> Sent: Tuesday, July 12, 2022 3:35 AM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; David
> Airlie ; Daniel Vetter ; Zhang, Hawking
> ; Zhou1, Tao ;
After removing the context lock by patch e68efb27647f21 ("drm/amdgpu:
remove ctx->lock"), we see BO list corruption as documented in the bug of
the link below. While reverting removal of the context lock does fix the
issue, a more comprehensive approach was suggested, which this patch
implements. I
Protect the struct amdgpu_bo_list with a mutex. This is used during command
submission in order to avoid buffer object corruption as recorded in
the link below.
Suggested-by: Christian König
Cc: Alex Deucher
Cc: Andrey Grodzovsky
Cc: Vitaly Prosyak
Link: https://gitlab.freedesktop.org/drm/amd/
SMU is always alive, so it's fine to skip SMU FW reloading
when runpm resumed from BACO, this can avoid some race issues
when resuming SMU FW.
v2: Exclude boco case if an ASIC supports both boco and baco
Suggested-by: Evan Quan
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_p
SMU will perform dpm disablement when entering BACO,
and enable them later on, so talking to SMU to get
enabled features mask in runpm cycle as BACO support
check is not reliable. Hence, use a cached baco flag
to fix it.
v2: cache this flag in load sequence to simplify code (from Evan)
Signed-off
Instead of doing this way, suggest to cache the run_pm_mode in
struct amdgpu_pm {
}
You could cache the run_pm modes in kms logic -
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c#L183
Afterwards, you may use the cached value for any check
For ex: adev-
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