Hi Xiaojian,
Please move the power up IPU to "smu->is_apu" as Evan' comment and make sure
this is only called for PSP FW load type as
backdoor loading already included this in the IMU start process. After this,
Series is
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original
Seperately accumulate a statistic of rounded up allocations to use
to report availability, with a view to increasing the likelihood a
buffer object can be successfully allocated at exactly the size
reported by the availability API.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
Rounding up allocations in the allocation path caused test regressions,
so now just round in the availability path.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
Sorry for taking a while on respinning this! I've been busy with trying to
review as much nouveau patches as possible before we passed the deadline for
getting pulled into the kernel, since we've got quite a lot of pending patches
coming up. The pull deadline we had from Dave has passed at this
Am 2022-07-27 um 23:30 schrieb Yu Zhe:
time_is_before_jiffies deals with timer wrapping correctly.
Signed-off-by: Yu Zhe
Thank you. This patch looks good to me. I'm applying it to
amd-staging-drm-next.
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 4
On Fri, Jul 22, 2022 at 2:33 PM Jason Baron wrote:
>
>
>
> On 7/20/22 11:32, Jim Cromie wrote:
> > Add kernel_param_ops and callbacks to apply a class-map to a
> > sysfs-node, which then can control classes defined in that class-map.
> > This supports uses like:
> >
> > echo 0x3 >
On Thu, Jul 28, 2022 at 4:34 PM Rodrigo Siqueira
wrote:
>
> We got a report from Stephen/Michael that the PowerPC build was failing
> with the following error:
>
> ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float,
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses
We got a report from Stephen/Michael that the PowerPC build was failing
with the following error:
ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
ld: failed to merge target specific data of file
The variables OutputBPP, VTotal_Min,
TotalBandwidthConsumedGBytePerSecond, BandwidthSupport,
dummy_integer_array, dummysinglestring,
SurfaceRequiredDISPCLKWithoutODMCombine, SurfaceRequiredDISPCLK,
MinVoltageLevel, and MaxVoltageLevel are never used. So, remove the
variables entries from the
The variables PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE,
RefreshRate, FECEnable, ScalerRecoutWidth, MaxNumDP2p0Streams, and
MaxNumDP2p0Outputs are only used on assignments, so there values are not
used on code. So, remove the variables entries from the struct
vba_vars_st.
Signed-off-by:
On 2022-07-28 06:30, Victor Zhao wrote:
To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.
v2: move skip mode2 flag part separately
Signed-off-by: Victor Zhao
---
On 2022-07-28 06:30, Victor Zhao wrote:
In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset
v2: add a hang flag to indicate the reset comes from a job timeout,
skip ring
The TFinalxFill variable from the struct vba_vars_st is only used
on assignments, so its value is not used on code. So,
remove the TFinalxFill entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ---
The MaximumDCCCompressionYSurface variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. So,
remove the MaximumDCCCompressionYSurface entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
.../amd/display/dc/dml/dcn21/display_mode_vba_21.c
The WritebackAllowFCLKChangeEndPosition variable from the struct
vba_vars_st is only used on assignments, so its value is not used on
code. So, remove the WritebackAllowFCLKChangeEndPosition entry
from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
The NumberOfDP2p0Support variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. So,
remove the NumberOfDP2p0Support entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2
The MPCCombineEnable variable from the struct vba_vars_st is only
used on assignments, so its value is not used on code. So, remove
the MPCCombineEnable entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 1 -
The ModeIsSupported variable from the struct vba_vars_st is only used on
assignments, so its value is not used on code. So, remove the
ModeIsSupported entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 1 -
The ImmediateFlipSupportedSurface variable from the struct
vba_vars_st is only used on assignments, so its value is not used
on code. So, remove the ImmediateFlipSupportedSurface entry from the struct
vba_vars_st.
Signed-off-by: Maíra Canal
---
The SwathWidthCSingleDPP variable from the struct vba_vars_st is only
used on assignments, so its value is not used on code. So, remove the
SwathWidthCSingleDPP entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2
The variables XFCSupported, XFCTSlvVupdateOffset, XFCSlaveVupdateWidth,
XFCSlaveVReadyOffset, XFCTransferDelay, XFCPrechargeDelay,
XFCRemoteSurfaceFlipLatency and XFCPrefetchMargin are are only
used on assignments, so their values are not used on code. So, remove
the variables entries from the
The variables VStartupMargin and FirstMainPlane from the struct
vba_vars_st are only used on assignments, so there values are not used
on code. So, remove the variables entries from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
.../display/dc/dml/dcn20/display_mode_vba_20.c | 14
The AllowDRAMSelfRefreshDuringVBlank variable from the struct vba_vars_st
is only used on assignments, so its value is not used on code. So, remove
it the AllowDRAMSelfRefreshDuringVBlank entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
The DSCCLK_calculated variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the DSCCLK_calculated
entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
The variables CompBufReservedSpaceZs, CompBufReservedSpace64B and
CompBufReservedSpaceNeedAdjustment from the struct vba_vars_st are
only used on assignments, so their values are not used on code. Moreover,
their getter functions are not used also. So, remove the variables
entries from the struct
The NonUrgentLatencyTolerance variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the
NonUrgentLatencyTolerance entry from the struct vba_vars_st.
Signed-off-by: Maíra Canal
---
A while ago, I sent a patch removing some entries from the struct vba_vars_st
[1]. At that time, I used git grep and checked if they were used anywhere else
manually. But the struct vba_vars_st has more than 900 variables, so git grep
every variable is a pretty huge work. So, I grabbed all the
[Public]
> -Original Message-
> From: Liu, Shaoyun
> Sent: July 28, 2022 1:10 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org
> Cc: Kim, Jonathan
> Subject: RE: [PATCH] drm/amdgpu: fix hive reference leak when reflecting
> psp topology info
>
> [AMD Official Use Only -
[AMD Official Use Only - General]
Looks good to me .
BTW , why we didn't catch it on baremetal mode ?
Reviewed-by: Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Jonathan Kim
Sent: Thursday, July 28, 2022 1:06 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kim, Jonathan
Hives that require psp topology info to be reflected will leak hive
reference so fix it.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
On 28/07/2022 15:33, Arunpravin Paneer Selvam wrote:
Apply new intersect and compatible callback instead
of having a generic placement range verfications.
v2: Added a separate callback for compatiblilty
checks (Christian)
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer
On 28/07/2022 15:33, Arunpravin Paneer Selvam wrote:
Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.
v2: move the bits that are specific to buddy_man (Matthew)
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
Hi Matthew,
On 7/26/2022 4:11 PM, Matthew Auld wrote:
On 25/07/2022 12:42, Arunpravin Paneer Selvam wrote:
Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.
v2: move the bits that are specific to buddy_man (Matthew)
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 39
Apply new intersect and compatible callback instead
of having a generic placement range verfications.
v2: Added a separate callback for compatiblilty
checks (Christian)
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45
Implemented a new intersect and compatible callback function
fetching the start offset from struct ttm_resource.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/nouveau/nouveau_mem.c | 29 +++
Implemented a new intersect and compatible callback function
fetching start offset from backend drm buddy allocator.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 38
We are adding two new callbacks to ttm resource manager
function to handle intersection and compatibility of
placement and resources.
v2: move the amdgpu and ttm_range_manager changes to
separate patches (Christian)
v3: rename "intersect" to "intersects" (Matthew)
Signed-off-by: Christian
Implemented a new intersect and compatible callback functions
to ttm range manager fetching start offset from drm mm range
allocator.
Signed-off-by: Christian König
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/ttm/ttm_range_manager.c | 33 +
1 file
Am 2022-07-27 um 23:52 schrieb Alex Deucher:
On Wed, Jul 27, 2022 at 7:08 PM Felix Kuehling wrote:
Don't drop the stub fence reference after installing it as a replacement
for the eviction fence. dma_resv_replace_fences doesn't take another
reference to the fence, so it takes ownership of the
manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
which causes drm_crtc_vblank_get in vrr_transition to fail, and later
when drm_crtc_vblank_put is called the refcount on vblank will be messed
up. Therefore move the call to after manage_dm_interrupts.
Unchecked calls to
Introduce amdgpu_reset_level debugfs in order to help debug and
test specific type of reset. Also helps blocking unwanted type of
resets.
By default, mode2 reset will not be enabled
v2: make this debugfs in adev and use debugfs_create_u32
Signed-off-by: Victor Zhao
---
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 26 +++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 72 +++
For some hang caused by slow tests, engine cannot be stopped which
may cause resume failure after reset. In this case, force halt
engine by reverting context addresses
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset
v2: add a hang flag to indicate the reset comes from a job timeout,
skip ring test and cp halt wait in this case
- introduce AMDGPU_SKIP_MODE2_RESET flag
- let mode2 reset fallback to default reset method if failed
v2: move this part out from the asic specific part
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.
v2: move skip mode2 flag part separately
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
Of course, I will move it under "smu->is_apu".
Thanks,
Xiaojian
>-Original Message-
>From: Quan, Evan
>Sent: 2022年7月28日 16:14
>To: Du, Xiaojian ; amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander ; Huang, Tim
>; Du, Xiaojian ; Zhang, Yifan
>
>Subject: RE: [PATCH 1/5] drm/amdgpu:
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Xiaojian Du
> Sent: Thursday, July 28, 2022 3:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Tim
> ; Du, Xiaojian ; Zhang, Yifan
>
> Subject: [PATCH 1/5] drm/amdgpu: send
This patch will enable support for psp 13.0.4 blcok.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
This patch will add files for PSP 13.0.4.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c | 387 +++
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.h | 30 ++
2 files changed, 417 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
This patch will make SMU send msg to IMU for the front-door loading, it is
required by some ASICs.
Signed-off-by: Yifan Zhang
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8
1 file changed, 8 insertions(+)
diff --git
This patch will add header files for MP 13.0.4.
Signed-off-by: Xiaojian Du
---
.../include/asic_reg/mp/mp_13_0_4_offset.h| 402
.../include/asic_reg/mp/mp_13_0_4_sh_mask.h | 595 ++
2 files changed, 997 insertions(+)
create mode 100644
This patch corrects RLC_RLCS_BOOTLOAD_STATUS offset and index for
GC 11.0.1.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
Hi Andre,
On 7/27/2022 8:56 PM, André Almeida wrote:
Hi Arunpravin,
Às 02:30 de 27/07/22, Arunpravin Paneer Selvam escreveu:
Check the bo->resource value before accessing the resource
mem_type.
v2: Fix commit description unwrapped warning
[ 40.191227][ T184] general protection fault,
-tip
head: df865a97749db8fbb9ec3491f34bf40771ce1f7b
commit: 9c7f5cf088789957dcfb460cca1ab0fb578f2376 [4/8] Merge
remote-tracking branch 'drm-misc/drm-misc-next' into drm-tip
config: alpha-randconfig-r003-20220728
(https://download.01.org/0day-ci/archive/20220728/202207281420.mnf0xrnj-...@intel.com
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