On 9/13/2022 8:18 PM, Alex Deucher wrote:
This mirrors what we do for other asics and this way we are
sure the ih doorbell range is properly initialized.
There is a comment about the way doorbells on gfx9 work that
requires that they are initialized for other IPs before GFX
is initialized. I
Am 13.09.22 um 22:52 schrieb Felix Kuehling:
Am 2022-09-12 um 08:36 schrieb Christian König:
Use DMA_RESV_USAGE_BOOKKEEP for VM page table updates and KFD
preemption fence.
v2: actually update all usages for KFD
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.
Am 14.09.22 um 00:16 schrieb Mukul Joshi:
This patch updates the PTE flags when translate further (TF) is
enabled:
- With translate_further enabled, invalid PTEs can be 0. Reading
consecutive invalid PTEs as 0 is considered a fault. To prevent
this, ensure invalid PTEs have at least 1 bit s
This symbol is not used outside of dcn314_dio_stream_encoder.c, so marks
it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dio_stream_encoder.c:84:6:
warning: no previous prototype for
‘enc314_stream_encoder_dvi_set_stream_attribute’.
Link: https://bugzilla.openanolis.cn/show_bu
These functions are not used outside the file dcn30_resource.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1949:6:
warning: no previous prototype for
‘is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch’.
drivers/gpu/dr
This symbol is not used outside of dcn32_mmhubbub.c, so marks it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mmhubbub.c:103:6: warning:
no previous prototype for ‘mmhubbub32_config_mcif_buf’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2145
Reported-by: Abaci Robot
Sig
These functions are not used outside the file dcn32_dccg.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:257:6: warning: no
previous prototype for ‘dccg32_otg_drop_pixel’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:248:6: w
These three functions are not used outside the function
dcn32_optc.c, so the modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:159:6: warning: no
previous prototype for function 'optc32_phantom_crtc_post_enable'.
drivers/gpu/drm/amd/amdgpu/../display/d
These functions are not used outside the file dcn32_hubbub.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:912:6: warning:
no previous prototype for ‘hubbub32_force_wm_propagate_to_pipes’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dc
Sorry to trouble you, we ran some tests on this patch and want to communicate with you.static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned nom, unsigned den, unsigned post_div,unsigned fb_div_max, unsigned ref_div_ma
This symbol is not used outside of dcn314_optc.c, so marks it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:153:6: warning:
no previous prototype for ‘optc314_phantom_crtc_post_enable’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2147
Reported-by: Abaci Robot
Si
These functions are not used outside the file dcn32_hubbub.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:223:6: warning:
no previous prototype for ‘dccg314_set_valid_pixel_rate’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dc
Use swap() instead of the temp variable to swap values.
Signed-off-by: Yihao Han
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bi
Am 13.09.22 um 11:05 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
The software ring is created to support priority
context while there is only one hardware queue
for gfx.
Every software rings has its fence driver and could
be used as an ordinary ring for the gpu_scheduler.
Multiple softwar
From: Guchun Chen
[ Upstream commit aac4cec1ec45d72bd03eaf3fd772c5a609f5ed26 ]
It's missed in psp fini.
Signed-off-by: Guchun Chen
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +--
1 file changed, 5 ins
Am 13.09.22 um 16:48 schrieb Alex Deucher:
Move common IP init before GMC init so that HDP gets
remapped before GMC init which uses it.
At some point we should improve this so that we have the common and GMC
stuff in the hardware init as first thing without those hacks.
But anyway Acked-by f
Am 13.09.22 um 22:05 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedu
Am 13.09.22 um 22:05 schrieb Philip Yang:
SDMA update page table may be called from unlocked context, this
generate below warning. Use unlocked iterator to handle this case.
WARNING: CPU: 0 PID: 1475 at
drivers/dma-buf/dma-resv.c:483 dma_resv_iter_next
Call Trace:
dma_resv_iter_first+0x43/0xa0
[background]
For a gpu recovery caused by a hang on one ring (e.g. compute),
jobs from another ring (e.g. gfx) may continue signaling during
drm_sched_stop stage. The signal bit will not be cleared.
At the resubmit stage after recovery, the job with hw fence signaled
bit set will call job done dir
[background]
On current sienna cichlid mode2 reset, on the slow job hang cases,
since page table context was reverted to completely stop gpu, it
will generate page fault interrupt.
Since the irq are open during recovery stage, during ih resume step,
if this interrupt was in processing, which incre
Because the value of man->size is changed during suspend/resume process,
use mgr->mm.size instead of man->size here for lpfn checking.
Signed-off-by: Ma Jun
Suggested-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:729:63-68:
WARNING: conversion to bool not needed here
Generated by: scripts/coccinelle/misc/boolconv.cocci
Signed-off-by: Yihao Han
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hi Hans,
On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote:
> Hi All,
>
> Now that all patches have been reviewed/acked here is an immutable
> backlight-detect-refactor
> branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi,
> drm-* and pdx86)
> subsystems.
>
On Wed, Sep 14, 2022 at 3:05 AM Lazar, Lijo wrote:
>
>
>
> On 9/13/2022 8:18 PM, Alex Deucher wrote:
> > This mirrors what we do for other asics and this way we are
> > sure the ih doorbell range is properly initialized.
> >
> > There is a comment about the way doorbells on gfx9 work that
> > requ
Am 14.09.22 um 14:53 schrieb Ma Jun:
Because the value of man->size is changed during suspend/resume process,
use mgr->mm.size instead of man->size here for lpfn checking.
Signed-off-by: Ma Jun
Suggested-by: Christian König
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amd
Applied the series. Thanks!
Alex
On Wed, Sep 14, 2022 at 1:29 AM Jiapeng Chong
wrote:
>
> These three functions are not used outside the function
> dcn32_optc.c, so the modification is defined as static.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:159:6: warning:
> no previ
Applied. Thanks!
On Wed, Sep 14, 2022 at 3:53 AM Yihao Han wrote:
>
> ./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:729:63-68:
> WARNING: conversion to bool not needed here
>
> Generated by: scripts/coccinelle/misc/boolconv.cocci
> Signed-off-by: Yihao Han
> ---
> drivers/gpu/drm/amd/disp
Am 2022-09-13 um 18:16 schrieb Mukul Joshi:
This patch updates the PTE flags when translate further (TF) is
enabled:
- With translate_further enabled, invalid PTEs can be 0. Reading
consecutive invalid PTEs as 0 is considered a fault. To prevent
this, ensure invalid PTEs have at least 1 bit
On 2022-09-13 16:10, Felix Kuehling wrote:
Am 2022-09-13 um 09:19 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and
On 2022-09-14 05:10, Christian König wrote:
Am 13.09.22 um 22:05 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel errors when IGT disables primary planes during the
tests kms_universal_plane::functional_test_pipe/pageflip_test_pipe.
N
It's customary to add a Cc: tag in the commit message on subsequent revisions
of a patch, once a person has reviewed and commented on it--Christian, Andrey,
me,
so that subsequent patches' emails go out to those people automatically via a
CC.
Inlined:
On 2022-09-13 05:05, jiadong@amd.com wr
Hi,
On 9/14/22 12:29, Maxime Ripard wrote:
> Hi Hans,
>
> On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote:
>> Hi All,
>>
>> Now that all patches have been reviewed/acked here is an immutable
>> backlight-detect-refactor
>> branch with 6.0-rc1 + the v5 patch-set, for merging into th
There is a spelling mistake in a pr_debug message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 752
Am 2022-09-14 um 12:08 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and sche
Hi Dave, Daniel,
Fixes for 6.0. A bit bigger than usual, but this is mainly caused by some
regression fixes which took a while to sort out and validate. The rest is
fixes for new IPs added in the 6.0 cycle.
The following changes since commit 2edb79a5fb303dff577d6a0c7d571c3bab1d1455:
Merge ta
On 2022-09-14 10:55, Michel Dänzer wrote:
[ Adding the dri-devel list ]
On 2022-09-14 18:30, Alex Hung wrote:
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel errors w
Hi Maíra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip linus/master
v6.0-rc5 next-20220914]
[cannot apply to drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2177
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2182
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2180
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../amd/display/dc/dcn321/dcn321_resource.c | 26 +--
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2179
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/a
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2181
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2178
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/a
[AMD Official Use Only - General]
Ping.
Hi @Koenig, Christian and @Grodzovsky, Andrey,
We found some reset related issues during stress test on the sequence. Please
help give some comments.
Thanks,
Victor
-Original Message-
From: Victor Zhao
Sent: Wednesday, September 14, 2022 6:
[AMD Official Use Only - General]
>So, between the function names of "amdgpu_ring_get_rptr_from_mux()" and
>"amdgpu_ring_get_wptr_from_mux()",
>they are 96.6(6)% _the_same_ name to a human. How about
>"amdgpu_ring_get_readp_from_mux()" and "amdgpu_ring_get_writep_from_mux()"?
I agree with the s
On 9/14/2022 3:40 PM, Victor Zhao wrote:
[background]
On current sienna cichlid mode2 reset, on the slow job hang cases,
since page table context was reverted to completely stop gpu, it
will generate page fault interrupt.
Since the irq are open during recovery stage, during ih resume step,
if
Am 14.09.22 um 19:45 schrieb Felix Kuehling:
Am 2022-09-14 um 12:08 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and
Am 15.09.22 um 06:02 schrieb Zhao, Victor:
[AMD Official Use Only - General]
Ping.
Hi @Koenig, Christian and @Grodzovsky, Andrey,
We found some reset related issues during stress test on the sequence. Please
help give some comments.
Thanks,
Victor
-Original Message-
From: Vict
[AMD Official Use Only - General]
Hi Lijo,
IH resume was added to resolve an issue found during mode2 bring up on sienna
cichlid:
- close down mode2 reset and do a mode1 reset first
- open mode2 reset and do a mode2 reset. Mode2 reset was found fail in this
case.
Resume IH helps in this case
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer.
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
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