[AMD Official Use Only - General]
Reviewed-by: Evan Quan
> -Original Message-
> From: Li Zhong
> Sent: Thursday, September 22, 2022 12:18 PM
> To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: jiapeng.ch...@linux.alibaba.com; Powell, Darren
> ; Chen, Guchun ;
>
Perhaps you need to update the prefix of patch subject to 'drm/amd/pm: check
return value ...'.
With above addressed, it's: Acked-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Li Zhong
Sent: Thursday, September 22, 2022 9:27 AM
To: dri-de...@lists.freedesktop.org;
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Thursday, September 22, 2022 09:37
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ;
Clements, John ; Yang, Stanley
Subject: RE: [PATCH]
[AMD Official Use Only - General]
Ping ...
-
Best Regards,
Thomas
-Original Message-
From: Chai, Thomas
Sent: Tuesday, September 20, 2022 10:07 AM
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ;
Zhou1, Tao ; Clements, John ; Yang,
Stanley ;
From: Tom Rix
There are several copies of CalculateRemoteSurfaceFlipDelay.
Reduce to one instance.
Signed-off-by: Tom Rix
Reviewed-by: Maíra Canal
---
.../dc/dml/dcn20/display_mode_vba_20.c| 4 +-
.../dc/dml/dcn20/display_mode_vba_20v2.c | 40 +--
From: Wenjing Liu
[why]
vid stream control is double bufferred, if we don't wait for video
stream enable set to 0, we may get temporary image corruption
showing on the stream when setting PIXEL_TO_SYMBOL_FIFO_ENABLE to 0.
Reviewed-by: Ariel Bernstein
Acked-by: Jasdeep Dhillon
Signed-off-by:
From: Tom Rix
There are several copies of CalculateTwait.
Reduce to one instance and change local variable name to match common usage.
Signed-off-by: Tom Rix
Reviewed-by: Maíra Canal
---
.../dc/dml/dcn20/display_mode_vba_20.c| 16 +++---
From: Aric Cyr
Revert "dc: skip audio setup when audio stream is enabled"
This reverts commit c83f2553273a796b62411e73fb4fe19ec521f8a9
[why]
We have minimal pipe split transition method to avoid pipe
allocation outage.However, this method will invoke audio setup
which cause audio output stuck
From: Tom Rix
Mimimize the function signature by passing a pointer and an index instead
of passing several elements of the pointer.
The dml2x,dml3x families uses the same algorithm. Remove the duplicates.
Use dml20_ and dml30_ prefix to distinguish the two variants.
Signed-off-by: Tom Rix
From: Brandon Syu
[Description]
- Have option to exit idle opt on cursor updates
for debug and optimizations purposes
Reviewed-by: Aric Cyr
Acked-by: Jasdeep Dhillon
Signed-off-by: Brandon Syu
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 3 ++-
From: Aric Cyr
This version brings along following fixes:
- LTTPR mode can be be dynamically changed
- fixes divide by zero error
- features able to use same interface to update cursor info
- fixes for llvm compilation issues
- Fixes DIO FIFO underflow and other FIFO errors
From: Taimur Hassan
[Why]
Programming pixel rate divider when FIFO is enabled can cause FIFO error.
[How]
Skip divider programming when divider values are the same to prevent FIFO
error.
Reviewed-by: Alvin Lee
Acked-by: Jasdeep Dhillon
Signed-off-by: Taimur Hassan
---
From: Alvin Lee
[Description]
- Don't use MALL buffering of any kind when the
surface is TMZ
- Workaround for a HW bug
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++--
From: Samson Tam
[Why]
For individual feature testing, PMFW may not report all clock
values back. Driver will default them to 0 but this will
cause the BB table to be skipped and default to one state
with max clocks.
[How]
Add helper function to scan through initial clock values and
populate
From: Max Tseng
Dc: cursor info update: phase 1:
[Why]
Different feature might need to update cursor info, but
With different approaches.
To unify this diversity problem, all features should use
The same interface to update cursor.
Reviewed-by: Reza Amini
Acked-by: Jasdeep Dhillon
From: Alvin Lee
[Description]
Update MALL SS NumWays calculation according
to programming guide.
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 206
From: Wenjing Liu
[why]
There is a coding error for a missing null check for stream pointer when
iterating through
pipe_ctx.
Reviewed-by: Martin Leung
Acked-by: Jasdeep Dhillon
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
1 file changed, 1
From: Nathan Chancellor
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
dml314_ModeSupportAndSystemConfigurationFull() uses by 240 bytes with
LLVM 16 (2216 ->
From: Nicholas Kazlauskas
[Why]
We rely on DMCUB to do this when disabling the link but it should
actually come before we disable the DP VID stream.
If we don't then the FIFO can end up with underflow that persists
the next time it's enabled.
[How]
Add a DCN314 specific blank sequence that
From: Charlene Liu
[why]
adding debug keys used for compliance test.
Reviewed-by: Chris Park
Acked-by: Jasdeep Dhillon
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/bios/bios_parser2.c| 21 ---
drivers/gpu/drm/amd/display/dc/dc.h | 3 +++
2 files
From: Taimur Hassan
[Why & How]
Some FIFO errors still occur due to reading wrong pixel rate divider.
Fix typo to prevent FIFO error.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Jasdeep Dhillon
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c | 2 +-
1
From: Eric Bernstein
Remove assert that will hit during odm transition case, since this is a
valid case.
Signed-off-by: Eric Bernstein
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff
From: Ian Chen
Reviewed-by: Josip Pavic
Acked-by: Jasdeep Dhillon
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index
From: Alvin Lee
[Description]
Accidentally added when should have subtracted
in calculation
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Nathan Chancellor
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
dml314_ModeSupportAndSystemConfigurationFull() uses by 112 bytes with
LLVM 16 (1976 ->
From: Ilya Bakoulin
[Why]
Partially valid EDIDs on MST sinks are treated the same way as broken
EDIDs or read failures and result in a fallback EDID being used instead.
[How]
If edid_status is EDID_PARTIAL_VALID, prefer to use the valid EDID
blocks instead of using a fallback EDID.
From: Alvin Lee
[Description]
Update to new SR latencies for DCN32
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Aurabindo Pillai
[Why]
Phantom pipes are not programmed fully to hardware and hence we should
not expect a flip completion.
Reviewed-by: Alvin Lee
Acked-by: Jasdeep Dhillon
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1
From: Nicholas Kazlauskas
[Why]
Avoids a race condition where DIO FIFO can underflow due to no incoming
data available.
[How]
Shift the FIFO enable below stream enable.
Make sure fullness level is written before the DIO reset takes place
and that we're not doing it twice.
Reviewed-by: Syed
From: Aurabindo Pillai
[Why]
Incorrect variable was being checked for zero condition.
Reviewed-by: Alvin Lee
Acked-by: Jasdeep Dhillon
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Nicholas Kazlauskas
[Why]
The DIO FIFO will underflow if we turn off the OTG before we turn
off the FIFO.
Since this happens as part of the OTG workaround and we don't reset
the FIFO afterwards we see the error persist.
[How]
Add disable FIFO before the disable CRTC and enable FIFO after
From: Dillon Varone
[Why]
Several transitions were fixed that will allow Dynamic ODM and MPO
transitions to be supported on DCN32.
1) Due to resource limitations, in certain scenarios that require an MPO
plane to be split, the features cannot be combined with the current
policy. This is due to
From: Taimur Hassan
[Why]
Programming pixel rate divider when FIFO is enabled can cause FIFO error.
[How]
Skip divider programming when divider values are the same to prevent FIFO
error.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Jasdeep Dhillon
Signed-off-by: Taimur Hassan
---
This DC patchset brings improvements in multiple areas. In summary, we have:
- LTTPR mode can be be dynamically changed
- features able to use same interface to update cursor info
- fixes for llvm compilation issues
- Fixes DIO FIFO underflow and other FIFO errors
- Partially
From: Aric Cyr
[why]
Only a single VLINE interrupt is available so interface should not
expose the second one which is used by DMU firmware.
[how]
Remove references to periodic_interrupt1 and VLINE1 from DC interfaces.
Reviewed-by: Jaehyun Chung
Acked-by: Jasdeep Dhillon
Signed-off-by: Aric
From: Michael Strauss
[WHY]
Previously, LTTPR mode was decided during detection which makes
link training inflexible as mode can't be dynamically changed.
[HOW]
-Remove lttpr_mode from link struct, and move to link training settings
-Defer choosing LTTPR mode until link training
Other DP
From: Aurabindo Pillai
[Why]
Phantom pipes are not programmed fully to hardware and hence we should
not expect a flip completion.
Reviewed-by: Alvin Lee
Acked-by: Jasdeep Dhillon
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1
From: Taimur Hassan
[Why]
Programming pixel rate divider when FIFO is enabled can cause FIFO error.
[How]
Skip divider programming when divider values are the same to prevent FIFO
error.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Jasdeep Dhillon
Signed-off-by: Taimur Hassan
---
From: Nicholas Kazlauskas
[Why]
Avoids a race condition where DIO FIFO can underflow due to no incoming
data available.
[How]
Shift the FIFO enable below stream enable.
Make sure fullness level is written before the DIO reset takes place
and that we're not doing it twice.
Reviewed-by: Syed
From: Nicholas Kazlauskas
[Why]
The DIO FIFO will underflow if we turn off the OTG before we turn
off the FIFO.
Since this happens as part of the OTG workaround and we don't reset
the FIFO afterwards we see the error persist.
[How]
Add disable FIFO before the disable CRTC and enable FIFO after
From: Ilya Bakoulin
[Why]
Partially valid EDIDs on MST sinks are treated the same way as broken
EDIDs or read failures and result in a fallback EDID being used instead.
[How]
If edid_status is EDID_PARTIAL_VALID, prefer to use the valid EDID
blocks instead of using a fallback EDID.
From: Nicholas Kazlauskas
[Why]
We rely on DMCUB to do this when disabling the link but it should
actually come before we disable the DP VID stream.
If we don't then the FIFO can end up with underflow that persists
the next time it's enabled.
[How]
Add a DCN314 specific blank sequence that
From: Aric Cyr
[why]
Only a single VLINE interrupt is available so interface should not
expose the second one which is used by DMU firmware.
[how]
Remove references to periodic_interrupt1 and VLINE1 from DC interfaces.
Reviewed-by: Jaehyun Chung
Acked-by: Jasdeep Dhillon
Signed-off-by: Aric
From: Alvin Lee
[Description]
Update to new SR latencies for DCN32
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Michael Strauss
[WHY]
Previously, LTTPR mode was decided during detection which makes
link training inflexible as mode can't be dynamically changed.
[HOW]
-Remove lttpr_mode from link struct, and move to link training settings
-Defer choosing LTTPR mode until link training
Other DP
From: Dillon Varone
[Why]
Several transitions were fixed that will allow Dynamic ODM and MPO
transitions to be supported on DCN32.
1) Due to resource limitations, in certain scenarios that require an MPO
plane to be split, the features cannot be combined with the current
policy. This is due to
Subject: DC Patches MONTH DAY, YEAR
This DC patchset brings improvements in multiple areas. In summary, we have:
- LTTPR mode can be be dynamically changed
- features able to use same interface to update cursor info
- fixes for llvm compilation issues
- Fixes DIO FIFO
This was fixed in initialize_cpsch before, but not in initialize_nocpsch.
Factor sdma bitmap initialization into a helper function to apply the
correct implementation in both cases without duplicating it.
Reported-by: Ellis Michael
Signed-off-by: Felix Kuehling
---
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 483fed3b5dc8ce3644c83d24240cf5756fb0993e Add linux-next specific
files for 20220921
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209042337.fqi69rlv-...@intel.com
https
Hi Dave, Daniel,
Fixes for 6.0. Mainly fixes for new IPs. The big change here is the DML
clean up from Nathan to fix the Clang stack usage warnings on the DCN 3.1.4
code which was recently enabled.
The following changes since commit a8671493d2074950553da3cf07d1be43185ef6c6:
drm/amdgpu: make
Thank you for reporting this problem. This only affects a small number
of GPUs that don't use the HW scheduler in KFD. We fixed the same issue
in the HWS code path over a year ago but apparently didn't think to
apply the same fix for the non-HWS code path. This is that patch for
reference.
manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
which causes drm_crtc_vblank_get in vrr_transition to fail, and later
when drm_crtc_vblank_put is called the refcount on vblank will be messed
up. Therefore move the call to after manage_dm_interrupts.
Bug:
On Tue, Aug 23, 2022 at 8:25 PM Yunxiang Li wrote:
>
> manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
> which causes drm_crtc_vblank_get in vrr_transition to fail, and later
> when drm_crtc_vblank_put is called the refcount on vblank will be messed
> up. Therefore move
On Wed, Sep 21, 2022 at 2:47 PM Graham Sider wrote:
>
> Set remaining compute_static_thread_mgmt_se* accordingly.
>
> Signed-off-by: Graham Sider
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
Set remaining compute_static_thread_mgmt_se* accordingly.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
When many entities competing for same run queue on
the same scheduler When many entities have unacceptably long wait
time for some jobs waiting stuck in the run queue before being picked
up are observed (seen using GPUVis).
The issue is due to the Round Robin policy used by schedulers
to pick up
From: Yao Wang1
[ Upstream commit 3601d620f22e37740cf73f8278eabf9f2aa19eb7 ]
[Why]
For HDR mode, we get total 512 tf_point and after switching to SDR mode
we actually get 400 tf_point and the rest of points(401~512) still use
dirty value from HDR mode. We should limit the rest of the points to
From: Nathan Chancellor
[ Upstream commit 41012d715d5d7b9751ae84b8fb255e404ac9c5d0 ]
This function consumes a lot of stack space and it blows up the size of
dml30_ModeSupportAndSystemConfigurationFull() with clang:
From: Hamza Mahfooz
[ Upstream commit 66f99628eb24409cb8feb5061f78283c8b65f820 ]
Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
struct.
Signed-off-by: Hamza Mahfooz
Acked-by: Alex Deucher
Signed-off-by:
From: Yao Wang1
[ Upstream commit 3601d620f22e37740cf73f8278eabf9f2aa19eb7 ]
[Why]
For HDR mode, we get total 512 tf_point and after switching to SDR mode
we actually get 400 tf_point and the rest of points(401~512) still use
dirty value from HDR mode. We should limit the rest of the points to
From: Yao Wang1
[ Upstream commit 3601d620f22e37740cf73f8278eabf9f2aa19eb7 ]
[Why]
For HDR mode, we get total 512 tf_point and after switching to SDR mode
we actually get 400 tf_point and the rest of points(401~512) still use
dirty value from HDR mode. We should limit the rest of the points to
From: Nathan Chancellor
[ Upstream commit 21485d3da659b66c37d99071623af83ee1c6733d ]
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
From: Hamza Mahfooz
[ Upstream commit 66f99628eb24409cb8feb5061f78283c8b65f820 ]
Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
struct.
Signed-off-by: Hamza Mahfooz
Acked-by: Alex Deucher
Signed-off-by:
From: Yao Wang1
[ Upstream commit 3601d620f22e37740cf73f8278eabf9f2aa19eb7 ]
[Why]
For HDR mode, we get total 512 tf_point and after switching to SDR mode
we actually get 400 tf_point and the rest of points(401~512) still use
dirty value from HDR mode. We should limit the rest of the points to
From: Nathan Chancellor
[ Upstream commit 41012d715d5d7b9751ae84b8fb255e404ac9c5d0 ]
This function consumes a lot of stack space and it blows up the size of
dml30_ModeSupportAndSystemConfigurationFull() with clang:
From: Nathan Chancellor
[ Upstream commit 37934d4118e22bceb80141804391975078f31734 ]
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
From: Nathan Chancellor
[ Upstream commit 37934d4118e22bceb80141804391975078f31734 ]
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
From: Hamza Mahfooz
[ Upstream commit 66f99628eb24409cb8feb5061f78283c8b65f820 ]
Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
struct.
Signed-off-by: Hamza Mahfooz
Acked-by: Alex Deucher
Signed-off-by:
From: Guchun Chen
[ Upstream commit 7c6fb61a400bf3218c6504cb2d48858f98822c9d ]
To avoid hardware intermittent failures.
Signed-off-by: Guchun Chen
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 11
From: Nathan Chancellor
[ Upstream commit 41012d715d5d7b9751ae84b8fb255e404ac9c5d0 ]
This function consumes a lot of stack space and it blows up the size of
dml30_ModeSupportAndSystemConfigurationFull() with clang:
From: Nathan Chancellor
[ Upstream commit 21485d3da659b66c37d99071623af83ee1c6733d ]
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
From: Yao Wang1
[ Upstream commit 3601d620f22e37740cf73f8278eabf9f2aa19eb7 ]
[Why]
For HDR mode, we get total 512 tf_point and after switching to SDR mode
we actually get 400 tf_point and the rest of points(401~512) still use
dirty value from HDR mode. We should limit the rest of the points to
From: Candice Li
[ Upstream commit 86875d558b91cb46f43be112799c06ecce60ec1e ]
No need to reset error status since only umc ras supported on psp v13_0_0.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Alex Deucher
[ Upstream commit 8c5708d3da37b8c7c3c22c7e945b9a76a7c9539b ]
Was missing before and would have resulted in a write to
a non-existant register. Normally APUs don't use HDP, but
other asics could use this code and APUs do use the HDP
when used in passthrough.
Reviewed-by: Lijo
From: Yang Wang
[ Upstream commit 36de13fdb04abef3ee03ade5129ab146de63983b ]
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
v2:
add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size
Signed-off-by: Yang Wang
From: Hamza Mahfooz
[ Upstream commit 66f99628eb24409cb8feb5061f78283c8b65f820 ]
Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
struct.
Signed-off-by: Hamza Mahfooz
Acked-by: Alex Deucher
Signed-off-by:
From: Guchun Chen
[ Upstream commit 7c6fb61a400bf3218c6504cb2d48858f98822c9d ]
To avoid hardware intermittent failures.
Signed-off-by: Guchun Chen
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 11
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, September 21, 2022 8:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Koenig, Christian ;
Chen, Guchun ; Bai, Zoy (zoybai)
Subject: [PATCH 2/2]
This patch is: Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Wednesday, September 21, 2022 8:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Bai, Zoy (zoybai)
; Koenig, Christian ; Chen, Guchun
; Zhang,
Am 21.09.22 um 11:41 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
The current position calulated in gfx_v9_0_ring_emit_patch_cond_exec
underflows when the wptr is divisible by ring->buf_mask + 1.
Good catch, looks like a completely independent bug fix to me. So please
push separately.
Am 21.09.22 um 11:41 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with
On 9/20/22 17:13, Sumit Semwal wrote:
> Hi Dmitry,
>
> Thanks very much for the series.
>
> On Wed, 14 Sept 2022 at 00:59, Dmitry Osipenko
> wrote:
>>
>> Move dma_buf_vmap/vunmap_unlocked() functions to the dynamic locking
>> specification by asserting that the reservation lock is held.
>
Am 21.09.22 um 11:41 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify
Am 21.09.22 um 11:41 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring
Am 21.09.22 um 14:30 schrieb Lijo Lazar:
Disable verbose while getting p2p distance. With verbose, it shows
warning if ACS redirect is set between the devices. Adds noise
to dmesg logs when a few GPU devices are on the same platform.
Example log:
amdgpu :34:00.0: ACS redirect is set
Am 21.09.22 um 11:41 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple
Use the simpified API that calculates distance between two devices.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
Disable verbose while getting p2p distance. With verbose, it shows
warning if ACS redirect is set between the devices. Adds noise
to dmesg logs when a few GPU devices are on the same platform.
Example log:
amdgpu :34:00.0: ACS redirect is set between the client and provider
(:31:00.0)
On 9/21/2022 10:26 AM, Evan Quan wrote:
Make sure gfxoff is disabled before gfx register accessing.
Signed-off-by: Evan Quan
Series is -
Reviewed-by: Lijo Lazar
Thanks,
Lijo
Change-Id: Ia032869080f51cdefc6e6bad4f04405193ab0fec
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
From: "Jiadong.Zhu"
The current position calulated in gfx_v9_0_ring_emit_patch_cond_exec
underflows when the wptr is divisible by ring->buf_mask + 1.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue, and pops
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
Signed-off-by: Jiadong.Zhu
---
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring
Inlined:
On 2022-09-20 15:16, Andrey Grodzovsky wrote:
>
> On 2022-09-19 23:11, Luben Tuikov wrote:
>> Please run this patch through checkpatch.pl, as it shows
>> 12 warnings with it. Use these command line options:
>> "--strict --show-types".
>>
>> Inlined:
>>
>> On 2022-09-13 16:40, Andrey
Reporting an undefined behavior issue in the amdgpu driver in the
linux kernel I ran into recently. It appears during boot, fairly early
in the process.
[drm] UVD initialized successfully.
[drm] VCE initialized successfully.
kfd kfd: amdgpu: Allocated 3969056 bytes on gart
96 matches
Mail list logo
