On 10/6/2022 10:51 PM, Leo Li wrote:
On 2022-10-06 03:46, S, Shirish wrote:
On 10/6/2022 4:33 AM, Leo Li wrote:
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06
[Why]
If psr_feature_enable is set to true by default, it continues to be enabled
for non capable links.
[How]
explicitly disable the feature on links that are not capable of the same.
Signed-off-by: Shirish S
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 ++--
1 file change
From: Rodrigo Siqueira
When using a device based on DCN32/321,
we have an issue where a second
4k@60Hz display does not light up,
and the system becomes unresponsive
for a few minutes. In the debug process,
it was possible to see a hang
in the function dcn20_post_unlock_program_front_end
in this
From: Alvin Lee
Watermark calculation was incorrect
due to missing brackets.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Rodrigo Siqueira
The OTG_MASTER_UPDATE_LOCK_SEL is used for
GSL and OTGs in the same group for selecting
the OTG_MASTER_UPDATE_LOCK from the same OTG. At
some point, it a check was added to see if
OTG is running or not, which is not necessary,
and for this reason, this commit dropped that c
From: Alvin Lee
pipe_ctx[i] exists even if the pipe is not
in use. If the pipe is not in use it will
always have a null stream, so don't return
false in this case.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_re
From: Rodrigo Siqueira
Some unused macros might mislead developers
during the debug, which can be removed without
any issue. This commit drops some unused references
to SE_COMMON_MASK_SH_LIST_DCN32.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dcn32/dcn32_dio
From: Aric Cyr
DC version 3.2.207 brings along the following:
- PMFW z-state interface update
- Cursor update refactor
- Fixes to DSC validation, DCFCLK during Freesync, etc.
- Code cleanup
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file
From: Rodrigo Siqueira
In multiple parts of the DCN code, we
write directly to the OTG_V_TOTAL_* registers
in some OPTC functions. Let's avoid it by using
the set_vtotal_min_max.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 18 ++
From: Max Tseng
[Why]
Since different features would need to update cursor registers,
However, they would use different approaches.
To unify varied methods, this refactor is implemented the same
update cursor info method for current varied features.
Reviewed-by: Anthony Koo
Reviewed-by: Jun Le
From: Rodrigo Siqueira
The struct timing_generator_funcs provides a hook
for setting up the maximum possible vertical
dimension of display for OTG, as the panel
supports. DCN10 has a standard function named
optc1_set_vtotal_min_max which all ASICs can use
to set the aforementioned hook. Since we
From: Fangzhi Zuo
Before enabling new crtc, stream_count in dc_state does not sync with
that in drm_atomic_state. Validating dsc in such case would leave
newly added stream not jointly participating in dsc optimization with
existing streams, but simply using default initialized vcpi all the time
From: Dillon Varone
[Why & How]
FCLK pstate allow message should not be
dependent on local "update_fclk".
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+),
From: Meenakshikumar Somasundaram
[Why]
Dpia hpd interrupt processing is disabled when entering S4/S0i3 and would
be reenabled after detection completes during resuming. Because, keeping
hpd interrupts enabled during detection leads to multiple detections for
the same hpd transition. There is a S
From: Aurabindo Pillai
[Why&How]
Doing timing sync seqence for phantom pipes
will not go through since they are not fully
programmed like normal pipes. Skip the sequence
on such pipes
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
.../amd/display/dc/dcn10/
From: Dmytro Laktyushkin
[Why & How]
Prevents certain configs blocking s0i3
when streams aren't completely removed
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 9 ++---
1 file changed, 6 ins
From: Dillon Varone
[Why & How]
Acquire FCLK DPM levels to properly
construct DML clock limits. Further add
new logic to keep number of indices for
each clock in clk_mgr.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.
From: Jun Lei
[Why & How]
Add a helper to map ODM/MPC/Multi-Plane
resources from DC
Reviewed-by: Nevenko Stupar
Reviewed-by: Chaitanya Dhere
Acked-by: Qingqing Zhuo
Signed-off-by: Jun Lei
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 49 ++-
drivers/gpu/drm/amd/display
From: Vladimir Stempen
[Why]
Diagnostics reports exceptions generated when
timeout waiting for DISPCLK frequency divider
change expires when testing ODM4to1.
Diagnostics reports exceptions generated when
timeout waiting for OTG busy status expires
when disabling OTG during ODM4to1 test.
[How]
In
From: Dillon Varone
[Why?]
Currently phy_pix_clk is used to program DTO's which is incorrect.
[How?]
Use the timing pixel clock to program DTO's correctly.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions
From: Martin Leung
[Why & How]
bug was caused when moving variable from stack to
heap because it was reusable and garbage was left
over, so we need to zero mem
Fixes: 593eef8c1a5e ("drm/amd/display: reduce stack size in dcn32 dml (v2)")
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Sig
From: Vladimir Stempen
[Why]
Bandwidth validation is using Freesync parameters
from previous Freesync state.
Bandwidth validation ignores DCFCLK calculated
after Freesync parameters are configured
[How]
Set Freesync bandwidth parameters to its default
state before running bandwidth validation.
T
From: Dillon Varone
This reverts commit 0a1b86a611f14df7a490b827556a4b8c2e31c050.
[Why & How]
The reverted commit creates memory leak and causes issue
upon driver install.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/core/
This DC patch-set brings improvements in multiple areas. In summary, we
highlight:
- PMFW z-state interface update
- Cursor update refactor
- Fixes to DSC validation, DCFCLK during Freesync, etc.
- Code cleanup
Cc: Daniel Wheeler
---
Alvin Lee (2):
drm/amd/display: Fix watermark cal
From: Nicholas Kazlauskas
[Why]
Request from PMFW to change the messaging format to specify whether we
support z-state via individual bits.
[How]
Update the args we pass in the support message.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
.../drm/
On Thu, Oct 6, 2022 at 9:37 PM Kees Cook wrote:
>
> On Thu, Oct 06, 2022 at 12:39:40PM -0700, Linus Torvalds wrote:
> > What confuses me is that error message ("array subscript [0, 0] is
> > outside array bounds of 'struct dc_writeback_info[1]') which seems to
> > be aware that the value is actual
On Thu, Oct 06, 2022 at 12:39:40PM -0700, Linus Torvalds wrote:
> What confuses me is that error message ("array subscript [0, 0] is
> outside array bounds of 'struct dc_writeback_info[1]') which seems to
> be aware that the value is actually 0.
I've seen bugs in the tracker where the reporting is
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 7da9fed0474b4cd46055dd92d55c42faf32c19ac Add linux-next specific
files for 20221006
Error/Warning reports:
https://lore.kernel.org/linux-doc/202210070057.npbamyxb-...@intel.com
https
On Thu, Oct 6, 2022 at 8:39 PM Linus Torvalds
wrote:
>
> On Thu, Oct 6, 2022 at 1:51 AM Sudip Mukherjee (Codethink)
> wrote:
> >
> > This is only seen with gcc-11, gcc-12 builds are ok.
>
> Hmm. This seems to be some odd gcc issue.
>
>
> The fix *MAY* be to just add a '&& i < MAX_DWB_PIPES' to
On Thu, Oct 6, 2022 at 2:11 PM Zhang, Bokun wrote:
>
> [AMD Official Use Only - General]
>
> Hey guys,
> Please help review this patch for the suspend and resume issue.
> I have tested it with multi-VF environment, I think it is ok.
Seems a little hacky, but I think that's the least intru
Hey Linus,
On 2022-10-06 15:39, Linus Torvalds wrote:
On Thu, Oct 6, 2022 at 1:51 AM Sudip Mukherjee (Codethink)
wrote:
This is only seen with gcc-11, gcc-12 builds are ok.
Hmm. This seems to be some odd gcc issue.
I *think* that what is going on is that the test
j = 0 ; j < MAX_
On Thu, Oct 6, 2022 at 1:51 AM Sudip Mukherjee (Codethink)
wrote:
>
> This is only seen with gcc-11, gcc-12 builds are ok.
Hmm. This seems to be some odd gcc issue.
I *think* that what is going on is that the test
j = 0 ; j < MAX_DWB_PIPES
makes gcc decide that "hey, j is in the range
[AMD Official Use Only - General]
Hey guys,
Please help review this patch for the suspend and resume issue.
I have tested it with multi-VF environment, I think it is ok.
Thanks!
-Original Message-
From: Bokun Zhang
Sent: Thursday, October 6, 2022 2:09 PM
To: amd-gfx@lists.freed
- Under SRIOV, SDMA engine is shared between VFs. Therefore,
we will not stop SDMA during hw_fini. This is not an issue
with normal dirver loading and unloading.
- However, when we put the SDMA engine to suspend state and resume
it, the issue starts to show up. Something could attempt to use
On Wed, Oct 05, 2022 at 11:46:15PM -0700, Guenter Roeck wrote:
> On Tue, Sep 27, 2022 at 03:12:00PM -0400, Hamza Mahfooz wrote:
> > Address the following error:
> > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function
> > ‘dc_stream_remove_writeback’:
> > drivers/gpu/drm/amd/amdg
On 2022-10-06 03:46, S, Shirish wrote:
On 10/6/2022 4:33 AM, Leo Li wrote:
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr featur
Fixes a warning in dc.c.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 40a34b600c8e..96bba1c8246f 100644
Hi All,
The latest mainline kernel branch fails to build allmodconfig for every
ARCH with gcc-11 with the error:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function
'dc_stream_remove_writeback':
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:83: error: array
su
On Tue, Sep 27, 2022 at 03:12:00PM -0400, Hamza Mahfooz wrote:
> Address the following error:
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function
> ‘dc_stream_remove_writeback’:
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:55: error:
> array subscript [0, 0
On Thu, Oct 06, 2022 at 04:58:28AM +0800, kernel test robot wrote:
> tree/branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> branch HEAD: 67ae4f7434cee86ee318d46fb10b8a9840ad2e81 Add linux-next
> specific files for 20221005
>
> Error/Warning reports:
>
> htt
On 10/6/2022 4:33 AM, Leo Li wrote:
On 2022-10-03 11:26, S, Shirish wrote:
Ping!
Regards,
Shirish S
On 9/30/2022 7:17 PM, S, Shirish wrote:
On 9/30/2022 6:59 PM, Harry Wentland wrote:
+Leo
On 9/30/22 06:27, Shirish S wrote:
[Why]
psr feature continues to be enabled for non capable li
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