When the CPU SMT changes on the fly, send the message to pmfw
to notify the SMT status changed.
Changes in v2:
1/. Embed the smt notifer callback into "struct smu_context" structure.
2/. Correct the PPSMC_Message_Count value.
3./ Improve several code styles and others.
Wenyou Yang (3):
cpu/smt:
Add the notifier chain to notify the cpu SMT status changes
Signed-off-by: Wenyou Yang
---
include/linux/cpu.h | 5 +
kernel/cpu.c| 10 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 314802f98b9d..9a842317fe2
When the CPU SMT status is changed in the fly, sent the SMT enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7
2 files cha
Add the support to send PPSMC_MSG_SetCClkSMTEnable(0x58) message
to pmfw for vangogh.
Signed-off-by: Wenyou Yang
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_pp
On 3/27/2023 12:54 PM, Wenyou Yang wrote:
When the CPU SMT status is changed in the fly, sent the SMT enable
message to pmfw to notify it that the SMT status changed.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 +++
drivers/gpu/drm/amd
[Public]
Hi all,
This week this patchset was tested on the following systems:
Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
Lenovo Thinkpad T13s Gen4 with AMD Ryzen 5 6600U
Reference AMD RX6800
These systems were tested on the following display types:
eDP, (1080p 60hz [5650U]) (1920x12
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_enc_cfg.c:625:6: error:
variable 'matching_stream_ptrs' set but not used
[-Werror,-Wunused-but-set-variable]
int matching_stream_ptrs = 0;
^
This variable is not used so remove it.
Signed-off-by: To
On Wed 2023-03-22 10:05:13, Rodrigo Siqueira wrote:
> Cc: Anthony Koo
> Cc: Iswara Negulendran
> Cc: Felipe Clark
> Cc: Harry Wentland
> Signed-off-by: Rodrigo Siqueira
Some changelog would be useful.
> +++ b/include/drm/display/drm_dp.h
> @@ -977,6 +977,8 @@
> # define DP_EDP_BACKLIGHT_FR
On 26/03/2023 23:49, Yang, WenYou wrote:
> Hi Guilherme,
>
> Thank you for your attention on the patch set.
> The purpose of the patch set is to improve the performance when playing the
> game.
>
> Best Regards,
> Wenyou
Hi Wenyou, thank you for the clarification and for the interesting patch
s
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 011eb7443621f49ca1e8cdf9c74c215f25019118 Add linux-next specific
files for 20230327
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303082135.njdx1bij-...@intel.com
https
Thanks for the fix. I'll push this via amd-staging-drm-next.
Reviewed-by: Luben Tuikov
Regards,
Luben
On 2023-03-25 09:15, Caio Novais wrote:
> Compiling AMD GPU drivers displays two warnings:
>
> drivers/gpu/drm/scheduler/sched_main.c:738: warning: Function parameter or
> member 'file' not d
[Why]
After gpu-reset, sometimes the driver would fail to enable vblank irq,
causing flip_done timed out and the desktop freezed.
During gpu-reset, we will disable and enable vblank irq in dm_suspend()
and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we
will check irqs' refcount
Pushed through drm-misc-next.
Regards,
Luben
On 2023-03-27 11:02, Luben Tuikov wrote:
> Thanks for the fix. I'll push this via amd-staging-drm-next.
>
> Reviewed-by: Luben Tuikov
>
> Regards,
> Luben
>
> On 2023-03-25 09:15, Caio Novais wrote:
>> Compiling AMD GPU drivers displays two warning
Commit 075e2099c32c ("drm/amd/display: Fix race condition in DPIA AUX
transfer") was backported to stable, which I noticed because of git
saying
linux-6.1/.git/rebase-apply/patch:37154: space before tab in indent.
while applying patch-6.1.21. While fixing the code location that issued
tha
Global variables do not need to be initialized to 0 and checkpatch
flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:
ERROR: do not initialise globals to 0
+int amdgpu_no_queue_eviction_on_vm_fault = 0;
Fix this checkpatch error.
Cc: Christian König
Cc: Alex Deucher
Cc: Mario Limonci
On 3/27/23 13:19, Srinivasan Shanmugam wrote:
Global variables do not need to be initialized to 0 and checkpatch
flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:
ERROR: do not initialise globals to 0
+int amdgpu_no_queue_eviction_on_vm_fault = 0;
Fix this checkpatch error.
Cc: Chri
[AMD Official Use Only - General]
Thanks a lot! Hamza Mahfooz for reviewing!
Best Wishes,
Srini
-Original Message-
From: Mahfooz, Hamza
Sent: Monday, March 27, 2023 11:00 PM
To: SHANMUGAM, SRINIVASAN ; Koenig, Christian
; Deucher, Alexander ;
Limonciello, Mario
Cc: amd-gfx@lists.fre
On 3/27/23 12:07, Uwe Kleine-König wrote:
Commit 075e2099c32c ("drm/amd/display: Fix race condition in DPIA AUX
transfer") was backported to stable, which I noticed because of git
saying
linux-6.1/.git/rebase-apply/patch:37154: space before tab in indent.
while applying patch-6.1.21. Wh
Global variables do not need to be initialized to 0 or NULL and checkpatch
flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:
ERROR: do not initialise globals to NULL
+char *amdgpu_disable_cu = NULL;
+char *amdgpu_virtual_display = NULL;
Fix this checkpatch error.
Cc: Christian König
On Mon, Mar 27, 2023 at 2:11 PM Srinivasan Shanmugam
wrote:
>
> Global variables do not need to be initialized to 0 or NULL and checkpatch
> flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:
>
> ERROR: do not initialise globals to NULL
> +char *amdgpu_disable_cu = NULL;
> +char *amdgpu_
The ROCm debugger will attach to a process to debug by PTRACE and will
expect the KFD to prepare a process for the target PID, whether the
target PID has opened the KFD device or not.
This patch is to explicity handle this requirement. Further HW mode
setting and runtime coordination requirements
Introduce the require KGD debug calls that will execute hardware debug
mode setting.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
.../gpu/drm/amd/include/kgd_kfd_interface.h | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd
Introduce the GPU debug operations interface.
For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD GPU
instruction set, provide the necessary interface to allow the debugger
to HW debug-mode set and query exceptions per HSA queue, process or
device.
The runtime_enable interface co
GFX9.4.2 now supports per-VMID debug mode controls registers
(SPI_GDBG_PER_VMID_CNTL).
Because the KFD lets the HWS handle PASID-VMID mapping, the KFD will
forward all debug mode setting register writes to the HWS scheduler
using a new MAP_PROCESS API, so instead of writing to registers, return
th
Similar to GFX9 debug devices, set the hardware debug mode by draining
the SPI appropriately prior the mode setting request.
Because GFX10 has waves allocated by the work group boundary and each
SE's SPI instances do not communicate, the SPI drain time is much longer.
This long drain time will be
Add missing debug trap registers references and initialize all debug
registers on boot by clearing the hardware exception overrides and the
wave allocation ID index.
The debugger requires that TTMPs 6 & 7 save the dispatch ID to map
waves onto dispatch during compute context inspection.
In order t
The HWS schedule allows a grace period for wave completion prior to
preemption for better performance by avoiding CWSR on waves that can
potentially complete quickly. The debugger, on the other hand, will
want to inspect wave status immediately after it actively triggers
preemption (a suspend funct
Expose debug capabilities in the KFD topology node's HSA capabilities and
debug properties flags.
Ensure correct capabilities are exposed based on firmware support.
Flag definitions can be referenced in uapi/linux/kfd_sysfs.h.
v2: v1 was reviewed but re-requesting review for the following.
- rem
Implement the per-device calls to enable or disable HW debug mode for
GFX9 prior to GFX9.4.1.
GFX9.4.1 and onward will require their own enable/disable sequence as
follow on patches.
When hardware debug mode setting is requested, waves will inherit
these settings in the Shader Processor Input's (
Exception events can be generated from interrupts or queue activitity.
The raise event function will save exception status of a queue, device
or process then notify the debugger of the status change by writing to
a debugger polled file descriptor that the debugger provides during
debug attach.
Fo
The debugger for GFX9.4.1 uses kfd_suspend_all_processes to pause the
compute pipe line so it can safely toggle the SQ's implicit wait on
barrier setting during debug attach/detach to work around the wave
exception s_barrier race condition.
For mGPU setups, repeated calls to cancel all outstanding
The debugger must be notified by any debugger subscribed exception
that comes from hardware interrupts.
If a debugger session exits, any exceptions it subscribed to may still
have interrupts in the interrupt ring buffer or KGD/KFD pipeline.
To prevent a new session from inheriting stale interrupts
Implement the per-device calls to enable or disable HW debug mode
for GFX11.
v2: remove unneeded ioctl reference and fix types and comment formats.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 38 +++
1 file changed
Allow the debugger to query a single queue, device and process
exception.
The KFD should also return the GPU or Queue id of the exception.
The debugger also has the option of clearing exceptions after
being queried.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd
This operation allows the debugger to override the enabled HW
exceptions on the device.
On debug devices that only support the debugging of a single process,
the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK
register.
Because they are global, only address watch exceptions are all
The debugger subscibes to nofication for requested exceptions on attach.
Allow the debugger to change its subsciption later on.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 36 +++
Similar to the F32 HWS, the RS64 HWS for GFX11 now supports a multi-process
debug API.
The skip_process_ctx_clear ADD_QUEUE requirement is to prevent the MES
from clearing the process context when the first queue is added to the
scheduler in order to maintain debug mode settings during queue preem
Unlike single process debug devices, multi-process debug devices allow
debug mode setting per-VMID (non-device-global).
Because the HWS manages PASID-VMID mapping, the new MAP_PROCESS API allows
the KFD to forward the required SPI debug register write requests.
To request a new debug mode setting
Due to a HW bug, waves in only half the shader arrays can enter trap.
When starting a debug session, relocate all waves to the first shader
array of each shader engine and mask off the 2nd shader array as
unavailable.
When ending a debug session, re-enable the 2nd shader array per
shader engine.
Allow the debugger to get a snapshot of a specified number of queues
containing various queue property information that is copied to the
debugger.
Since the debugger doesn't know how many queues exist at any given time,
allow the debugger to pass the requested number of snapshots as 0 to get
the a
Allow the debugger to query additional info based on an exception code.
For device exceptions, it's currently only memory violation information.
For process exceptions, it's currently only runtime information.
Queue exception only report the queue exception status.
The debugger has the option of c
On GFX9.4.1, the implicit wait count instruction on s_barrier is
disabled by default in the driver during normal operation for
performance requirements.
There is a hardware bug in GFX9.4.1 where if the implicit wait count
instruction after an s_barrier instruction is disabled, any wave that
hits a
Older HW only supports debugging on a single process because the
SPI debug mode setting registers are device global.
The HWS has supplied a single pinned VMID (0xf) for MAP_PROCESS
for debug purposes. To pin the VMID, the KFD will remove the VMID from
the HWS dynamic VMID allocation via SET_RESOUC
Similar to queue snapshot, return an array of device information using
an entry_size check and return.
Unlike queue snapshots, the debugger needs to pass to correct number of
devices that exist. If it fails to do so, the KFD will return the
number of actual devices so that the debugger can make a
To enable HW debug mode per process, all devices must be debug enabled
successfully. If a failure occures, rewind the enablement of debug mode
on the enabled devices.
A power management scenario that needs to be considered is HW
debug mode setting during GFXOFF. During GFXOFF, these registers
wi
The debugger can attach to a process prior to HSA enablement (i.e.
inferior is spawned by the debugger and attached to immediately before
target process has been enabled for HSA dispatches) or it
can attach to a running target that is already HSA enabled. Either
way, the debugger needs to know the
Add a debug operation that allows the debugger to send an exception
directly to runtime through a payload address.
For memory violations, normal vmfault signals will be applied to
notify runtime instead after passing in the saved exception data
when a memory violation was raised to the debugger.
Allow the debugger to set wave behaviour on to either normally operate,
halt at launch, trap on every instruction, terminate immediately or
stall on allocation.
v3: remove unrequired stall_launch reference in an earlier patch.
gfx off optimization will be addressed later.
v2: add gfx11 support an
In order to inspect waves from the saved context at any point during a
debug session, the debugger must be able to preempt queues to trigger
context save by suspending them.
On queue suspend, the KFD will copy the context save header information
so that the debugger can correctly crawl the appropr
Allow the debugger to set single memory and single ALU operations.
Some exceptions are imprecise (memory violations, address watch) in the
sense that a trap occurs only when the exception interrupt occurs and
not at the non-halting faulty instruction. Trap temporaries 0 & 1 save
the program count
From: Jay Cornwall
Trap handler behavior will differ when a debugger is attached.
Make the debug trap flag available in the trap handler TMA.
Update it when the debug trap ioctl is invoked.
v4: fix up comments to clarify flagging implementation.
v3: Rebase for upstream
v2:
Add missing debug f
Bump the minor version to declare debugging capability is now
available.
v2: bump to 1.13 after upstream rebase.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 -
include/uapi/linux/kfd_ioctl.h | 3 ++-
2 files changed, 2 inse
Shader read, write and atomic memory operations can be alerted to the
debugger as an address watch exception.
Allow the debugger to pass in a watch point to a particular memory
address per device.
Note that there exists only 4 watch points per devices to date, so have
the KFD keep track of what w
Legacy debug devices limited to pinning a single debug VMID for debugging
are the only devices that require disabling GFX OFF while accessing
debug registers. Debug devices that support multi-process debugging
rely on the hardware scheduler to update debug registers and do not run
into GFX OFF acc
[AMD Official Use Only - General]
Thanks a lot Alex for reviewing the patch.
Best Regards,
Srini
-Original Message-
From: Alex Deucher
Sent: Tuesday, March 28, 2023 12:12 AM
To: SHANMUGAM, SRINIVASAN
Cc: Koenig, Christian ; Deucher, Alexander
; Limonciello, Mario ;
Mahfooz, Hamza ;
Hi,
That's a good fix. Some questions and comments below:
On 2023-03-27 11:20, Alan Liu wrote:
> [Why]
> After gpu-reset, sometimes the driver would fail to enable vblank irq,
> causing flip_done timed out and the desktop freezed.
>
> During gpu-reset, we will disable and enable vblank irq in dm
From: Hawking Zhang
Add initial KFD support
Convert a few structures to IP version checking (Hawking)
Signed-off-by: Elena Sakhnovitch
Signed-off-by: Hawking Zhang
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/a
From: Amber Lin
For GC 9.4.3, disable retry as default and XNACK can be different
modes per process.
Signed-off-by: Amber Lin
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++-
2 files ch
From: Amber Lin
On GC 9.4.3, DW 41 in MQD is repurposed as compute_tg_chunk_size
for cooperative dispatch. When it's a AQL queue, set compute_tg_chunk_size
as 1 to spread work groups evenly among XCCs. If it's PM4 queue, unset
compute_tg_chunk_size to disable cooperative mode.
v3: set compute_tg
From: Graham Sider
Required for Thunk GFX version sysfs query.
Signed-off-by: Graham Sider
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dev
From: Amber Lin
GC 9.4.3 uses the hardware to update AQL queues read pointer, so
remove CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK flag from MQD if it's
GC 9.4.3, and keep it for other existing gfx9 ASICs.
Signed-off-by: Amber Lin
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/
From: Hawking Zhang
Add common IP handling for GC 9.4.3
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/g
From: Hawking Zhang
init asic funcs and cp/pg flags for GC 9.4.3
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/a
From: Jay Cornwall
v1:
Check new exception bits in TRAPSTS register
Remove single step exception workaround, now part of
exception bits
v2:
GC 9.4.3 uses ttmp11 to store {1’b0, dispatch index [24:0],
wave_id_in_workgroup[5:0]}, so use ttmp13 instead of ttmp11 to
preserve ib_sts. (Laurent)
Signe
From: Hawking Zhang
all the gc v9_4_3 registers fall in gc_rlcpdec address range
have different relative offsets and base_idx from the ones
defined in gc v9_0 ip headers. gc_v9_0_rlc_funcs can not be
reused anymore for gc v9_4_3
v2: drop unused handshake function (Alex)
Signed-off-by: Hawking Z
From: Hawking Zhang
add gfx_funcs callbacks implemenation based on
gc_v9_4_3 ip headers
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 154 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h | 1 +
2 f
[Why&How]
Fix the incorrect value for parameters used to enable multi plane
overlay support for DCN321
Fixes: 235c6763423 ("drm/amd/display: add DCN32/321 specific files for Display
Core")
Cc: sta...@vger.kernel.org
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn321/dcn32
From: Le Ma
Add some basic definitions and structure member. Inscrease MAX_WB slots
to 1024 to support the increasing number of rings for multiple partitions.
v2: unify naming style
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/am
From: Le Ma
It looks better to place this field in ring
structure. Also drop the repeated ring funcs definitions
if there's no difference except for vmhub field.
v2: rename the field to vm_hub like others (Le)
v3: apply the changes to new ip blocks (Hawking)
v4: fix vcn sw ring (Alex)
Signed-of
From: Le Ma
v1: more kiq instances are a available in SOC (Le)
v2: squash commits to avoid breaking the build (Le)
v3: make the conversion for gfx/mec v11_0 (Hawking)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../drm/amd/amd
From: Le Ma
To allocate independent queue_bitmap for each XCD,
then the old bitmap policy can be continued to use
with a clear logic.
Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs.
v2: squash commits to avoid breaking the build
v3: unify naming style
Signed-off-by: Le Ma
Reviewed-by:
From: Le Ma
v1: Modify kiq_init/fini, mqd_sw_init/fini and
enable/disable_kcq to adapt to multi-die case.
Pass 0 as default to all asics with single xcc (Le)
v2: squash commits to avoid breaking the build (Le)
v3: unify naming style (Le)
v4: apply the changes to gc v11_0 (Hawking)
Signed-off-by:
From: Le Ma
This will benifit the mqd indexing for kiq/kcq in multi XCD case.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
From: Le Ma
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 10 +++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 +--
From: Le Ma
As the layout of VMHUB definition has been changed to cover multiple
XCD/AID case, the original num_vmhubs is not appropriate to do vmhub
iteration any more.
Drop num_vmhubs and introduce vmhubs_mask instead.
v2: switch to the new VMHUB layout
v3: use DECLARE_BITMAP to define vmhubs
From: Le Ma
Assign value here as the num_xcd is referenced in some gfx9 common path.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
From: Le Ma
v1: To support multple XCD case (Le)
v2: unify naming style (Le)
v3: apply the changes to gc v11_0 (Hawking)
v4: apply the changes to gc SOC21 (Morris)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Morris Zhang
Signed-off-by: Alex Deu
From: Le Ma
Each XCD needs to be initialized respectively. The major changes are:
1. add iteration to do rlc/kiq/kcq init/fini for each xcd
2. load rlc/mec microcode to each xcd
3. add argument to specify xcc index in initialization functions
Signed-off-by: Le Ma
Reviewed-by: Hawking Zha
From: Le Ma
Pass the xcc_id to AMDGPU_GFXHUB(x)
Signed-off-by: Le Ma
Reviewed-by: Christian König
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
2 files changed, 2 insertions(+), 2 de
From: Le Ma
Skip KCQ setup on slave xcc as there's no use case.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 59 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +
drivers/gpu/drm/amd/amdgpu/a
From: Le Ma
Change those v9_4_3 interfaces which are exposed in gfx_v9_0.c.
For some active single-xcc emu models, the code path in
gfx_v9_0.c is better to keep reserved for a while.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gf
From: Le Ma
To prepare for gc v9_4_3 specific feature.
v2: fix exports (Alex)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2668 ++-
drivers/gpu/drm/amd/amdgpu/gfx_
From: Le Ma
v1: To support multiple XCD case (Le)
v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 +--
drivers/gpu/drm/
From: Shiwu Zhang
There are AMDGPU_MAX_VMHUBS of vmhub in maximum and need to init the
vm_inv_engs for all of them.
In this way, the below error can be ruled out.
[ 217.317752] amdgpu :02:00.0: amdgpu: no VM inv eng for ring sdma0
Signed-off-by: Shiwu Zhang
Reviewed-by: Christian Koenig
From: Le Ma
Each XCD has its own gfxhub.
v2: switch to the new VMHUB layout
v3: fix mistake
Signed-off-by: Le Ma
Reviewed-by: Christian König
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 58 ++--
1 file changed, 3
From: Hawking Zhang
v1: Each partition has its own gfxhub or mmhub. adjust
the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le)
v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le)
v3: apply the gfxhub/mmhub layout to new IPs (Hawking)
v4: fix up gmc11 (Alex)
v5: rebase (Alex)
Signed-o
From: Le Ma
Each XCD needs to do gfxhub init
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 581 +--
1 file changed, 317 insertions(+), 264 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gf
From: Shiwu Zhang
Add a module parameter to override the partition mode.
Signed-off-by: Shiwu Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +
drivers/gpu/drm/amd/amdgpu/gfx_v
From: Le Ma
Allocate different doorbell index for kiq/kcq rings
on each die
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 9 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 5 +
drivers/gpu/drm/amd/
From: Le Ma
Add current/available compute partitin mode sysfs node.
v2: make the sysfs node as IP independent one in amdgpu_gfx.c
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/am
From: Amber Lin
New GC (v9.4.3) and ATHUB (v1.8.0) versions
are used. Add kgd_gfx_v9_4_3_*
functions if registers in use of kgd_gfx_v9_*
functions are changed or have different offset.
Signed-off-by: Amber Lin
Acked-by: Felix Kuehling
Reviewed-by: Mukul Joshi
Signed-off-by: Alex Deucher
---
From: James Zhu
Add more macro to support offset variant and
simplify macro SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 28 +
From: Shiwu Zhang
To write regs on different GCDs, use the inst index.
Signed-off-by: Shiwu Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/
From: Lijo Lazar
Use SOC15 API so that the register offset is calculated correctly.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
From: Le Ma
Each XCD owns one GFXHUB.
v2: switch to the new VMHUB layout
Signed-off-by: Le Ma
Acked-by: Christian König
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a
This adds support for VCN 4.0.3. VCN is the media engine on AMD
GPUs. Patch 1 add new register headers and is too big for the
mailing list.
Hawking Zhang (1):
drm/amdgpu: add vcn v4_0_3 ip headers
James Zhu (10):
drm/amdgpu: add VCN4_0_3 firmware
drm/amdgpu/jpeg: add jpeg support for VCN4
From: James Zhu
Add VCN4_0_3 firmware.
v2: fix fw name (Alex)
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
From: James Zhu
Add vcn support for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1438 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h | 29
From: James Zhu
Enable jpeg pg for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu
From: James Zhu
Enable vcn pg for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 5ccd
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