Should I push this to drm-misc-next or do we take it through
amd-staging-drm-next?
Christian.
Am 30.03.23 um 21:50 schrieb Alex Deucher:
From: Rajneesh Bhardwaj
This allows backing ttm_tt structure with pages from different NUMA
pools.
Tested-by: Graham Sider
Reviewed-by: Felix Kuehling
S
Am 30.03.23 um 15:10 schrieb Alex Deucher:
On Thu, Mar 30, 2023 at 6:48 AM Christian König
wrote:
Am 30.03.23 um 11:15 schrieb Liu, HaoPing (Alan):
[AMD Official Use Only - General]
Hi Christian,
Thanks for the review. Please see inline.
Best Regards,
Alan
-Original Message---
On 3/31/2023 2:55 AM, Alex Deucher wrote:
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
From: Arvind Yadav
This patch:
- adds some new parameters defined for the gfx usermode queues
use cases in the v11_mqd_struct.
- sets those parametes with the respective allocated gpu contex
Hi Luben,
sorry, looks like I haven't seen your reply in my inbox at the time I've
wrote my reply.
That seems to happen quite often with freedesktop.org list recently and
I'm wondering if there's something wrong with my setup or the list server.
Christian.
Am 30.03.23 um 14:27 schrieb Lube
Am 30.03.23 um 21:17 schrieb Alex Deucher:
Only set the supported flag if we have new enough CP FW.
XXX: don't commit this until the CP FW versions are finalized!
Maybe commit the rest of this series and just hold back this one?
It should still keep everything working.
Regards,
Christian.
Am 30.03.23 um 21:17 schrieb Alex Deucher:
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMD
Am 30.03.23 um 21:48 schrieb Alex Deucher:
From: James Zhu
[WA] Increase AMDGPU_MAX_HWIP_RINGS to 64 to support more compute
ring resource. Later need redesign with queue/prirority/scheduler
factors to reduce AMDGPU_MAX_HWIP_RINGS.
This is just a workaround for internal use and not meant f
Am 30.03.23 um 21:48 schrieb Alex Deucher:
From: Harish Kasiviswanathan
‘for’ loop initial declarations are only allowed in C99 or C11 mode
This isn't necessary any more and can be dropped.
Christian.
Signed-off-by: Harish Kasiviswanathan
Reviewed-by: Mukul Joshi
Signed-off-by: Alex Deu
[AMD Official Use Only - General]
> -Original Message-
> From: Yang, WenYou
> Sent: Wednesday, March 29, 2023 5:43 PM
> To: Peter Zijlstra
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; Quan, Evan
> ; Limonciello, Mario ;
> b...@alien8.de; jpoim...@kernel.org; Phillips,
[AMD Official Use Only - General]
Please ignore this v2 patch, already have one with the fix. Thanks.
https://gitlab.freedesktop.org/agd5f/linux/-/commit/2fec9dc8e0acc3dfb56d1389151bcf405f087b10
Best Regards,
Tim Huang
-Original Message-
From: Huang, Tim
Sent: Friday, March 31, 2023 11
Skip mode2 reset only for IMU enabled APUs when do S4 to
fix the possible S4 regression issues on old ASICs.
v2:
Update this commit message to add Fixes and Link tags.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2483
Fixes: 2bedd3f21b30 ("drm/amdgpu: skip ASIC reset for APUs when go to
[AMD Official Use Only - General]
Yes, will use the Fixes and Link tags, thanks so much.
Best Regards,
Tim Huang
-Original Message-
From: Limonciello, Mario
Sent: Thursday, March 30, 2023 8:36 PM
To: Zhang, Yifan ; Huang, Tim ;
amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Yua
Hi Jonathan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-exynos/exynos-drm-next drm-intel/for-linux-next
drm-tip/drm-tip next-20230330]
[cannot apply to drm-misc/drm-misc-next drm-intel/for-linux-next-fixes
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
>
> From: Arvind Yadav
>
> This patch:
> - adds some new parameters defined for the gfx usermode queues
> use cases in the v11_mqd_struct.
> - sets those parametes with the respective allocated gpu context
> space addresses.
>
> Cc: Alex
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
>
> From: Shashank Sharma
>
> The FW expects us to allocate atleast one page as context space to
> process gang, process, shadow, GDS and FW related work. This patch
> creates a joint object for the same, and calculates GPU space offsets
>
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
>
> From: Shashank Sharma
>
> A Memory queue descriptor (MQD) of a userqueue defines it in the harware's
> context. As MQD format can vary between different graphics IPs, we need gfx
> GEN specific handlers to create MQDs.
>
> This patch:
>
On Wed, Mar 29, 2023 at 12:05 PM Shashank Sharma
wrote:
>
> From: Shashank Sharma
>
> This patch adds skeleton code for amdgpu usermode queue. It contains:
> - A new files with init functions of usermode queues.
> - A queue context manager in driver private data.
>
> V1: Worked on design review c
On Wed, Mar 29, 2023 at 11:48 AM Shashank Sharma
wrote:
>
> This patch:
> - adds a doorbell object in MES structure, to manage the MES
> doorbell requirements in kernel.
> - Removes the doorbell management code, and its variables from
> the doorbell_init function, it will be done in doorbell m
On Wed, Mar 29, 2023 at 11:48 AM Shashank Sharma
wrote:
>
> This patch:
> - adds a new doorbell manager object in kfd pdd structure.
> - allocates doorbells for a process while creating its pdd.
> - frees the doorbells with pdd destroy.
> - uses direct doorbell manager API for doorbell indexing.
>
On Wed, Mar 29, 2023 at 11:48 AM Shashank Sharma
wrote:
>
> This patch:
> - adds a doorbell manager structure in kfd device structure.
> - plugs-in doorbell manager APIs for KFD kernel doorbell allocations
> an free functions.
> - removes the doorbell bitmap, uses the one into the doorbell manag
On Thu, Mar 30, 2023 at 11:21 AM Shashank Sharma
wrote:
>
>
> On 30/03/2023 16:55, Alex Deucher wrote:
> > On Thu, Mar 30, 2023 at 10:34 AM Shashank Sharma
> > wrote:
> >>
> >> On 30/03/2023 16:15, Luben Tuikov wrote:
> >>> On 2023-03-30 10:04, Shashank Sharma wrote:
> On 30/03/2023 15:42, L
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm-intel/for-linux-next
drm-intel/for-linux-next-fixes drm-exynos/exynos-drm-next linus/master v6.3-rc4
next-20230330]
[If your patch is applied to the wrong git
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm-intel/for-linux-next
drm-intel/for-linux-next-fixes drm-exynos/exynos-drm-next linus/master v6.3-rc4
next-20230330]
[If your patch is applied to the wrong git
On Wed, Mar 29, 2023 at 11:48 AM Shashank Sharma
wrote:
>
> From: Alex Deucher
>
> This patch adds changes:
> - to accommodate the new GEM domain DOORBELL
> - to accommodate the new TTM PL DOORBELL
>
> in order to manage doorbell pages as GEM object.
>
> V2: Addressed reviwe comments from Christi
From: Rajneesh Bhardwaj
This allows backing ttm_tt structure with pages from different NUMA
pools.
Tested-by: Graham Sider
Reviewed-by: Felix Kuehling
Signed-off-by: Christian König
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/ttm/ttm_device.c | 2 +-
d
I think this workaround was reverted later after a firmware fix.
Regards,
Felix
Am 2023-03-30 um 15:42 schrieb Alex Deucher:
From: Philip Yang
MEC FW should flush TLB and cache when unmapping user queues, this
is not working correctly in master FW via HIQ, it affects SDMA queues
which use
From: Lijo Lazar
For MQD init, an XCC's queue is selected with GRBM select. However, for
initialization of MQD, values read from logical XCC0 registers are used.
This results in garbage values being read from XCC0 whose queue is not
selected. Change to read from the right XCC for MQD initializati
From: Lijo Lazar
Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove
programming that is not meant for GC 9.4.3.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 14 +-
drivers/gpu/drm/amd
From: Lijo Lazar
Program different ranges in each XCC with MEC_DOORBELL_RANGE_LOWER/HIGHER.
Keeping the same range causes CPF in other XCCs also to be busy when an IB
packet is submitted to KCQ. Only the XCC which processes the packet
comes back to idle afterwards and this causes other CPs not be
From: Harish Kasiviswanathan
‘for’ loop initial declarations are only allowed in C99 or C11 mode
Signed-off-by: Harish Kasiviswanathan
Reviewed-by: Mukul Joshi
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 del
From: Rajneesh Bhardwaj
GFXIP 9.4.3 could be in APU or carveout mode but we cannot use the
xgmi.connected_to_cpu flag to identify the iolinks type. Use appropriate
APU or Carveout mode based condition to report xgmi connection in kfd
topology.
Reviewed-by: Felix Kuehling
Signed-off-by: Rajneesh
From: James Zhu
Add num_xcps return.
Signed-off-by: James Zhu
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
b/drivers/gpu/d
From: Lijo Lazar
During ASIC wide reset, SDMA shouldn't be clockgated and be ready to
accept freeze requests from PMFW. For that, don't stop SDMA engine
during reset and keep the clocks active.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/d
From: James Zhu
[WA] Increase AMDGPU_MAX_HWIP_RINGS to 64 to support more compute
ring resource. Later need redesign with queue/prirority/scheduler
factors to reduce AMDGPU_MAX_HWIP_RINGS.
Signed-off-by: James Zhu
Acked-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/
From: Asad kamal
SDMA v4.4.2 doesn't need explicit power gating control through PMFW
Signed-off-by: Asad kamal
Reviewed-by: Hawking Zhang
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4
1 file changed, 4 deletions(-)
diff --git a/d
From: Lijo Lazar
Certain instances of VCN/JPEG IPs may not be usable. Fetch the information
from harvest table.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8
1 file changed, 4 insertions(+), 4
From: James Zhu
Enable vcn/jpeg on vcn_v4_0_3.
Signed-off-by: James Zhu
Acked-by Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/d
From: Graham Sider
Revert temporary dGPU VRAM MTYPE setting and align with expected
coherency protocol.
Signed-off-by: Graham Sider
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 15 +--
drivers/gpu/drm/amd/amdkfd/kfd_svm.c |
From: James Zhu
Signed-off-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd
From: James Zhu
Add unified queue support on vcn_v4_0_3.
Signed-off-by: James Zhu
Acked-by Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 173 +---
2 files changed, 102 insertions(+), 80
From: James Zhu
Enable indirect_sram mode on vcn_v4_0_3.
Signed-off-by: James Zhu
Acked-by Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vc
From: James Zhu
Add fwlog support on vcn_v4_0_3.
Signed-off-by: James Zhu
Acked-by Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_
From: Lijo Lazar
Get information about active XCC and SDMAs from discovery table.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 25 ---
1 file changed, 22 insertions(+),
From: Rajneesh Bhardwaj
[NOT FOR UPSTREAM]
For debug purpose and more test coverage, we want to enable GART in the
system memory for GFXIP9.4.3 bring up branch while we still continue to
use the APU in the carveout mode.
Reviewed-by: Felix Kuehling
Suggested-by: Harish Kasiviswanathan
Signed-
From: Mukul Joshi
In GFX 9.4.3, there can be more than 8 SDMA engines.
As a result, extended_engine_sel and engine_sel fields
in MAP_QUEUES packet need to be updated to allow correct
mapping of SDMA queues to these SDMA engines.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
Signed-off
From: Felix Kuehling
[NOT FOR UPSTREAM]
Christian prefers to use another TTM based version for upstream so this
should be used on the NPI branch till the said patch lands on the
upstream list.
Some AMD APUs may not have a dedicated VRAM. On such platforms the GART
table should be allocated on th
From: Rajneesh Bhardwaj
Apply the GFXIP 9.4.3 specific snoop and mtype settings for various
scenarios such as APU, APU in Carveout mode and dGPU mode.
Note: This is expected to change due to:
1 - NPS > 1 support in future
2 - Hardware bugs found during initial asic bringup.
Cc: Graham Sider
Cc
From: James Zhu
vcn_v4_0_3 increased jpeg instances,
need increasing MAX resources setting accordlingly.
Signed-off-by: James Zhu
Acked-by Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 +-
dri
From: Lijo Lazar
ASICs with GFX 9.4.3 support 48-bit addressing.
Signed-off-by: Lijo Lazar
Acked-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
From: Lijo Lazar
Add logic for fine grain clock gating logic for GFX v9.4.3. The feature
will be controlled using CG flags. Also, make a change so that RLC safe
mode entry/exit is done only once during CG update sequence.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex
From: Lijo Lazar
When overridden with module param, directly read discovery info
from discovery binary instead of reading from VRAM.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 31 +--
1
From: Lijo Lazar
Use a mask of available active clusters instead of using only the number
of active clusters.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
.../drm/amd/amdgpu/aqua_vanjaram_reg_init.
From: Amber Lin
For GFX v9_4_3, set MTYPE_UC for memory access over PCIe.
v4 - add missing indentation pointed out by Felix and add his
reviewed-by tag.
v3 - add missing logic for the svm path.
v2 - add amdgpu_xgmi_same_hive to separate access over xgmi from pcie
Reviewed-by: Felix Kuehling
Si
From: Mukul Joshi
Setup rolling current_logical_xcc_id in MQD for GFX9.4.3
to ensure each queue starts at a different place and prevent
hotspotting issues. Also, remove updating current_logical_xcc_id
during queue update.
Suggested-by: Joseph Greathouse
Signed-off-by: Mukul Joshi
Reviewed-by:
From: Le Ma
The AMDGPU_GFXHUB was bind to each xcc in the logical order.
Thus convert the node_id to logical xcc_id to index the
correct AMDGPU_GFXHUB. And "node_id / 4" can get the correct
AMDGPU_MMHUB0 index.
Signed-off-by: Le Ma
Tested-by: Asad kamal
Reviewed-by: Hawking Zhang
Signed-off-b
From: Lijo Lazar
Each compute cluster gets 8 compute queues in GFX v9.4.3. Fix the EOP
buffer allocation so that compute queue on every XCC gets a unique
address.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Tested-and-Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
---
drivers/
From: Lijo Lazar
Use the right register for semaphore release during invalidation.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/am
From: Rajneesh Bhardwaj
On AMD APP APUs, to make UTCL2 snoop CPU caches, its not sufficient to
rely on xgmi connected flag so add the logic to use is_app_apu to
program the PDE_REQUEST_PHYSICAL bit correctly for gfxhub and mmhub
both.
Reviewed-by: Felix Kuehling
Signed-off-by: Rajneesh Bhardwaj
From: Mukul Joshi
The calculation for allocating the SDMA+HIQ HQDs was updated
incorrectly when support for GFX 9.4.3 was added. This causes
kernel crash logs when allocating SDMA HQDs.
Fixes: bb3dcef654a8 ("drm/amdkfd: Update MQD management on multi XCC setup")
Signed-off-by: Mukul Joshi
Revie
From: Lijo Lazar
There is no need to check return value, as the function internally
used - amdgpu_discovery_read_binary_from_vram() - returns void.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 10 ++
1 fi
From: Lijo Lazar
SDMA instances per active cluster and SDMA instance mask are used
to find the number of active clusters.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 10 ++
1 file changed,
From: Philip Yang
MEC FW should flush TLB and cache when unmapping user queues, this
is not working correctly in master FW via HIQ, it affects SDMA queues
which use mmhub on AID, cause several KFDTest failure.
Workaround this in KFD for now. Will revert this patch to verify FW fix
later.
Signed
From: Lijo Lazar
Move soc specific configuration details to aqua vanjaram specific file.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drive
From: Shiwu Zhang
Just like the KIQ, KCQ need to clear the doorbell related regs as well
to avoid hangs when to load driver again after unloading.
Signed-off-by: Shiwu Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 28 ++
From: Lijo Lazar
On ASICs with PSPv13.0.6, TMR is reserved at boot time. There is no need
to allocate TMR region by driver. However, it's still required to send
SETUP_TMR command to PSP.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/
From: Lijo Lazar
On ASICs with PSPv13.0.6, TMR is reserved at boot time. There is no need
to allocate TMR region by driver. However, it's still required to send
SETUP_TMR command to PSP.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/
From: Shiwu Zhang
Just like the KIQ, KCQ need to clear the doorbell related regs as well
to avoid hangs when to load driver again after unloading.
Signed-off-by: Shiwu Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 28 ++
From: Lijo Lazar
Add function to initialize soc configuration information for GC 9.4.3
ASICs. Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.
For GC9.4.3 compute partition related callbacks are initialized as part
of configura
From: Lijo Lazar
Switching the partition mode configuration of ASIC is SOC
level function rather than something at GFX core level. Add
partition mode switch functions as SOC specific callbacks.
Implement the XCP manager callbacks needed for partition
switch for GC 9.4.3 based ASICs.
Signed-off-b
From: Lijo Lazar
Initialize with the IP specific functions needed for GFXHUB, GFX and
SDMA.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 9 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h
From: Lijo Lazar
Add functions to suspend/resume GFX instances belonging to an XCP.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 47 +
1 file changed, 47 insertions(+)
diff --git a/driv
From: Lijo Lazar
SDMA 4.4.2 supports multiple instances. Add functions to support
handling of each SDMA instance separately.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 162 +--
1 file cha
From: Lijo Lazar
For GFXv9.4.3, use SOC level partition switch implementation rather than
keeping them at GFX IP level. Change the exisiting implementation in
GFX IP for keeping partition mode and restrict it to only GFX related
switch.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Sign
From: Lijo Lazar
Within a device, an accelerator core partition can be constituted with
different IP instances. These partitions are spatial in nature. Number
of partitions which can exist at the same time depends on the 'partition
mode'. Add a manager entity which is responsible for switching be
From: Lijo Lazar
Add functions required for suspend/resume of GFXHUB instances which are
part of an XCP.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 35
1 file changed, 35 insertions(
From: Lijo Lazar
Add functions required to suspend/resume instances of SDMA which
are part of an XCP.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 36
1 file changed, 36 insertions(+)
From: Lijo Lazar
GFXHUB 1.2 supports multiple XCC instances. Add XCC specific functions
to handle XCC instances separately.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +
drivers/gpu/drm/amd/amdgpu/gfxhub
From: Rajneesh Bhardwaj
On GPXIP 9.4.3 APU, in no carveout mode there is no real vram heap and
could be emulated by the driver over the interleaved NUMA system memory
and the APU could also be in the carveout mode during early development
stage or otherwise for debugging purpose so introduce a n
From: Philip Yang
Output IH cookie node_id and translate it to the corresponding AID id
and XCC id, to help debug the GPU page fault.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 ---
1 file changed,
From: Lijo Lazar
Add 'xcc' prefix to xcc specific functions to distinguish from IP block
functions.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 205 +---
1 file changed, 113 insertions(+),
From: Lijo Lazar
Skip reading runtime db information for PSP 13.0.6.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/
From: Shiwu Zhang
For gfx_v9_4_3 and beyond, struct kiq has its own mqd_backup pointer
rather than using the last pointer from mec struct. Then the kfree
operation on the pointer from the mec struct should be removed otherwise
it will cause double free on the first kcq's mqd_backup buffer on XCD1
From: Le Ma
Assign the vm context register addr per aid instance.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amd
From: Rajneesh Bhardwaj
- Add helpers to detect the current GPU memory partition.
- Add current memory partition mode sysfs node.
Tested-by: Ori Messinger
Reviewed-by: Felix Kuehling
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
From: Shiwu Zhang
For driver de-init like rmmod operations those partition specific
attributes need to be removed accordingly.
Signed-off-by: Shiwu Zhang
Reviewed-by: Rajneesh Bhardwaj
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 +++
drivers/gpu/drm/amd/am
From: Lijo Lazar
Programming of this register is taken care by PSP. Incorrect programming
causes CP not to detect its XCC.
Signed-off-by: Lijo Lazar
Reported-by: Alexander Turek
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 ---
1 fil
Use the new callback to fetch the data. Return an error if
not supported. UMDs should use this query to check whether
shadow buffers are supported and if so what size they
should be.
v2: return an error rather than a zerod structure.
v3: drop GDS, move into dev_info structure. Data will be
Use this to determine if we support the new SET_Q_PREEMPTION_MODE
packet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu
We need to reset the shadow state every time we submit an
IB and there needs to be a COND_EXEC packet after the
SET_Q_PREEMPTION_MODE packet for it to work properly, so
we should emit both of these packets regardless of whether
there is a job present or not.
Reviewed-by: Christian König
Signed-of
Provide a debugfs interface to access the MQD. Useful for
debugging issues with the CP and MES hardware scheduler.
v2: fix missing unreserve/unmap when pos >= size (Alex)
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 60 +++
From: Christian König
Add ring callback for gfx to update the CP firmware
with the new shadow information before we process the
IB.
v2: add implementation for new packet (Alex)
v3: add current FW version checks (Alex)
v4: only initialize shadow on first use
Only set IB_VMID when a valid shad
It varies by generation and we need to know the size
to expose this via debugfs.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/g
To provide IP specific shadow sizes. UMDs will use
this to query the kernel driver for the size of the
shadow buffers.
v2: make callback return an int (Alex)
v3: drop GDS (Alex)
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 10 +
From: Christian König
Add support for submitting the shadow update packet
when submitting an IB. Needed for MCBP on GFX11.
v2: update API for CSA (Alex)
v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC
Add missing check for AMDGPU_CHUNK_ID_CP_GFX_SHADOW in
amdgpu_cs_pa
Add UAPI to query the GFX shadow buffer requirements
for preemption on GFX11. UMDs need to specify the shadow
areas for preemption.
v2: move into existing asic info query
drop GDS as its use is determined by the UMD (Marek)
v3: Update comments to note that alignment is base
virtual alignm
So UMDs can determine whether the kernel supports this.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
Used to get the size and alignment requirements for
the gfx shadow buffer for preemption.
v2: use FW version check to determine whether to
return a valid size here
return an error if not supported (Alex)
v3: drop GDS (Alex)
v4: make amdgpu_gfx_shadow_info mandatory (Alex)
Signed-off-by: A
Only set the supported flag if we have new enough CP FW.
XXX: don't commit this until the CP FW versions are finalized!
Acked-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/
For GFX11, the UMD needs to allocate some shadow buffers
to be used for preemption. The UMD allocates the buffers
and passes the GPU virtual address to the kernel since the
kernel will program the packet that specified these
addresses as part of its IB submission frame.
v2: UMD passes shadow init
This patch set allows for FW assisted shadowing on supported
platforms. A new enough CP FW is required. This feature is
required for mid command buffer preemption and proper SR-IOV
support. This also simplifies the UMDs by allowing persistent
hardware state when the command submission executes.
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