if check over DSC passthrough is removed, as this is not for
MST use case. It is for DP-HDMI pcon use case. sst pcon is
detected as sst not mst. In sst pcon dsc passthrough message
will not get below log printed
'Fixes: 8dc5bfdab0ecf ("drm/amd/display: Check & log if receiver supports
MST, DSC &
On 2023-02-28 03:34, Christian König wrote:
Avoids quite a bit of logic and kmalloc overhead.
Not sure what's the status of this patch series. In general I'm in
favour. I think it could help with some tricky locking cases for the
work we're doing for validating GEM objects in KFD contexts.
On 4/21/23 14:39, Aurabindo Pillai wrote:
[Why]
Drop the above line, with that:
Reviewed-by: Rodrigo Siqueira
OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if
writes to OTG timing registers need to be honoured. This is usually
needed only when freesync is active.
On 4/21/23 14:39, Aurabindo Pillai wrote:
This reverts commit 541908cc2cca427fc3ae3bd4c9b82797a78e63a9.
Hi,
Please add an explanation of the reason why we want to revert this patch.
With that change:
Reviewed-by: Rodrigo Siqueira
Thanks
Siqueira
---
[Why]
OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if
writes to OTG timing registers need to be honoured. This is usually
needed only when freesync is active. However, SubVP + DRR requires that
we're able to change timing even without freesync being active (but
supported). By
This reverts commit 541908cc2cca427fc3ae3bd4c9b82797a78e63a9.
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 5 -
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4
drivers/gpu/drm/amd/include/amd_shared.h | 1 -
3 files changed, 10 deletions(-)
diff --git
On 2023-04-12 12:25, Shashank Sharma wrote:
This patch:
- adds a doorbell object in kfd pdd structure.
- allocates doorbells for a process while creating its pdd.
- frees the doorbells with pdd destroy.
- removes previous calls to allocate process doorbells as
its not required anymore.
PS:
On 2023-04-12 12:25, Shashank Sharma wrote:
This patch:
- adds a doorbell bo in kfd device structure.
- creates doorbell page for kfd kernel usages.
- updates the get_kernel_doorbell and free_kernel_doorbell functions
accordingly
V2: Do not use wrapper API, use direct
On 2023-04-20 18:25, Xiaogang.Chen wrote:
From: Xiaogang Chen
amdgpu_ttm_tt_get_user_pages can fail(-EFAULT). If it failed mem has no
associated
hmm range or user_pages associated. Keep it at process_info->userptr_inval_list
and
mark mem->invalid until following scheduled attempts can valid
[Public]
Hi all,
This week this patchset was tested on the following systems:
Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
Lenovo Thinkpad T13s Gen4 with AMD Ryzen 5 6600U
Reference AMD RX6800
These systems were tested on the following display types:
eDP, (1080p 60hz [5650U])
On Fri, Apr 21, 2023 at 3:30 AM Evan Quan wrote:
>
> Disable the pcie lane switching for some sienna_cichlid SKUs since it
> might not work well on some platforms.
>
> Signed-off-by: Evan Quan
> Change-Id: Iea9ceaa146c8706768ee077c10e5d33bce9bc1c2
> ---
>
[AMD Official Use Only - General]
Sure. We can pull it into amd-staging-drm-next as well if we need it for any
customers in the short term.
Alex
From: Christian König
Sent: Friday, April 21, 2023 9:27 AM
To: amd-gfx@lists.freedesktop.org ; Deucher,
Alexander
[Public]
> -Original Message-
> From: Quan, Evan
> Sent: Friday, April 21, 2023 02:29
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Limonciello, Mario
> ; Quan, Evan
> Subject: [PATCH] drm/amd/pm: conditionally disable pcie lane switching for
> some sienna_cichlid
Alex can I merge that through drm-misc-next or do we really need
amd-staging-drm-next?
Christian.
Am 21.04.23 um 07:22 schrieb Luben Tuikov:
Hi Christian,
Thanks for working on this.
Series is,
Reviewed-by: Luben Tuikov
Regards,
Luben
On 2023-04-20 07:57, Christian König wrote:
When a
Am 20.04.23 um 16:47 schrieb Arunpravin Paneer Selvam:
This patch introduces new IOCTL for userqueue secure semaphore.
The signal IOCTL called from userspace application creates a drm
syncobj and array of bo GEM handles and passed in as parameter to
the driver to install the fence into it.
The
[Public]
Much appreciated, Ville and Jani!
To tackle this MST message ack event now, probably I could just pull out the
drm_dp_mst_kick_tx() out of drm_dp_mst_hpd_irq() and make it the second
step function to handle mst hpd irq? Would like to know your thoughts : )
Again, thanks for your
Am 20.04.23 um 16:47 schrieb Arunpravin Paneer Selvam:
Developed a userqueue fence driver for the userqueue process shared
BO synchronization.
Create a dma fence having write pointer as the seqno and allocate a
seq64 memory for each user queue process and feed this memory address
into the
Am 20.04.23 um 16:47 schrieb Arunpravin Paneer Selvam:
Developed a new driver which allocates a 64bit memory on
each request in sequence order. At the moment, user queue
fence memory is the main consumer of this seq64 driver.
v2: Worked on review comments from Christian for the following
Am 21.04.23 um 09:06 schrieb Jack Xiao:
The fences associated with mes queue have to be freed
up during amdgpu_ring_fini.
Signed-off-by: Jack Xiao
Well big NAK to this! The fences are supposed to be freed by the fence
handling code.
Christian.
---
Am 20.04.23 um 18:00 schrieb Hamza Mahfooz:
Currently, on a handful of ASICs. We allow the framebuffer for a given
plane to exist in either VRAM or GTT. However, if the plane's new
framebuffer is in a different memory domain than it's previous
framebuffer, flipping between them can cause the
On 4/21/2023 1:02 PM, Quan, Evan wrote:
[AMD Official Use Only - General]
This seems able to address some audio noise issue observed per customer's
feedback.
Evan
-Original Message-
From: Quan, Evan
Sent: Friday, April 21, 2023 3:29 PM
To: amd-gfx@lists.freedesktop.org
Cc:
[AMD Official Use Only - General]
For some Vulkan stress tests, it might be not possible to rewrite using ROCm.
After a twice think, it might be too risky if we put 120s, because of the
softlockup timeout set to 120s.
To support some stress tests like the one which recently I saw on stressbench
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Xiao, Jack
Sent: Friday, April 21, 2023 15:06
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Cc: Xiao, Jack
Subject: [PATCH] drm/amdgpu: fix memory leak in mes self test
The
[AMD Official Use Only - General]
This seems able to address some audio noise issue observed per customer's
feedback.
Evan
> -Original Message-
> From: Quan, Evan
> Sent: Friday, April 21, 2023 3:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Limonciello, Mario
>
Disable the pcie lane switching for some sienna_cichlid SKUs since it
might not work well on some platforms.
Signed-off-by: Evan Quan
Change-Id: Iea9ceaa146c8706768ee077c10e5d33bce9bc1c2
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 92 +++
1 file changed, 74
The fences associated with mes queue have to be freed
up during amdgpu_ring_fini.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
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