XCP_CTL register is expected to be programmed by firmware. Under certain
conditions FW may not have programmed it correctly. As a workaround,
program it when FW has not programmed the right values.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 23
[AMD Official Use Only - General]
OK, will do.
-
Best Regards,
Thomas
-Original Message-
From: Zhang, Hawking
Sent: Thursday, July 20, 2023 1:44 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Li, Candice ; Yang,
Stanley
Subject: RE: [PATCH 2/2]
[AMD Official Use Only - General]
Please apply the same change to gmc_v10_0_process_interrupt.
Might be better to check the client_id == VMC to decide vmhub.
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Thursday, July 20, 2023 13:42
To: amd-gfx@lists.freedesktop.org
[AMD Official Use Only - General]
Please ignore this series. I will send a fresh one.
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Thursday, July 20, 2023 11:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Morris
; Zhang, Hawking
Fix incorrect vmhub index.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index d04fc0f19a29..c0b588e5d6aa 100644
---
Fix printing empty string array.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index c571f0d95994..d04fc0f19a29
XCP_CTL register is expected to be programmed by firmware. Under certain
conditions FW may not have programmed it correctly. As a workaround,
program only when FW has not programmed the right values.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
---
This reverts commit cd65f5547f06b8c144063b1744011a135157e364.
FW programming is not yet functional fully. Revert till the programming
is in place in FW.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 29 +
1 file
Fixes the below checkpatch.pl warnings:
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line
WARNING: suspect code indent for conditional statements (8, 12)
WARNING: braces {} are not necessary for single statement blocks
Cc: Christian
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Saturday, July 15, 2023 11:27 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/radeon: Fix style issues in
On 2023/7/20 03:32, Bjorn Helgaas wrote:
but I think it's just confusing to
mention this in the commit log, so I would just remove it.
Ok, will be done at the next version.
Hi,
On 2023/7/20 03:32, Bjorn Helgaas wrote:
[+cc linux-pci (please cc in the future since the bulk of this patch
is in drivers/pci/)]
On Wed, Jul 12, 2023 at 12:43:05AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
Currently, the strategy of selecting the default boot on a multiple video
Hi,
On 2023/7/20 04:43, Bjorn Helgaas wrote:
[+cc linux-pci; I don't apply or ack PCI patches unless they appear there]
On Wed, Jul 12, 2023 at 12:43:04AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
The observation behind this is that we should avoid accessing the global
screen_info
Am 2023-07-19 um 17:22 schrieb Alex Sierra:
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists
from svm_range_debug_dump when dynamic debug is disabled. Otherwise,
it could drop performance, specially with big number of SVM ranges.
Make sure both svm_range_set_attr and
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists
from svm_range_debug_dump when dynamic debug is disabled. Otherwise,
it could drop performance, specially with big number of SVM ranges.
Make sure both svm_range_set_attr and svm_range_debug_dump functions
are dynamically enabled
Hi,
On 2023/7/20 04:43, Bjorn Helgaas wrote:
On Wed, Jul 12, 2023 at 12:43:02AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
This patch adds the aperture_contain_firmware_fb() function to do the
determination. Unfortunately, due to the fact that the apertures list
will be freed
On Wed, Jul 12, 2023 at 12:43:02AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> This patch adds the aperture_contain_firmware_fb() function to do the
> determination. Unfortunately, due to the fact that the apertures list
> will be freed dynamically, the location and size information of
[+cc linux-pci; I don't apply or ack PCI patches unless they appear there]
On Wed, Jul 12, 2023 at 12:43:04AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> The observation behind this is that we should avoid accessing the global
> screen_info directly. Call the
Am 2023-07-19 um 14:03 schrieb Alex Sierra:
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists
from svm_range_debug_dump when dynamic debug is disabled. Otherwise,
it could drop performance, specially with big number of SVM ranges.
Make sure both svm_range_set_attr and
With my comments on patches 6 and 10 addressed this series is
Reviewed-by: Harry Wentland
Harry
On 2023-07-10 15:27, Bhawanpreet Lakha wrote:
> This patch set introduces Freesync Panel Replay capability on DCN 3.1.4
> and newer. Replay has been verified to be working with these patches (in
>
On 2023-07-10 15:27, Bhawanpreet Lakha wrote:
> - Setup replay config on device init.
> - Enable replay if feature is enabled (prioritize replay over PSR, since
> it can be enabled in more usecases)
> - Add debug masks to enable replay on supported ASICs
>
> Signed-off-by: Bhawanpreet Lakha
>
[+cc linux-pci]
On Wed, Jul 12, 2023 at 12:43:01AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> Currently, the default VGA device selection is not perfect. Potential
> problems are:
>
> 1) This function is a no-op on non-x86 architectures.
> 2) It does not take the PCI Bar may get
[+cc linux-pci (please cc in the future since the bulk of this patch
is in drivers/pci/)]
On Wed, Jul 12, 2023 at 12:43:05AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> Currently, the strategy of selecting the default boot on a multiple video
> card coexistence system is not perfect.
On 2023-07-10 15:27, Bhawanpreet Lakha wrote:
> - Add checks for Cursor update and dirty rects (sending updates to dmub)
> - Add checks for dc_notify_vsync, and fbc and subvp
>
> Signed-off-by: Bhawanpreet Lakha
> ---
> drivers/gpu/drm/amd/display/dc/core/dc.c| 6 ++
>
From: Aric Cyr
This version brings along following fixes:
- Fix underflow issue on 175hz timing
- Add interface to modify DMUB panel power options
- Remove check for default eDP panel_mode
- Add new sequence for 4-lane HBR3 on vendor specific retimers
- Update DPG test pattern programming
-
From: Leo Ma
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Leo Ma
---
From: Paul Hsieh
[Why]
This option can vary depending on the panel and may be required to be
called during sink detection phase before transmitter control.
[How]
Allow modify the bit depending on the eDP panel connected with a new
interface.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex
From: Anthony Koo
- Rearranged defs order
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 54 +--
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Taimur Hassan
[Why]
DPCD read is skipped first time after driver initialization.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Taimur Hassan
---
.../link/protocols/link_edp_panel_control.c | 49 +--
1 file changed, 24 insertions(+), 25 deletions(-)
From: Ovidiu Bunea
[Why]
In some vendor specific retimer setups for downstream 4-lane HBR3
configuration, the sink will show severe corruption (horizontal shifting)
and intermittent blanking.
[How]
Add new retimer programming sequence before clock recovery when 4 lanes
are active.
Reviewed-by:
From: Wenjing Liu
[Why]
Last ODM slice could be slightly larger than other slice because it can be
including the residual.
[How]
Update DPG pattern programming sequence to use a different width for
last odm slice.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
From: Reza Amini
[Why]
vstartup is calculated to be a large number. It works because
it is within vertical blank, but it reduces region of blank that
can be used for power gating.
[How]
Calculation needs to convert micro seconds to number of
vertical lines.
Reviewed-by: Nicholas Kazlauskas
From: Leo Chen
[Why & How]
DMUB may hang when powering down pixel clocks due to no dprefclk.
It is fixed by exiting idle optimization before the attempt to access PHY.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Leo Chen
---
From: Wenjing Liu
[Why]
Current recout calculation has a few assumptions and implementation
for MPO + ODM combine calculation is very specific. The equation has
too many cases without enough comments to document the detail.
[How]
The change remove the following assumptions:
1. When MPO is
From: Martin Tsai
[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Martin Tsai
---
.../dc/clk_mgr/dcn314/dcn314_clk_mgr.c
From: Alvin Lee
[Description]
It is not valid to set the WDIVIDER value to 0, so do not
re-write to DISPCLK_WDIVIDER if the current value is 0
(i.e., it is at it's initial value and we have not made any
requests to change DISPCLK yet).
Reviewed-by: Saaem Rizvi
Acked-by: Alex Hung
From: Ethan Bitnun
[Description]
- Prevent ODM pipe connections between pipes that are not part
of the same plane when adding a plane to context
- Re-attach child pipes of ODM slice about to be disconnected
to prevent any lost pipes with invalid tops/bottoms
- We cannot split if
From: Iswara Nagulendran
[How & Why]
When determining default aux backlight level, read from
DPCD address 0x734 for VESA SCR on OLED.
Reviewed-by: Felipe Clark
Acked-by: Alex Hung
Signed-off-by: Iswara Nagulendran
---
.../dc/link/protocols/link_edp_panel_control.c | 18 ++
1
From: George Shen
[Why]
Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other
ASICs.
[How]
Add guard to check chip family is yellow carp before applying logic.
Reviewed-by: Hansen Dsouza
Acked-by: Alex Hung
Signed-off-by: George Shen
---
From: Reza Amini
[Why]
There are grammer mistakes in comments
[How]
Correct grammar mistakes
Reviewed-by: Anthony Koo
Acked-by: Alex Hung
Signed-off-by: Reza Amini
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 20 ++-
1 file changed, 11 insertions(+), 9 deletions(-)
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fix underflow issue on 175hz timing
- Add interface to modify DMUB panel power options
- Remove check for default eDP panel_mode
- Add new sequence for 4-lane HBR3 on vendor specific retimers
- Update DPG test
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists
from svm_range_debug_dump when dynamic debug is disabled. Otherwise,
it could drop performance, specially with big number of SVM ranges.
Make sure both svm_range_set_attr and svm_range_debug_dump functions
are dynamically enabled
On 2023-07-10 16:17, Alex Deucher wrote:
On Mon, Jul 10, 2023 at 3:27 PM Bhawanpreet Lakha
wrote:
This patch set introduces Freesync Panel Replay capability on DCN 3.1.4
and newer. Replay has been verified to be working with these patches (in
house)
These patches are enabling panel replay
Am 2023-07-08 um 12:57 schrieb Alex Sierra:
svm_range_debug_dump should not be called at all when dynamic debug
is disabled to avoid iterating over SVM lists. This could drop
performance, specially with big number of SVM ranges.
Signed-off-by: Alex Sierra
Signed-off-by: Philip Yang
---
[Public]
With the scripts/package/builddeb changes dropped, the patch is:
Acked-by: Alex Deucher
From: amd-gfx on behalf of Victor Lu
Sent: Wednesday, July 19, 2023 10:52 AM
To: amd-gfx@lists.freedesktop.org
Cc: Skvortsov, Victor ; Zhou, Bob ;
Lazar, Lijo ;
Am 2023-07-19 um 10:36 schrieb Jonathan Kim:
MES can concurrently schedule queues on the device that require
exclusive device access if marked exclusively_scheduled without the
requirement of GWS. Similar to the F32 HWS, MES will manage
quality of service for these queues.
Use this for
[TLDR: I'm adding this report to the list of tracked Linux kernel
regressions; the text you find below is based on a few templates
paragraphs you might have encountered already in similar form.
See link in footer if these mails annoy you.]
On 17.07.23 15:09, Michel Dänzer wrote:
> On 5/10/23
On Wed, Jul 19, 2023 at 6:23 AM Kefeng Wang wrote:
> On 2023/7/19 17:02, Christian Göttsche wrote:
> > On Wed, 19 Jul 2023 at 09:40, Kefeng Wang
> > wrote:
> >>
> >> Use the helpers to simplify code.
> >>
> >> Cc: Paul Moore
> >> Cc: Stephen Smalley
> >> Cc: Eric Paris
> >> Acked-by: Paul
An instance of for_each_inst() was not changed to match its new
behaviour and is causing a loop.
v2: remove tmp_mask variable
Fixes: 50c1d81d6365 ("drm/amdgpu: Modify for_each_inst macro")
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 5 +-
scripts/package/builddeb
MES can concurrently schedule queues on the device that require
exclusive device access if marked exclusively_scheduled without the
requirement of GWS. Similar to the F32 HWS, MES will manage
quality of service for these queues.
Use this for cooperative groups since cooperative groups are device
Am 2023-07-19 um 03:51 schrieb Kefeng Wang:
Use the helpers to simplify code.
Cc: Felix Kuehling
Cc: Alex Deucher
Cc: "Christian König"
Cc: "Pan, Xinhui"
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Kefeng Wang
Reviewed-by: Felix Kuehling
---
Am 2023-07-14 um 05:37 schrieb Jonathan Kim:
Update the list of devices that require the cwsr trap handling
workaround for debugging use cases.
Signed-off-by: Jonathan Kim
This patch is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 5 ++---
On Wed, Jul 19, 2023 at 1:20 AM Srinivasan Shanmugam
wrote:
>
> Convert macros to functions to fix the following & for better readability:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.h:26: Macro argument reuse 'adev' -
> possible side-effects?
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.h:32:
On Wed, Jul 19, 2023 at 1:20 AM Srinivasan Shanmugam
wrote:
>
> From: Srinivasan Shanmugam
>
> Fixes the following checkpatch.pl:
>
> WARNING: printk() should include KERN_ facility level
Might be better to convert to dev_* variants so that we get better
info when there are multiple GPUs in the
Applied. Thanks!
On Tue, Jul 18, 2023 at 12:40 PM Nathan Chancellor wrote:
>
> On Mon, Jul 17, 2023 at 03:29:23PM -0700, Samuel Holland wrote:
> > clang on RISC-V appears to be unaffected by the bug causing excessive
> > stack usage in calculate_bandwidth(). clang 16 with -fstack-usage
> >
not update the same version ras ta.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
index
Add ta initialization failure check condition.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
index
On 19.07.23 09:51, Kefeng Wang wrote:
Use the helpers to simplify code.
Cc: Paul Moore
Cc: Stephen Smalley
Cc: Eric Paris
Acked-by: Paul Moore
Signed-off-by: Kefeng Wang
---
security/selinux/hooks.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
Use the helpers to simplify code.
Cc: Felix Kuehling
Cc: Alex Deucher
Cc: "Christian König"
Cc: "Pan, Xinhui"
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Kefeng Wang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
On Wed, Jul 19, 2023 at 03:51:14PM +0800, Kefeng Wang wrote:
> Use the helpers to simplify code, also kill unneeded goto cpy_name.
Grrr.. why am I only getting 4/4 ?
I'm going to write a bot that auto NAKs all partial series :/
On 2023/7/19 17:29, Peter Zijlstra wrote:
On Wed, Jul 19, 2023 at 03:51:14PM +0800, Kefeng Wang wrote:
Use the helpers to simplify code, also kill unneeded goto cpy_name.
Grrr.. why am I only getting 4/4 ?
I'm going to write a bot that auto NAKs all partial series :/
Sorry, I should add
On 2023/7/19 17:02, Christian Göttsche wrote:
On Wed, 19 Jul 2023 at 09:40, Kefeng Wang wrote:
Use the helpers to simplify code.
Cc: Paul Moore
Cc: Stephen Smalley
Cc: Eric Paris
Acked-by: Paul Moore
Signed-off-by: Kefeng Wang
---
security/selinux/hooks.c | 7 ++-
1 file
Add vma_is_initial_stack() and vma_is_initial_heap() helper and use
them to simplify code.
v2:
- address comments per David Hildenbrand and Christian Göttsche
- fix selinux build
Kefeng Wang (4):
mm: factor out VMA stack and heap checks
drm/amdkfd: use vma_is_initial_stack() and
On Wed, 19 Jul 2023 at 09:40, Kefeng Wang wrote:
>
> Use the helpers to simplify code.
>
> Cc: Paul Moore
> Cc: Stephen Smalley
> Cc: Eric Paris
> Acked-by: Paul Moore
> Signed-off-by: Kefeng Wang
> ---
> security/selinux/hooks.c | 7 ++-
> 1 file changed, 2 insertions(+), 5
On 19.07.23 09:51, Kefeng Wang wrote:
Factor out VMA stack and heap checks and name them
vma_is_initial_stack() and vma_is_initial_heap() for
general use.
Cc: Christian Göttsche
Cc: David Hildenbrand
Signed-off-by: Kefeng Wang
---
[...]
diff --git a/include/linux/mm.h
Factor out VMA stack and heap checks and name them
vma_is_initial_stack() and vma_is_initial_heap() for
general use.
Cc: Christian G??ttsche
Cc: David Hildenbrand
Signed-off-by: Kefeng Wang
---
fs/proc/task_mmu.c | 24
fs/proc/task_nommu.c | 15 +--
Use the helpers to simplify code, also kill unneeded goto cpy_name.
Cc: Peter Zijlstra
Cc: Arnaldo Carvalho de Melo
Signed-off-by: Kefeng Wang
---
kernel/events/core.c | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/kernel/events/core.c
On 19.07.23 09:51, Kefeng Wang wrote:
Use the helpers to simplify code.
Cc: Felix Kuehling
Cc: Alex Deucher
Cc: "Christian König"
Cc: "Pan, Xinhui"
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Kefeng Wang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 5 +
1 file changed, 1
Use the helpers to simplify code.
Cc: Paul Moore
Cc: Stephen Smalley
Cc: Eric Paris
Acked-by: Paul Moore
Signed-off-by: Kefeng Wang
---
security/selinux/hooks.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
On 19.07.23 09:51, Kefeng Wang wrote:
Use the helpers to simplify code, also kill unneeded goto cpy_name.
Cc: Peter Zijlstra
Cc: Arnaldo Carvalho de Melo
Signed-off-by: Kefeng Wang
---
kernel/events/core.c | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff
[AMD Official Use Only - General]
The variable tmp_mask also could be removed.
Regards,
Bob
-Original Message-
From: amd-gfx On Behalf Of Victor Lu
Sent: Wednesday, July 19, 2023 3:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Skvortsov, Victor
; Lu, Victor Cheng Chi
[Why]
Current SR-IOV will not set GC to off state, while it is a real
GC hard reset. Whthout GFX off flag, driver may do gfxhub invalidation
before firmware load and gfxhub gart enable. This operation may cause
CP to become busy because GC is not in the right state for invalidation.
[How]
Add a
Fulfill the SMU13.0.7 support for Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
Fulfill the SMU13.0.0 support for Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 +
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +
To protect PMFW from being overloaded.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 31 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git
With WBRF feature supported, as a driver responding to the frequencies,
amdgpu driver is able to do shadow pstate switching to mitigate possible
interference(between its (G-)DDR memory clocks and local radio module
frequency bands used by Wifi 6/6e/7).
Signed-off-by: Evan Quan
Reviewed-by: Mario
Add those data structures to support Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
---
.../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 14 +-
.../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 14 +-
To support AMD's WBRF interference mitigation mechanism, Wifi adapters
utilized in the system must register the frequencies in use(or unregister
those frequencies no longer used) via the dedicated APCI calls. So that,
other drivers responding to the frequencies can take proper actions to
mitigate
The newly added WBRF feature needs this interface for channel
width calculation.
Signed-off-by: Evan Quan
---
include/net/cfg80211.h | 8
net/wireless/chan.c| 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index
AMD has introduced an ACPI based mechanism to support WBRF for some
platforms with AMD dGPU + WLAN. This needs support from BIOS equipped
with necessary AML implementations and dGPU firmwares.
For those systems without the ACPI mechanism and developing solutions,
user can use the generic WBRF
Due to electrical and mechanical constraints in certain platform designs
there may be likely interference of relatively high-powered harmonics of
the (G-)DDR memory clocks with local radio module frequency bands used
by Wifi 6/6e/7.
To mitigate this, AMD has introduced a mechanism that devices
Due to electrical and mechanical constraints in certain platform designs there
may
be likely interference of relatively high-powered harmonics of the (G-)DDR
memory
clocks with local radio module frequency bands used by Wifi 6/6e/7. To mitigate
possible RFI interference producers can advertise
[Public]
Looks good.
Reviewed-by: Guchun Chen
Regards,
Guchun
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Wednesday, July 19, 2023 1:20 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: Srinivasan Shanmugam partner.google.com>; SHANMUGAM,
[Public]
Reviewed-by: Guchun Chen
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Wednesday, July 19, 2023 1:29 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@lists.freedesktop.org
> Subject: [PATCH]
[Public]
Instead of converting all to functions, below improvement may be a bit more
simple. Can you please double check?
-#define amdgpu_display_vblank_get_counter(adev, crtc)
(adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
+#define amdgpu_display_vblank_get_counter(_adev, crtc) \
On 7/19/2023 1:34 AM, Limonciello, Mario wrote:
[Public]
[Public]
-Original Message-
From: Limonciello, Mario
Sent: Thursday, July 13, 2023 00:15
To: amd-gfx@lists.freedesktop.org
Cc: Limonciello, Mario
Subject: [PATCH] drm/amd: Fix an error handling mistake in psp_sw_init()
If
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