[AMD Official Use Only - General]
Looks good to me.
Series is:
Reviewed-by: Solomon Chiu
From: Yu, Lang
Sent: Monday, September 4, 2023 12:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Chiu, Solomon
; Yu, Lang ; kernel test robot
Subje
Instead of each implementation doing this more or less correctly
move taking the reset lock at a higher level.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5
The same PASID can be used by more than one VMID, reset each of them.
Use the common KIQ handling.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 66 --
1 file changed, 19 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID can be used by more than once VMID, build a mask of VMIDs
to reset instead of just restting the first one.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgp
For the PASID flushing we already handled that at a higher layer, apply
those workarounds to the standard flush as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 19 +++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 74 -
2 files change
That function never fails, drop the error return.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 7 +++
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 7 +++
The same PASID can be used by more than one VMID, reset each of them.
Use the common KIQ handling.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 63 --
1 file changed, 19 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
Move the SDMA workaround necessary for Navi 1x into a higher layer.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 48 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 3 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID can be used by more than once VMID, build a mask of VMIDs
to reset instead of just restting the first one.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgp
Testing for reset is pointless since the reset can start right after the
test.
The same PASID can be used by more than one VMID, reset each of them.
Move the KIQ and all the workaround handling into common GMC code.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c |
Remove leftovers from copying this from the gmc v10 code.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 108 ++---
1 file changed, 41 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgp
The KIQ code path was ignoring the second flush. Also avoid long lines and
re-calculating the register offsets over and over again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 29 +--
1 file changed, 18 insertions(+), 11 deletions(-)
diff -
Hi guys,
as discussed internally the MES and KFD needs some form of TLB fence
which signals when flushing VM updates out to the hardware is completed
and resources can be freed.
As prerequisite to this we need to rework all the different workarounds
and approaches around TLB flushing to be at a h
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time.
Question is why is that useful? Should we give users the ability to
control that?
I don't see an use case for this.
Regards,
C
Am 04.09.23 um 08:05 schrieb Ma Jun:
[1] Remove the irq flags setting code since pci_alloc_irq_vectors()
handles these flags.
[2] Free the msi vectors in case of error.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 43 ++---
1 file changed, 25 insert
Am 04.09.23 um 10:18 schrieb Yifan Zhang:
Use amdgpu_gmc_vram_pa to simplify codes.
Signed-off-by: Yifan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c| 3 +--
drivers/gpu/drm/amd/amdgpu/gfxhub_v3
[AMD Official Use Only - General]
The series is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Li, Candice
> Sent: Monday, September 4, 2023 3:20 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Li, Candice ; Zhou1, Tao
> Subject: [PATCH 3/3] drm/amdgpu: Add umc v12_0 ras functions
>
[AMD Official Use Only - General]
Reviewed-by: Asad Kamal asad.ka...@amd.com
Thanks & Regards
Asad
-Original Message-
From: amd-gfx On Behalf Of Lijo Lazar
Sent: Monday, September 4, 2023 6:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Kamal, Asad ; Zhang, H
pp_dpm_*clk nodes also could show the frequencies when a clock is in
'sleep' state. Add documentation related to that.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
On SMU v13.0.6, effective clocks are reported by FW which won't exactly
match with DPM level. Report the current clock based on the values
matching closest to the effective clock. Also, when deep sleep is
applied to a clock, report it with a special level "S:" as in sample
clock levels below
S: 19
For SMU v13.0.6, keep GFX deep sleep clock reporting style consistent
with that of other clocks. Sample format below.
S: 78Mhz *
0: 600Mhz
1: 800Mhz
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 10 ++
Restrict the wait for boot loader steady state only to SMUv13.0.6. For
older SOCs, ASIC init has a longer wait period and that takes care.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/
Am 03.09.23 um 08:52 schrieb Srinivasan Shanmugam:
Use min_t to replace min, min_t is a bit fast because min use
twice typeof.
Well that is probably negligibly.
The point is that using min_t is cleaner here since the min/max macros
do a typecheck while min_t()/max_t() to an explicit type cast
Am 03.09.23 um 08:05 schrieb Srinivasan Shanmugam:
This warning is for the declaration of a static array, and it is
recommended to declare it as type "static const char * const" instead of
"static const char *".
an array pointer declared as type "static const char *" can point to a
different cha
Use amdgpu_gmc_vram_pa to simplify codes.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c| 3 +--
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 +--
drivers/gpu
On Fri, 1 Sept 2023 at 21:00, Alex Deucher wrote:
>
> On Thu, Aug 31, 2023 at 6:01 PM Alex Hung wrote:
> >
> >
> >
> > On 2023-08-30 01:29, Jani Nikula wrote:
> > > On Tue, 29 Aug 2023, Alex Hung wrote:
> > >> On 2023-08-29 11:03, Jani Nikula wrote:
> > >>> On Tue, 29 Aug 2023, Jani Nikula wrot
[AMD Official Use Only - General]
Please split the change in amdgpu_device_indirect_rreg|wreg_ext to another
patch.
With above addressed, the series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Monday, September 4, 202
On Fri, 1 Sep 2023 16:41:25 -0700, Douglas Anderson wrote:
> Based on grepping through the source code, this driver appears to be
> missing a call to drm_atomic_helper_shutdown(), or in this case the
> non-atomic equivalent drm_helper_force_disable_all(), at system
> shutdown time and at driver rem
On 01/09/2023 07:02, Christian König wrote:
Am 31.08.23 um 20:55 schrieb Chia-I Wu:
On Thu, Aug 31, 2023 at 7:01 AM Greg KH
wrote:
On Thu, Aug 31, 2023 at 03:26:28PM +0200, Christian König wrote:
Am 31.08.23 um 12:56 schrieb Greg KH:
On Thu, Aug 31, 2023 at 12:27:27PM +0200, Christian König
Add umc v12_0 ras error querying.
Signed-off-by: Candice Li
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16 +-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 256 +
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
Add umc v12_0_0 ip headers.
Signed-off-by: Candice Li
Reviewed-by: Tao Zhou
---
.../include/asic_reg/umc/umc_12_0_0_offset.h | 33 +++
.../include/asic_reg/umc/umc_12_0_0_sh_mask.h | 95 +++
2 files changed, 128 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/
1. Add 64bits register access support on register whose address
is greater than 32bits.
2. Update RREG32_PCIE_EXT/WREG32_PCIE_EXT.
Signed-off-by: Candice Li
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 11 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 119 ++
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