[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Thursday, September 14, 2023 14:18
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
Subject: [PATCH] Revert "drm/amdgpu: Report vbios versi
[putting Harry on BCC, sorry for the noise]
Yeah, that is clearly a bug in the KFD.
During the second eviction the hw should already be disabled, so we
don't have any SDMA or similar to evict BOs any more and can only copy
them with the CPU.
@Felix what workqueue do you guys use for the rest
This reverts commit c187a67725b47f9c1603359a51b79cc19e27442a.
vbios_version sysfs node is used to identify Part Number also. Revert to
the same so that it doesn't break scripts/software which parse this.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +-
1 file c
On 09/13/ , Felix Kuehling wrote:
> On 2023-09-13 6:23, Lang Yu wrote:
> > On 09/12/ , Felix Kuehling wrote:
> > > On 2023-09-11 22:52, Lang Yu wrote:
> > > > On 09/11/ , Harish Kasiviswanathan wrote:
> > > > > Heavy-weight TLB flush is required after unmap on all GPUs for
> > > > > correctness and
[Public]
> -Original Message-
> From: Imre Deak
> Sent: Tuesday, September 12, 2023 7:19 PM
> To: Lin, Wayne
> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> ly...@redhat.com; jani.nik...@intel.com; ville.syrj...@linux.intel.com;
> Wentland, Harry ; Zuo, Jerry
>
>
There are multiple parts of the code that DC does not use anymore, and
this commit drops those dead codes.
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/bios/bios_parser2.c| 9 --
drivers/gpu/drm/amd/display/dc/link/Makefile | 4 +-
.../display/dc/link/accessories/link_fpga.c
From: Aric Cyr
This version brings along the following:
- Use optc32 instead of optc30 in DC
- Optimize OLED T7 delay
- Multiple fixes for MST, register mas, and others
- Update driver and IPS interop
- Improve z8 watermark mask
- DCN35 updates
- Enable replay for DCN35
- Temporarily disable clo
From: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f7e207efddb4..48021d196484 100644
--- a
From: Muhammad Ahmed
Enable DCN low mem power by default.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/displ
From: Muhammad Ahmed
Update with extended blank Vstartup adjustment for replay.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Muhammad Ahmed
---
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/driver
From: Ovidiu Bunea
Change DC to use optc32, which uses REG_UPDATE instead of REG_SET.
REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 for
FRL DSC.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Ovidiu Bunea
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn3
From: Agustin Gutierrez
[Why]
Driver doesn't need T7 delay for OLED panels, since it doesn't control
power sequence.
[How]
This delay can be skipped to optimize resume times.
Reviewed-by: Charlene Liu
Reviewed-by: Swapnil Patel
Acked-by: Rodrigo Siqueira
Signed-off-by: Agustin Gutierrez
---
From: Anthony Koo
- Add new IPS ALLOW masks
- Add new Replay power configuration options
Acked-by: Rodrigo Siqueira
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/displ
From: Charlene Liu
[why]
fix some non-initialized register mask and update goldn setting
Reviewed-by: Duncan Ma
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 8 +-
.../drm/amd/display/dc/dcn35/dcn35_hubbub.c | 8 +-
.../drm/amd/
From: Muhammad Ahmed
[What]
MST now recognizes both connected displays
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Muhammad Ahmed
---
.../gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c | 95 +++
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 4 -
2 files cha
From: Gabe Teeger
[Why & How]
Add a config option to disable odm dispclk optimization
for debug purpose.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Gabe Teeger
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/am
From: Roman Li
[Why]
DCN35 supports replay.
[How]
Setup replay config for dcn35 on device init.
Reviewed-by: Qingqing Zhuo
Acked-by: Qingqing Zhuo
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/dr
From: Muhammad Ahmed
Disable IPS by default till it is ready.
Reviewed-by: Duncan Ma
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/
From: Duncan Ma
[Why]
Two issues fixed:
1. Currently, driver does not allow idle prior to PSR entry. Once
PSR1+IPS is enabled, there is intermittent hang due to DCN access
from IrqMgr during IPS2.
2. Driver is sending multiple commands to PMFW and dmcub to exit IPS
even during IPS0.
[How
From: Sung Joon Kim
[why]
Currently, driver is not aware if IPS is supported. After PMFW helps
implement new message query functionality, driver will set IPS
capability flag.
[how]
Create new SMU hook function to query IPS capability. Based on the cap,
set appropriate flags to false for power-ga
From: Charlene Liu
Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35
dprefclk in clk_mgr_construct.
Reviewed-by: Muhammad Ahmed
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 2 --
.../gpu/drm/amd/display/dc/dcn
From: Artem Grishin
[Why]
The STREAM_MAPPER_CONTROL register offset was left uninitialized,
causing warning in the driver log at runtime
[How]
A temporary solution to add it into dcn35_create_resource_pool.
[TODO]
Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h
and SE_DCN35_
From: Sung Joon Kim
[Why & How]
Call to immediate_disable_crtc was not checked before calling,
exposing a potential null pointer hang. Fix it.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 4 +
From: Wenjing Liu
Pipe resource interfaces were changed.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
From: Mustapha Ghaddar
[HOW & WHY]
For DPIA we should have preferred DIG assignment based on DPIA
selected as per the ASIC design
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Mustapha Ghaddar
---
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 23 +++
1 fil
From: Sung-huai Wang
[Why & How]
set_static_screen_control has been updated for
DCN3 series. Update it for DCN35.
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off-by: Sung-huai Wang
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c | 2 +-
1 file changed, 1 insertion(+), 1 del
From: Qingqing Zhuo
Add DCN35 case for dc_clk_mgr_create.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_
From: Muhammad Ahmed
[Why]
pmfw ungate this feature, this can be enabled now
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/
From: Charlene Liu
Add z8 watermarks to struct for DCN35.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn35/dcn35_hubbub.c | 34 +++
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 3 +-
2 files changed, 36 insertio
From: Charlene Liu
Temporarily disable dchubbub clock gating, registers:
.DISPCLK_R_DCHUBBUB_GATE_DIS
.DCFCLK_R_DCHUBBUB_GATE_DIS
need to follow up with sequence issue.
Reviewed-by: Leo Chen
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_r
From: Duncan Ma
[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.
[How]
Fix stream encoder register define list.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Sig
From: Taimur Hassan
[Why & How]
To prevent confusion after symclk has already been disabled.
Reviewed-by: Meenakshikumar Somasundaram
Acked-by: Qingqing Zhuo
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c | 25 +++
1 file changed, 15 insertions
From: Muhammad Ahmed
Disable clock gating logic.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn3
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Use optc32 instead of optc30 in DC
- Optimize OLED T7 delay
- Multiple fixes for MST, register mas, and others
- Update driver and IPS interop
- Improve z8 watermark mask
- DCN35 updates
- Enable replay for DCN35
-
[AMD Official Use Only - General]
Chris,
I can dump these busy BOs with their alloc/free stack later today.
BTW, the two evictions and the kfd suspend are all called before hw_fini. IOW,
between phase 1 and phase 2. SDMA is turned only in phase2. So current code
works fine maybe.
From: Koenig,
On 9/13/23 10:43, Melissa Wen wrote:
Hi,
This is an update of previous RFC [0] improving the data collection of
Gamma Correction and Blend Gamma color blocks.
As I mentioned in the last version, I'm updating the color state part of
DTN log to match DCN3.0 HW better. Currently, the DTN log co
On 9/13/23 10:43, Melissa Wen wrote:
DCN3 DPP color state was uncollected and some state elements from DCN1
doesn't fit DCN3. Create new elements according to DCN3 color caps and
fill them up for DTN log output.
rfc-v2:
- fix reading of gamcor and blnd gamma states
Signed-off-by: Melissa Wen
On 9/13/23 10:43, Melissa Wen wrote:
Prepare to hook color state logging according to DCN version.
Signed-off-by: Melissa Wen
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 27 +--
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/disp
On Mon, Sep 04, 2023 at 06:58:20AM +, Lin, Wayne wrote:
> [Public]
>
> Thank you Lyude and Alex!
This patch had i915 changes, please also Cc the
intel-...@lists.freedesktop.org list for such patchsets, so that
we get CI test results for it.
Also, I think patches with i915 changes need an Ack
On 2023-09-11 10:04, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according to migration
granularity(default 2MB) and not split svm range in cpu page fault handling.
A svm range may include pages from both system ram and vram of one gpu now.
;>>> struct drm_dp_mst_topology_state *mst_state;
> >>>>> struct drm_dp_mst_topology_mgr *mst_mgr;
> >>>>> - struct drm_dp_mst_atomic_payload *new_payload, *old_payload;
> >>>>> + struct drm_dp_mst_atomic_payload *new_payload, old_payload;
> >>>>> enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
> >>>>> enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
> >>>>> int ret = 0;
> >>>>> @@ -365,8 +365,8 @@ bool dm_helpers_dp_mst_send_payload_allocation(
> >>>>> ret = drm_dp_add_payload_part2(mst_mgr,
> >>>>> mst_state->base.state, new_payload);
> >>>>> } else {
> >>>>> dm_helpers_construct_old_payload(stream->link,
> >>>>> mst_state->pbn_div,
> >>>>> - new_payload,
> >>>>> old_payload);
> >>>>> - drm_dp_remove_payload_part2(mst_mgr, mst_state,
> >>>>> old_payload, new_payload);
> >>>>> + new_payload,
> >>>>> &old_payload);
> >>>>> + drm_dp_remove_payload_part2(mst_mgr, mst_state,
> >>>>> &old_payload, new_payload);
> >>>>> }
> >>>>>
> >>>>> if (ret) {
> >>>>>
> >>>>> ---
> >>>>> base-commit: 8569c31545385195bdb0c021124e68336e91c693
> >>>>> change-id:
> >>>>> 20230913-fix-wuninitialized-dm_helpers_dp_mst_send_payload_allocation-c37b33aaad18
> >>>>>
> >>>>> Best regards,
> >>>> --
> >>>> Hamza
> >>>>
> >> --
> >> Hamza
> >>
> --
> Hamza
>
On Wed, Sep 13, 2023 at 3:31 AM Zhang, Hawking wrote:
>
> [AMD Official Use Only - General]
>
> Series is
>
> Reviewed-by: Hawking Zhang
>
> Regards,
> Hawking
> -Original Message-
> From: Lazar, Lijo
> Sent: Wednesday, September 13, 2023 13:58
> To: amd-gfx@lists.freedesktop.org
> Cc: Z
;
+ new_payload, &old_payload);
+ drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload,
new_payload);
}
if (ret) {
---
base-commit: 8569c31545385195bdb0c021124e68336e91c693
change-id:
20230913-fix-wuninitializ
dp_mst_atomic_payload *new_payload, old_payload;
> >>>enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
> >>>enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
> >>>int ret = 0;
> >>> @@ -365,8
ayload,
new_payload);
}
if (ret) {
---
base-commit: 8569c31545385195bdb0c021124e68336e91c693
change-id:
20230913-fix-wuninitialized-dm_helpers_dp_mst_send_payload_allocation-c37b33aaad18
Best regards,
--
Hamza
--
Hamza
struct_old_payload(stream->link,
> > mst_state->pbn_div,
> > - new_payload, old_payload);
> > - drm_dp_remove_payload_part2(mst_mgr, mst_state, old_payload,
> > new_payload);
> > + new_payload, &old_payload);
> > + drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload,
> > new_payload);
> > }
> >
> > if (ret) {
> >
> > ---
> > base-commit: 8569c31545385195bdb0c021124e68336e91c693
> > change-id:
> > 20230913-fix-wuninitialized-dm_helpers_dp_mst_send_payload_allocation-c37b33aaad18
> >
> > Best regards,
> --
> Hamza
>
Hi Dave, Daniel,
Fixes for 6.6.
The following changes since commit afaf2b38025ab327c85e218f36d1819e777d4d45:
Merge tag 'drm-misc-next-fixes-2023-09-11' of
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2023-09-11 16:23:42
+0200)
are available in the Git repository at:
https:/
On 2023-09-13 13:33, Philip Yang wrote:
On 2023-09-13 12:14, Felix Kuehling wrote:
On 2023-09-13 11:16, Philip Yang wrote:
If new range is added to update list, splited to multiple pranges with
max_svm_range_pages alignment, and svm validate and map returns error
for the first prange, then
On 2023-09-13 13:14, Mario Limonciello wrote:
Seamless boot can technically be supported as far back as DCN1
but to avoid regressions on older hardware, enable it for DCN3 and
later.
If users report using the module parameter that it works on older
ASICs as well, this can be adjusted.
Signed
On 2023-09-13 12:14, Felix Kuehling
wrote:
On
2023-09-13 11:16, Philip Yang wrote:
If new range is added to update list,
splited to multiple pranges with
max_svm_range_pages alignment, and svm validate and map returns
On 2023-09-13 12:14, Felix Kuehling
wrote:
On
2023-09-13 11:16, Philip Yang wrote:
If new range is added to update list,
splited to multiple pranges with
max_svm_range_pages alignment, and svm validate and map returns
Seamless boot can technically be supported as far back as DCN1
but to avoid regressions on older hardware, enable it for DCN3 and
later.
If users report using the module parameter that it works on older
ASICs as well, this can be adjusted.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/am
`amdgpu_gmc_get_vbios_allocations` has a special case for how to
bring up yellow carp when amdgpu discovery is turned off. As this ASIC
ships with discovery turned on, it's generally dead code and worse it
causes `adev->mman.keep_stolen_vga_memory` to not be initialized for
yellow carp.
Remove it.
The module parameter can be used to test more easily enabling seamless
boot support on additional ASICs.
Reviewed-by: Harry Wentland
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 +---
driv
Seamless boot allows keeping the content on the framebuffer from pre-boot
so the screen doesn't get "painted black" during boot process.
Ideally the flow looks like:
* UEFI F/W posts vendor logo
* GRUB doesn't show anything, but silently continues
* Plymouth starts and adds OS logo to bottom and s
This will allow base driver to dictate whether seamless should be
enabled. No intended functional changes.
Reviewed-by: Harry Wentland
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 21 +
r, mst_state, old_payload,
new_payload);
+new_payload, &old_payload);
+ drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload,
new_payload);
}
if (ret) {
---
base-commit: 8569c31545385195bdb0c021124e68336e91c693
change-id:
20230913-fix-wuninitia
Logging DCN3 MPC state was following DCN1 implementation that doesn't
consider new DCN3 MPC color blocks. Create new elements according to
DCN3 MPC color caps and a new DCN3-specific function for reading MPC
data.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 55
Add color caps information for DPP and MPC block to show HW color caps.
Signed-off-by: Melissa Wen
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 23 +++
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 23 +++
2 files changed, 46 insertions(+)
diff --git a/d
Color caps changed between HW versions which caused DCN10 color state
sections on DTN log no longer fit DCN3.0 versions. Create a
DCN3.0-specific color state logging and hook it to drivers of DCN3.0
family.
rfc-v2:
- detail RAM mode for gamcor and blnd gamma blocks
Signed-off-by: Melissa Wen
---
DCN3 DPP color state was uncollected and some state elements from DCN1
doesn't fit DCN3. Create new elements according to DCN3 color caps and
fill them up for DTN log output.
rfc-v2:
- fix reading of gamcor and blnd gamma states
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/dcn30/dc
Hi,
This is an update of previous RFC [0] improving the data collection of
Gamma Correction and Blend Gamma color blocks.
As I mentioned in the last version, I'm updating the color state part of
DTN log to match DCN3.0 HW better. Currently, the DTN log considers the
DCN10 color pipeline, which is
Prepare to hook color state logging according to DCN version.
Signed-off-by: Melissa Wen
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 27 +--
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers
yload);
}
if (ret) {
---
base-commit: 8569c31545385195bdb0c021124e68336e91c693
change-id:
20230913-fix-wuninitialized-dm_helpers_dp_mst_send_payload_allocation-c37b33aaad18
Best regards,
--
Hamza
On 2023-09-13 11:16, Philip Yang wrote:
If new range is added to update list, splited to multiple pranges with
max_svm_range_pages alignment, and svm validate and map returns error
for the first prange, then the caller retry should add pranges with
prange->is_error_flag or prange without prange->
+ drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload,
new_payload);
}
if (ret) {
---
base-commit: 8569c31545385195bdb0c021124e68336e91c693
change-id:
20230913-fix-wuninitialized-dm_helpers_dp_mst_send_payload_allocation-c37b33aaad18
Best regards,
--
Nathan Chancellor
On 2023-09-05 16:13, Mario Limonciello wrote:
On 9/5/2023 15:07, Deucher, Alexander wrote:
[Public]
-Original Message-
From: amd-gfx On Behalf Of Mario
Limonciello
Sent: Tuesday, September 5, 2023 3:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Limonciello, Mario
Subject: [PATCH 4/4
If new range is added to update list, splited to multiple pranges with
max_svm_range_pages alignment, and svm validate and map returns error
for the first prange, then the caller retry should add pranges with
prange->is_error_flag or prange without prange->mapped_to_gpu to the
update list, to updat
On 11/09/23 03:46, Matthew Auld wrote:
On 09/09/2023 17:09, Arunpravin Paneer Selvam wrote:
Problem statement: The current method roundup_power_of_two()
to allocate contiguous address triggers -ENOSPC in some cases
even though we have enough free spaces and so to help with
that we introduce a
[+Harry]
Am 13.09.23 um 15:54 schrieb Felix Kuehling:
On 2023-09-13 4:07, Christian König wrote:
[+Fleix]
Well that looks like quite a serious bug.
If I'm not completely mistaken the KFD work item tries to restore the
process by moving BOs into memory even after the suspend freeze.
Normally
On 2023-09-12 21:52, Jonathan Kim wrote:
There are cases where HSA runtime is not enabled through the
AMDKFD_IOC_RUNTIME_ENABLE call when adding queues and the MES ADD_QUEUE
API should clear the MES process context instead of SET_SHADER_DEBUGGER.
Such examples are legacy HSA runtime builds that d
On 2023-09-13 4:07, Christian König wrote:
[+Fleix]
Well that looks like quite a serious bug.
If I'm not completely mistaken the KFD work item tries to restore the
process by moving BOs into memory even after the suspend freeze.
Normally work items are frozen together with the user space proc
On 2023-09-13 6:23, Lang Yu wrote:
On 09/12/ , Felix Kuehling wrote:
On 2023-09-11 22:52, Lang Yu wrote:
On 09/11/ , Harish Kasiviswanathan wrote:
Heavy-weight TLB flush is required after unmap on all GPUs for
correctness and security.
Signed-off-by: Harish Kasiviswanathan
---
drivers/gpu/
On 09/12/ , Felix Kuehling wrote:
> On 2023-09-11 22:52, Lang Yu wrote:
> > On 09/11/ , Harish Kasiviswanathan wrote:
> > > Heavy-weight TLB flush is required after unmap on all GPUs for
> > > correctness and security.
> > >
> > > Signed-off-by: Harish Kasiviswanathan
> > > ---
> > > drivers/gpu
On 09/12/ , Alex Deucher wrote:
> Add missing IP discovery info.
>
> Signed-off-by: Alex Deucher
Reviewed-by: Lang Yu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/a
v1:
implement smu_v13_0_6 mca bank interface.
v2:
- remove unnecessary lock
- move MCMP1_* macros to mp_13_0_6_sh_mask.h file
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
---
.../include/asic_reg/mp/mp_13_0_6_sh_mask.h | 28 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 515 +
update smu header to support mca dump interface.
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
---
.../inc/pmfw_if/smu13_driver_if_v13_0_6.h | 88 +++
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 4 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 6 +-
.../drm/
add amdgpu mca debug sysfs support.
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 116
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +
3 files changed, 120 insertions(+
add amdgpu smu mca dump feature support.
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 68 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h | 57 +
2 files changed, 125 insertions(+)
diff --git a/drivers/g
Am 12.09.23 um 23:28 schrieb Alex Deucher:
Add missing IP discovery info.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/dr
Am 11.09.23 um 21:00 schrieb Harish Kasiviswanathan:
Heavy-weight TLB flush is required after unmap on all GPUs for
correctness and security.
Signed-off-by: Harish Kasiviswanathan
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +--
1 file changed, 1 insertion(+)
[+Fleix]
Well that looks like quite a serious bug.
If I'm not completely mistaken the KFD work item tries to restore the
process by moving BOs into memory even after the suspend freeze.
Normally work items are frozen together with the user space processes
unless explicitly marked as not freez
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, September 13, 2023 13:58
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Olsak, Marek ; Deucher,
Alexander
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