This reverts commit b5abd7f983e14054593dc91d6df2aa5f8cc67652.
This change breaks DSC on 4k monitors at 144Hz over USB-C.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3254
Signed-off-by: Alex Deucher
Cc: Muhammad Ahmed
Cc: Tom Chung
Cc: Charlene Liu
Cc: Hamza Mahfooz
Cc: Harry Went
Hi,
On Fri, Mar 29, 2024 at 10:28:14AM -0700, Easwar Hariharan wrote:
> On 3/29/2024 10:16 AM, Andi Shyti wrote:
> > Hi Easwar,
> >
> > On Fri, Mar 29, 2024 at 05:00:26PM +, Easwar Hariharan wrote:
> >> I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave"
> >
> > I don't un
Hi Easwar,
On Fri, Mar 29, 2024 at 05:00:26PM +, Easwar Hariharan wrote:
> I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave"
I don't understand why we forget that i3c is 1.1.1 :-)
> with more appropriate terms. Inspired by and following on to Wolfram's
> series to fix dr
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Srinivasan Shanmugam
[ Upstream commit eb4f139888f636614dab3bcce97ff61cefc4b3a7 ]
This ensures that the memory mapped by ioremap for adev->rmmio, is
properly handled in amdgpu_device_init(). If the function exits early
due to an error, the memory is unmapped. If the function completes
succ
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Srinivasan Shanmugam
[ Upstream commit eb4f139888f636614dab3bcce97ff61cefc4b3a7 ]
This ensures that the memory mapped by ioremap for adev->rmmio, is
properly handled in amdgpu_device_init(). If the function exits early
due to an error, the memory is unmapped. If the function completes
succ
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Aric Cyr
[ Upstream commit 14d68acfd04b39f34eea7bea65dda652e6db5bf6 ]
[Why]
Nanosec stats can overflow on long running systems potentially causing
statistic logging issues.
[How]
Use 64bit types for nanosec stats to ensure no overflow.
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Whe
From: Srinivasan Shanmugam
[ Upstream commit eb4f139888f636614dab3bcce97ff61cefc4b3a7 ]
This ensures that the memory mapped by ioremap for adev->rmmio, is
properly handled in amdgpu_device_init(). If the function exits early
due to an error, the memory is unmapped. If the function completes
succ
From: Nicholas Kazlauskas
[ Upstream commit 6226a5aa77370329e01ee8abe50a95e60618ce97 ]
[Why]
Workaroud for a race condition where DMCUB is in the process of
committing to IPS1 during the handshake causing us to miss the
transition into IPS2 and touch the INBOX1 RPTR causing a HW hang.
[How]
Dis
From: Alvin Lee
[ Upstream commit fc9f47455ae143e8831415a46eab3fbc69e408aa ]
[Why & How]
For FPO and SubVP/DRR cases we need to ensure to program
OTG_V_TOTAL_MIN/MAX_SEL, otherwise stretching the vblank
in FPO / SubVP / DRR cases will not have any effect
and we could hit underflow / corruption.
From: Sohaib Nadeem
[ Upstream commit d46fb0068c54d3dc95ae8298299c4d9edb0fb7c1 ]
[why]
Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
requirement will still be satisfied. Increasing min DCFCLK ad
From: "Stanley.Yang"
[ Upstream commit 601429cca96b4af3be44172c3b64e4228515dbe1 ]
Why:
The PCI error slot reset maybe triggered after inject ue to UMC multi
times, this
caused system hang.
[ 557.371857] amdgpu :af:00.0: amdgpu: GPU reset succeeded, trying to
resume
[ 557.
The include guard should match the filename, or it will conflict with
the newly-added asm/fpu.h.
Signed-off-by: Samuel Holland
---
Changes in v4:
- New patch for v4
arch/x86/include/asm/fpu/types.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/
Now that CC_FLAGS_FPU is exported and can be used anywhere in the source
tree, use it instead of duplicating the flags here.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- New patch for v2
arch/arm64/lib/Makefile | 6 ++
1 file ch
On Fri, 15 Mar 2024 13:09:56 -0400
wrote:
> From: Leo Li
>
> These patches aim to make the amdgpgu KMS driver play nicer with compositors
> when building multi-plane scanout configurations. They do so by:
>
> 1. Making cursor behavior more sensible.
> 2. Allowing placement of DRM OVERLAY plane
Now that all previously-supported architectures select
ARCH_HAS_KERNEL_FPU_SUPPORT, this code can depend on that symbol instead
of the existing list of architectures. It can also take advantage of the
common kernel-mode FPU API and method of adjusting CFLAGS.
Acked-by: Alex Deucher
Reviewed-by: C
This series unifies the kernel-mode FPU API across several architectures
by wrapping the existing functions (where needed) in consistently-named
functions placed in a consistent header location, with mostly the same
semantics: they can be called from preemptible or non-preemptible task
context, and
Hi,
On 15.03.24 18:09, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).
Each DCN pipe has the ability to blend in a cursor early on in
On Fri, 15 Mar 2024 13:09:57 -0400
wrote:
> From: Leo Li
>
> [Why]
>
> DCN is the display hardware for amdgpu. DRM planes are backed by DCN
> hardware pipes, which carry pixel data from one end (memory), to the
> other (output encoder).
>
> Each DCN pipe has the ability to blend in a cursor e
From: Michael Ellerman
The compiler flags enable altivec, but that is not required; hard-float
is sufficient for the code to build and function.
Drop altivec from the compiler flags and adjust the enable/disable code
to only enable FPU use.
Signed-off-by: Michael Ellerman
Acked-by: Alex Deuche
Now that CC_FLAGS_FPU is exported and can be used anywhere in the source
tree, use it instead of duplicating the flags here.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
Changes in v4:
- Add missed CFLAGS changes for recov_neon_inner.c
(fixes arm build failures)
lib/ra
This is motivated by the amdgpu DRM driver, which needs floating-point
code to support recent hardware. That code is not performance-critical,
so only provide a minimal non-preemptible implementation for now.
Support is limited to riscv64 because riscv32 requires runtime (libgcc)
assistance to con
LoongArch already provides kernel_fpu_begin() and kernel_fpu_end() in
asm/fpu.h, so it only needs to add kernel_fpu_available() and export
the CFLAGS adjustments.
Acked-by: WANG Xuerui
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v3)
Changes in v3:
- Reb
x86 already provides kernel_fpu_begin() and kernel_fpu_end(), but in a
different header. Add a wrapper header, and export the CFLAGS
adjustments as found in lib/Makefile.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/x86/Kconfig | 1 +
Now that ARCH_HAS_KERNEL_FPU_SUPPORT provides a common way to compile
and run floating-point code, this test is no longer x86-specific.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v1)
lib/Kconfig.debug | 2 +-
lib/Makefile| 25 ++--
ARM provides an equivalent to the common kernel-mode FPU API, but in a
different header and using different function names. Add a wrapper
header, and export CFLAGS adjustments as found in lib/raid6/Makefile.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v2)
On Fri, 15 Mar 2024 13:09:58 -0400
wrote:
> From: Leo Li
>
> [Why]
>
> Compositors have different ways of assigning surfaces to DRM planes for
> render offloading. It may decide between various strategies: overlay,
> underlay, or a mix of both
>
> One way for compositors to implement the unde
This ensures no compiler-generated floating-point code can appear
outside kernel_fpu_{begin,end}() sections, and some architectures
enforce this separation.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Declare test_fpu() in a header
Several architectures provide an API to enable the FPU and run
floating-point SIMD code in kernel space. However, the function names,
header locations, and semantics are inconsistent across architectures,
and FPU support may be gated behind other Kconfig options.
Provide a standard way for archite
Now that CC_FLAGS_FPU is exported and can be used anywhere in the source
tree, use it instead of duplicating the flags here.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/arm/lib/Makefile | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
di
PowerPC provides an equivalent to the common kernel-mode FPU API, but in
a different header and using different function names. The PowerPC API
also requires a non-preemptible context. Add a wrapper header, and
export the CFLAGS adjustments.
Acked-by: Michael Ellerman (powerpc)
Reviewed-by: Chris
arm64 provides an equivalent to the common kernel-mode FPU API, but in a
different header and using different function names. Add a wrapper
header, and export CFLAGS adjustments as found in lib/raid6/Makefile.
Reviewed-by: Christoph Hellwig
Signed-off-by: Samuel Holland
---
(no changes since v2
Am 29.03.24 um 12:10 schrieb Christian König:
Am 25.03.24 um 08:45 schrieb Jesse Zhang:
remove the unsed the paramter in the function
ttm_bo_bounce_temp_buffer and ttm_bo_add_move_fence.
Signed-off-by: Jesse Zhang
Good catch, Reviewed-by: Christian König
Please rebase that patch on top of
Am 25.03.24 um 08:45 schrieb Jesse Zhang:
remove the unsed the paramter in the function
ttm_bo_bounce_temp_buffer and ttm_bo_add_move_fence.
Signed-off-by: Jesse Zhang
Good catch, Reviewed-by: Christian König
Regards,
Christian.
---
drivers/gpu/drm/ttm/ttm_bo.c | 10 --
1 file
Am 25.03.24 um 06:35 schrieb Lang Yu:
drm sched is stopped and SDMA mode is not available,
while CPU mode worked well in such a case.
Use case,
amdgpu_do_asic_reset
amdgpu_device_ip_late_init
umsch_mm_late_init
umsch_mm_test
amdgpu_vm_init
Well big NAK to that.
The VM updates should just be s
From: Basavaraj Natikar
Various MP2 register sets are supported by newer processors. Therefore,
extend MP2 register access to SFH.
Signed-off-by: Basavaraj Natikar
(cherry picked from commit 92e38c2b7ea7c7ef77a55cce3c312b9377761990)
---
drivers/hid/amd-sfh-hid/amd_sfh_common.h | 14 +
From: Basavaraj Natikar
AMD SFH load takes longer time in initialization. Hence split and defer
initialization code to improve SFH module load time and boot time of the
system when SFH is available.
Signed-off-by: Basavaraj Natikar
(cherry picked from commit 4bd00ad0eabb67239ea833b8c461bf697035
From: Basavaraj Natikar
HP ProBook x360 435 G7 using older version of firmware which doesn't
support disabling the interrupt for all commands. Hence avoid disabling
the interrupt for that particular model.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=218104
Fixes: b300667b33b2 ("HID: amd_sf
From: Basavaraj Natikar
HPD sensor data is not populating properly because of wrong order of HPD
sensor structure elements. So update the order of structure elements to
match the HPD sensor data received from the firmware.
Fixes: 24a31ea94922 ("HID: amd_sfh: Add initial support for HPD sensor")
From: Basavaraj Natikar
During the initialization sensors may take some time to respond. Hence,
increase the sensor command timeouts in order to obtain status responses
within a maximum timeout.
Co-developed-by: Akshata MukundShetty
Signed-off-by: Akshata MukundShetty
Signed-off-by: Basavaraj
From: Basavaraj Natikar
AMDSFH has information about the Ambient light via the Ambient
Light Sensor (ALS) which is part of the AMD sensor fusion hub.
Add a new interface to export this information, where other drivers like
PMF can use this information to enhance user experiences.
Link:
https:/
From: Basavaraj Natikar
AMDSFH has information about the User presence information via the Human
Presence Detection (HPD) sensor which is part of the AMD sensor fusion hub.
Add a new interface to export this information, where other drivers like
PMF can use this information to enhance user exper
From: Basavaraj Natikar
[Backport]: to fix amd_sfh init fail issue in ASDN
Current amd_sfh driver has float_to_int() to convert units from
float to int. This is fine until this function gets called outside of
the current scope of file.
Add a prefix "amd_sfh" to float_to_int() so that function r
ASD is not needed by headless GPU.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 94b310fdb719d..063203865bbe2 100644
--- a/
refactor the code of runtime pm mode detection to support
amdgpu_runtime_pm =2 and 1 two cases
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 68 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 48 +---
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Candice Li
> Sent: Wednesday, March 27, 2024 2:16 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Li, Candice
> Subject: [PATCH] drm/amdgpu: Update EEPROM RAS table for mismatched table
> version
>
> Update
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Zhou1, Tao
Sent: Friday, March 29, 2024 11:10
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2
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