On Mon, 22 Apr 2024 16:47:36 +0200
Christian König wrote:
> Am 22.04.24 um 16:40 schrieb Alex Deucher:
> > On Mon, Apr 22, 2024 at 9:00 AM Christian König
> > wrote:
> >> Am 22.04.24 um 14:33 schrieb Qiang Ma:
> >>> On Mon, 22 Apr 2024 11:40:26 +0200
> >>> Christian König wrote:
> >>>
> >
Now we have two flags for contiguous VRAM buffer allocation.
If the application request for AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
it would set the ttm place TTM_PL_FLAG_CONTIGUOUS flag in the
buffer's placement function.
This patch will change the default behaviour of the two flags.
When we set AMDG
After amdgpu_i2c_get_byte fail, amdgpu_i2c_put_byte shouldn't be
conducted to put wrong value.
So return and check the i2c transfer result.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 42 +++--
1 file changed, 26 insertions(+), 16 deletions(-)
diff
[AMD Official Use Only - General]
Reviewed-by: Le Ma
Thanks for catching. Please populate the fix to sdma_v4_4_2 as well if
necessary.
> -Original Message-
> From: Bob Zhou
> Sent: Tuesday, April 23, 2024 5:15 PM
> To: amd-gfx@lists.freedesktop.org; Ma, Le
> Cc: Deucher, Alexander ;
Am 24.04.24 um 03:19 schrieb Jesse Zhang:
Fix some variables not initialized before use.
Scan them out using Synopsys tools.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +
drivers/gpu/drm/amd/amdgpu/atom.c
Am 24.04.24 um 04:04 schrieb Zhang, Jesse(Jie):
[AMD Official Use Only - General]
Hi Alex,
-Original Message-
From: Alex Deucher
Sent: Wednesday, April 24, 2024 9:46 AM
To: Zhang, Jesse(Jie)
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Koenig,
Christian ; Huang, Tim
Subje
Am 24.04.24 um 04:50 schrieb jesse.zh...@amd.com:
From: Jesse Zhang
Initialize the size before calling amdgpu_vce_cs_reloc, such as case 0x0301.
Signed-off-by: Jesse Zhang
To really improve the handling we would actually need to have a separate
value of 0x.
Regards,
Christian
Am 24.04.24 um 09:13 schrieb Arunpravin Paneer Selvam:
Now we have two flags for contiguous VRAM buffer allocation.
If the application request for AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
it would set the ttm place TTM_PL_FLAG_CONTIGUOUS flag in the
buffer's placement function.
This patch will change
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Disable seamless boot on 128b/132b encoding
- Change ASSR disable sequence to avoid corruption
- Fix few IPS problems
- Enable Replay for DCN315
- Fix few ODM problems
- Fix FEC_READY write timing
- Fix few FPO pr
From: Harry Wentland
Cursors are always programmed independently of updates on other
planes. When atomic commits program cursor and surface updates
together the cursor update might be locked out by the surface
update and not take effect.
To combat this program cursor and surface updates together
From: Harry Wentland
Some IGT tests fail with the new atomic cursor updates
when running on older DCE-based ASICs. To work around
these issues keep calling the amdgpu_dm_commit_cursors
for each cursor update on DCE, even if those cursor
updates coincide with other plane updates.
Reviewed-by: Agu
From: Hersen Wu
[Why & How]
Check return pointer of kzalloc before using it.
Reviewed-by: Alex Hung
Acked-by: Wayne Lin
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 8
.../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 8
From: Alex Hung
[WHAT]
msg_id is used as an array index and it cannot be a negative value, and
therefore cannot be equal to MOD_HDCP_MESSAGE_ID_INVALID (-1).
[HOW]
Check whether msg_id is valid before reading and setting.
This fixes 4 OVERRUN issues reported by Coverity.
Reviewed-by: Rodrigo S
From: Alex Hung
pipe_ctx has a size of MAX_PIPES so checking its index before accessing
the array.
This fixes an OVERRUN issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
.../drm/amd/display/dc/irq/dce110/irq_service_dce110.c| 8 +
Am 24.04.24 um 09:52 schrieb Bob Zhou:
After amdgpu_i2c_get_byte fail, amdgpu_i2c_put_byte shouldn't be
conducted to put wrong value.
So return and check the i2c transfer result.
Signed-off-by: Bob Zhou
Looks good in general, just some coding style comments below.
---
drivers/gpu/drm/amd/
From: Alex Hung
[WHY]
ENGINE_ID_UNKNOWN = -1 and can not be used as an array index. Plus, it
also means it is uninitialized and does not need free audio.
[HOW]
Skip and return NULL.
This fixes 2 OVERRUN issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Wayne Lin
Signed-off
From: Hersen Wu
[WHY]
&mode_lib->mp.Watermark and &locals->Watermark are
the same address. memcpy may lead to unexpected behavior.
[HOW]
memmove should be used.
Reviewed-by: Rodrigo Siqueira
Acked-by: Wayne Lin
Reviewed-by: Alex Hung
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display
From: Alex Hung
[WHY]
resource_stream_to_stream_idx returns an array index and it return -1
when not found; however, -1 is not a valid array index number.
[HOW]
When this happens, call ASSERT(), and return a zero instead.
This fixes an OVERRUN and an NEGATIVE_RETURNS issues reported by Coverity
From: Alex Hung
[WHY]
find_disp_cfg_idx_by_plane_id and find_disp_cfg_idx_by_stream_id returns
an array index and they return -1 when not found; however, -1 is not a
valid index number.
[HOW]
When this happens, call ASSERT(), and return a positive number (which is
fewer than callers' array size)
[Why & How]
We accidentally upstream unnecessary files. Remove them.
Reviewed-by: Tom Chung
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dpp/dcn10/CMakeLists.txt | 6 --
drivers/gpu/drm/amd/display/dc/dpp/dcn20/CMakeLists.txt | 5 -
drivers/gpu/drm/amd/display/dc/
From: Rodrigo Siqueira
Add REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write for
the regama lut.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
From: Rodrigo Siqueira
This commit add PP_SMU_VER_VG to the pp_smu_ver list.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/d
From: Rodrigo Siqueira
This commit just update the code style in two if conditions and in an
static array.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 8
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 2 +-
2
From: Rodrigo Siqueira
Add VCO speed parameters in the bounding box array.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
b
Initialize the size before calling amdgpu_vce_cs_reloc, such as case 0x0301.
V2: To really improve the handling we would actually
need to have a separate value of 0x.(Christian)
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 2 +-
1 file changed, 1 inser
From: Rodrigo Siqueira
Add dcn301_fpu prefix to some of the FPU function with the required
adjustments.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dml/dcn301/dcn301_fpu.c| 4 ++--
.../amd/display/dc/dml/dcn301/dcn301_fpu.h| 7 +++
.../dc/resource/
Am 24.04.24 um 10:41 schrieb Jesse Zhang:
Initialize the size before calling amdgpu_vce_cs_reloc, such as case 0x0301.
V2: To really improve the handling we would actually
need to have a separate value of 0x.(Christian)
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgp
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Disable seamless boot on 128b/132b encoding
- Change ASSR disable sequence to avoid corruption
- Fix few IPS problems
- Enable Replay for DCN315
- Fix few ODM problems
- Fix FEC_READY write timing
- Fix few FPO pr
From: Harry Wentland
Cursors are always programmed independently of updates on other
planes. When atomic commits program cursor and surface updates
together the cursor update might be locked out by the surface
update and not take effect.
To combat this program cursor and surface updates together
From: Harry Wentland
Some IGT tests fail with the new atomic cursor updates
when running on older DCE-based ASICs. To work around
these issues keep calling the amdgpu_dm_commit_cursors
for each cursor update on DCE, even if those cursor
updates coincide with other plane updates.
Reviewed-by: Agu
From: Hersen Wu
[Why & How]
Check return pointer of kzalloc before using it.
Reviewed-by: Alex Hung
Acked-by: Wayne Lin
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 8
.../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 8
From: Alex Hung
[WHAT]
msg_id is used as an array index and it cannot be a negative value, and
therefore cannot be equal to MOD_HDCP_MESSAGE_ID_INVALID (-1).
[HOW]
Check whether msg_id is valid before reading and setting.
This fixes 4 OVERRUN issues reported by Coverity.
Reviewed-by: Rodrigo S
From: Alex Hung
pipe_ctx has a size of MAX_PIPES so checking its index before accessing
the array.
This fixes an OVERRUN issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
.../drm/amd/display/dc/irq/dce110/irq_service_dce110.c| 8 +
From: Alex Hung
[WHY]
ENGINE_ID_UNKNOWN = -1 and can not be used as an array index. Plus, it
also means it is uninitialized and does not need free audio.
[HOW]
Skip and return NULL.
This fixes 2 OVERRUN issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Wayne Lin
Signed-off
From: Hersen Wu
[WHY]
&mode_lib->mp.Watermark and &locals->Watermark are
the same address. memcpy may lead to unexpected behavior.
[HOW]
memmove should be used.
Reviewed-by: Rodrigo Siqueira
Acked-by: Wayne Lin
Reviewed-by: Alex Hung
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display
From: Alex Hung
[WHY]
resource_stream_to_stream_idx returns an array index and it return -1
when not found; however, -1 is not a valid array index number.
[HOW]
When this happens, call ASSERT(), and return a zero instead.
This fixes an OVERRUN and an NEGATIVE_RETURNS issues reported by Coverity
From: Alex Hung
[WHY]
find_disp_cfg_idx_by_plane_id and find_disp_cfg_idx_by_stream_id returns
an array index and they return -1 when not found; however, -1 is not a
valid index number.
[HOW]
When this happens, call ASSERT(), and return a positive number (which is
fewer than callers' array size)
[Why & How]
We accidentally upstream unnecessary files. Remove them.
Reviewed-by: Tom Chung
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dpp/dcn10/CMakeLists.txt | 6 --
drivers/gpu/drm/amd/display/dc/dpp/dcn20/CMakeLists.txt | 5 -
drivers/gpu/drm/amd/display/dc/
From: Rodrigo Siqueira
Add REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write for
the regama lut.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
From: Rodrigo Siqueira
This commit add PP_SMU_VER_VG to the pp_smu_ver list.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/d
From: Rodrigo Siqueira
This commit just update the code style in two if conditions and in an
static array.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 8
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 2 +-
2
From: Rodrigo Siqueira
Add VCO speed parameters in the bounding box array.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
b
From: Rodrigo Siqueira
Add dcn301_fpu prefix to some of the FPU function with the required
adjustments.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dml/dcn301/dcn301_fpu.c| 4 ++--
.../amd/display/dc/dml/dcn301/dcn301_fpu.h| 7 +++
.../dc/resource/
From: Rodrigo Siqueira
Set up to enable legacy fast update.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resour
From: Rodrigo Siqueira
Adjust to update some of the dcn303 parameters.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/resource/dcn303/dcn303_resource.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/r
From: Rodrigo Siqueira
This commit just remove some trivial legacy code in some of the DC
files.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 12
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 6 --
..
From: Rodrigo Siqueira
Set up to enable log color state for multiple DCNs.
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c | 1 +
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c | 1 +
drivers/gpu/drm/amd/display/dc/hws
From: Rodrigo Siqueira
Add code to handle case when quad_part is 0 in gpu_addr_to_uma().
Acked-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss
From: Dennis Chan
[why]
To refine for link off frame count in diagnose tool,
the driver show the link off frame count number instead of showing link
off frame count level.
Reviewed-by: ChunTao Tso
Reviewed-by: Robin Chen
Acked-by: Wayne Lin
Signed-off-by: Dennis Chan
---
drivers/gpu/drm/amd
From: Iswara Nagulendran
[HOW&WHY]
In multi-monitor cases the VBLANK stretch that is required to align both
monitors may be so large that it may create issues for gaming performance.
Use debug value to restrict in-game FAMS support for multi-disp use case.
Reviewed-by: Harry Vanzylldejong
Acke
From: Wayne Lin
[Why]
Like commit ec5fa9fcdeca ("drm/amd/display: Adjust the MST resume flow"), we
want to avoid handling mst topology changes before restoring the old state.
If we enable DP_UP_REQ_EN before calling drm_atomic_helper_resume(), have
changce to handle CSN event first and fire hotpl
From: Leo Ma
[Why && How]
Screen flickering saw on 4K@60 eDP with high refresh rate external
monitor when booting up in DC mode. DC Mode Capping is disabled
which caused wrong UCLK being used.
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Leo Ma
---
.../amd/display/dc/clk_mgr/dcn
From: Wenjing Liu
[why]
DSC slice must be divisible by ODM slice count.
[how]
If DSC slice count is not a multiple of ODM slice count, increase DSC
slice until it is. Otherwise fail to compute DSC configuration.
Reviewed-by: Chaitanya Dhere
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
From: Roman Li
[Why]
IPS stability was fixed in bios.
[How]
Set disable_ips init flag to DMUB_IPS_ENABLE.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Nicholas Kazlauskas
[Why]
FIFO error can occur if we don't trigger a DISPCLK change after
touching K1/K2 dividers. For 4k144 eDP + hotplug of USB-C DP display
we see FIFO underflow.
[How]
We have the path to trigger the resync as the workaround in
DCN314/DCN32, it just needs to be ported o
From: Daniel Miess
[Why & How]
Enable root clock optimization for PHYSYMCLK and only
disable it when it's actively being used
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/dcn35/d
From: Webb Chen
This reverts commit f7131558f362 ("drm/amd/display: Keep VBios pixel rate div
setting util next mode set") which causes issue.
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Webb Chen
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 --
.../drm/amd/display
From: Alex Hung
This fixes 1 PW.INCLUDE_RECURSION reported by Coverity.
"./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h"
includes itself: dc_types.h -> dal_types.h -> dc_types.h
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/include/dal_types.h | 1 -
1 f
From: Alvin Lee
[Description]
Today for MED update type we do not call update clocks. However, for FPO
the assumption is that update clocks should be called to disable P-State
switch before any HW programming since FPO in FW and driver are not
synchronized. This causes an issue where on a MED upd
From: Revalla Hari Krishna
[why]
cleaning up the code refactor requires hubbub to be in its own component.
[how]
Move all files under newly created hubbub folder and fix the makefiles.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/
From: Alvin Lee
[Description]
Assign linear_pitch_alignment so we don't cause a divide by 0
error in VM environments
Reviewed-by: Sohaib Nadeem
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/driver
From: Nevenko Stupar
[Why & How]
Currently in DML2.1 gpuvm_enable was hardcoded.
Use passed info from DC for DML21 to be in sync with
what is used in DC.
Reviewed-by: Chaitanya Dhere
Acked-by: Wayne Lin
Signed-off-by: Nevenko Stupar
---
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
From: Alvin Lee
[Description]
For FPO + Vactive scenarios we must check that all non-FPO pipes
have VACTIVE margin to allow it. The previous check only confirmed
that there is at least one pipe that has vactive margin, but this
is incorrect as the vactive display could be using two pipes (MPO)
wh
From: Alex Hung
This fixes 11 UNINIT issues reported by Coverity.
Reviewed-by: Hersen Wu
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 ++--
2 files change
From: Alex Hung
This fixes 49 UNINIT issues reported by Coverity.
Reviewed-by: Hersen Wu
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
.../gpu/drm/amd/display/dc/core/dc_resource.c| 2 +-
drivers/gpu/drm/amd/display/dc/dcn30
From: Ilya Bakoulin
[Why/How]
We can miss writing FEC_READY in some cases before LT start, which
violates DP spec. Remove the condition guarding the DPCD write so that
the write happens unconditionally.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Wenjing Liu
From: Wenjing Liu
[why]
When optc uses two pixel per container, each ODM slice width must be an
even number.
[how]
If ODM slice width is odd number increase it by 1.
Reviewed-by: Dillon Varone
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c |
From: Joan Lee
[why & how]
Enable Replay for DCN315.
Reviewed-by: Robin Chen
Acked-by: Wayne Lin
Signed-off-by: Joan Lee
---
.../amd/display/dc/resource/dcn315/dcn315_resource.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/d
From: Nicholas Kazlauskas
[Why]
We can hang in IPS2 checking DMCUB_SCRATCH0 for link detection state.
[How]
Replace the HW access with a check on the shared state bit. This will
work the same way as the SCRATCH0 but won't require a wake in the case
where link detection isn't required.
Reviewed-
From: Roman Li
[Why]
HPD interrupt cannot be handled in IPS2 state.
So if there's a display topology change while system in IPS2
it can be missed.
[How]
Implement worker to check each 5 sec in IPS for HPD.
Reviewed-by: Hamza Mahfooz
Acked-by: Wayne Lin
Signed-off-by: Roman Li
---
.../gpu/dr
From: Swapnil Patel
[Why]
Currently disabling ASSR before stream is disabled causes visible
display corruption.
[How]
Move disable ASSR command to after stream has been disabled.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Wenjing Liu
Acked-by: Wayne Lin
S
From: Alex Hung
This fixes 29 UNINIT issues reported by Coverity.
Reviewed-by: Hersen Wu
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +-
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 2 +-
drivers/gpu/dr
From: Sung Joon Kim
[why]
preOS will not support display mode programming and link training
for UHBR rates.
[how]
If we detect a sink that's UHBR capable, disable seamless boot
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/
From: Aric Cyr
This version brings along following fixes:
- Disable seamless boot on 128b/132b encoding
- Have cursor and surface updates together
- Change ASSR disable sequence to avoid corruption
- Fix few IPS problems
- Enable Replay for DCN315
- Fix few ODM problems
- Fix FEC_READY write timi
Initialize the size before calling amdgpu_vce_cs_reloc, such as case 0x0301.
V2: To really improve the handling we would actually
need to have a separate value of 0x.(Christian)
Signed-off-by: Jesse Zhang
Suggested-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |
Am 24.04.24 um 11:04 schrieb Jesse Zhang:
Initialize the size before calling amdgpu_vce_cs_reloc, such as case 0x0301.
V2: To really improve the handling we would actually
need to have a separate value of 0x.(Christian)
Signed-off-by: Jesse Zhang
Suggested-by: Christian König
After amdgpu_i2c_get_byte fail, amdgpu_i2c_put_byte shouldn't be
conducted to put wrong value.
So return and check the i2c transfer result.
Signed-off-by: Bob Zhou
Suggested-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 47 +++--
1 file changed, 28 insert
Am 24.04.24 um 11:36 schrieb Bob Zhou:
After amdgpu_i2c_get_byte fail, amdgpu_i2c_put_byte shouldn't be
conducted to put wrong value.
So return and check the i2c transfer result.
Signed-off-by: Bob Zhou
Suggested-by: Christian König
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/a
Assign value to clock to fix the warning below:
"Using uninitialized value res. Field res.clock is uninitialized"
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
b/d
Initialize the interrupt timestamp for some legacy SOCs
to fix the coverity issue "Uninitialized scalar variable"
Signed-off-by: Ma Jun
Suggested-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgp
Initialize the phy_id to 0 to fix the warning of
"Using uninitialized value phy_id"
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
b/drivers/gpu/drm
Am 24.04.24 um 12:03 schrieb Ma Jun:
Initialize the interrupt timestamp for some legacy SOCs
to fix the coverity issue "Uninitialized scalar variable"
Signed-off-by: Ma Jun
Suggested-by: Christian König
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 8 +++
Am 24.04.24 um 13:41 schrieb Dan Carpenter:
These lines are indented too far. Clean the whitespace.
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
[Public]
> We have the KFD, FLR, the per engine one in the scheduler and IIRC one more
> for the CP (illegal operation and register write).
>
> I'm not sure about the CP one, but all others should be handled correctly
> with the V2 patch as far as I can see.
Where can I find the CP one? Nothing
Am 24.04.24 um 15:20 schrieb Dan Carpenter:
On Wed, Apr 24, 2024 at 03:11:08PM +0200, Christian König wrote:
Am 24.04.24 um 13:41 schrieb Dan Carpenter:
These lines are indented too far. Clean the whitespace.
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++
On 2024-04-23 18:15, Felix Kuehling
wrote:
On
2024-04-23 11:28, Philip Yang wrote:
If the BO pages pinned for RDMA is not
contiguous on VRAM, evict it to
system memory first to free the VRAM space, then allocate
co
[Public]
> -Original Message-
> From: Wayne Lin
> Sent: Wednesday, April 24, 2024 4:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry ; Li, Sun peng (Leo)
> ; Siqueira, Rodrigo ;
> Pillai, Aurabindo ; Li, Roman
> ; Lin, Wayne ; Gutierrez,
> Agustin ; Chung, ChiaHsuan (Tom)
>
On 2024-04-23 18:17, Felix Kuehling
wrote:
On 2024-04-23 11:28, Philip Yang wrote:
RDMA device with limited scatter-gather
ability requires contiguous VRAM
buffer allocation for RDMA peer direct support.
Am 23.04.24 um 16:31 schrieb Tim Huang:
From: Tim Huang
Clear warning that uses uninitialized value fw_size.
Signed-off-by: Tim Huang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/
Define macro AMDGPU_MAX_SG_SEGMENT_SIZE 2GB, because struct scatterlist
length is unsigned int, and some users of it cast to a signed int, so
every segment of sg table is limited to size 2GB maximum.
For contiguous VRAM allocation, don't limit the max buddy block size in
order to get contiguous VR
This patch series implement new KFD memory alloc flag for best effort contiguous
VRAM allocation, to support peer direct access RDMA device with limited
scatter-gather
dma capability.
v2: rebase on patch ("drm/amdgpu: Modify the contiguous flags behaviour")
to avoid adding the new GEM flag
v
When TTM failed to alloc VRAM, TTM try evict BOs from VRAM to system
memory then retry the allocation, this skips the KFD BOs from the same
process because KFD require all BOs are resident for user queues.
If TTM with TTM_PL_FLAG_CONTIGUOUS flag to alloc contiguous VRAM, allow
TTM evict KFD BOs fr
RDMA device with limited scatter-gather ability requires contiguous VRAM
buffer allocation for RDMA peer direct support.
Add a new KFD alloc memory flag and store as bo alloc flag
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS. When pin this bo to export for RDMA
peerdirect access, this will set TTM_PL_FLAG_CO
Bump the kfd ioctl minor version to delcare the contiguous VRAM
allocation flag support.
Signed-off-by: Philip Yang
---
include/uapi/linux/kfd_ioctl.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index d09c4
If the BO pages pinned for RDMA is not contiguous on VRAM, evict it to
system memory first to free the VRAM space, then allocate contiguous
VRAM space, and then move it from system memory back to VRAM.
v6: user context should use interruptible call (Felix)
Signed-off-by: Philip Yang
---
.../gpu
On 4/23/2024 7:13 AM, Srinivasan Shanmugam wrote:
> The buffer size is determined by the declaration char fw_name[30]; This
> means fw_name can hold up to 30 characters, including the null character
> that marks the end of the string.
>
> The string to be written is "amdgpu/%s_mec.bin" or "amdg
lower */
if (divider < DFS_DIVIDER_RANGE_2_START) {
---
base-commit: d60dc4dd72412d5d9566fdf391e4202b05f88912
change-id: 20240424-amdgpu-display-dcn401-enum-float-conversion-c09cc1826ea2
Best regards,
--
Nathan Chancellor
The series is
Reviewed-by: Felix Kuehling
On 2024-04-24 11:27, Philip Yang wrote:
This patch series implement new KFD memory alloc flag for best effort contiguous
VRAM allocation, to support peer direct access RDMA device with limited
scatter-gather
dma capability.
v2: rebase on patch ("drm/
For now, they are only used internally inside TTM, but this will change
with the introduction of dynamic buffer priorities.
Signed-off-by: Friedrich Vock
---
drivers/gpu/drm/ttm/ttm_bo.c | 168 ++-
include/drm/ttm/ttm_bo.h | 6 ++
2 files changed, 172 insert
Make each buffer object aware of whether it has been evicted or not.
Signed-off-by: Friedrich Vock
---
drivers/gpu/drm/ttm/ttm_bo.c | 1 +
include/drm/ttm/ttm_bo.h | 11 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
i
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