RE: [v5 1/4] drm/amdgpu: Refactor VCN v5.0.1 HW init into separate instance function

[AMD Official Use Only - AMD Internal Distribution Only] Ping this series. > -Original Message- > From: Jesse.Zhang > Sent: Monday, September 15, 2025 10:09 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Liu, Leo ; Jiang, Sonny > ; Zhang, Jesse(J

RE: [PATCH 2/2] amd/amdkfd: drain kfd process workquque before switch partition

[Public] Hi Yifan, Please wrap the KFD sequences in an API inside amdkfd/. XCP will only make use of the API and doesn't want to deal with KFD internals. Thanks, Lijo -Original Message- From: amd-gfx On Behalf Of Yifan Zhang Sent: Wednesday, September 17, 2025 9:09 AM To: amd-gfx@list

[PATCH 1/2] amd/amdkfd: resolve a race in amdgpu_amdkfd_device_fini_sw

There is race in amdgpu_amdkfd_device_fini_sw and interrupt. if amdgpu_amdkfd_device_fini_sw run in b/w kfd_cleanup_nodes and kfree(kfd), and KGD interrupt generated. kernel panic log: BUG: kernel NULL pointer dereference, address: 0098 amdgpu :c8:00.0: amdgpu: Requesting 4 part

[PATCH 11/20] drm/amd/display: Isolate dcn401 SMU functions

From: Dillon Varone [WHY&HOW] SMU interfaces are not backwards and forwards compatible, so they should be isolated per version. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski --- .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 26 ++-- .../clk_mgr/dcn401/dcn4

Re: [PATCH V11 06/47] drm/colorop: Add 1D Curve subtype

On 8/26/25 03:03, Pekka Paalanen wrote: On Thu, 21 Aug 2025 11:54:32 -0600 Alex Hung wrote: On 8/21/25 06:23, Xaver Hugl wrote: We user space folks have been convinced at this point that the sRGB EOTF is actually gamma 2.2, and not the piece-wise function. Now, if the hardware is actually

[PATCH 2/2] amd/amdkfd: drain kfd process workquque before switch partition

to resolve the race [3966658.307702] divide error: [#1] SMP NOPTI [3966658.350818] i10nm_edac [3966658.356318] CPU: 124 PID: 38435 Comm: kworker/124:0 Kdump: loaded Tainted [3966658.356890] Workqueue: kfd_process_wq kfd_process_wq_release [amdgpu] [3966658.362839] nfit [3966658.366457] RIP:

Re: [PATCH V11 11/47] drm/colorop: Introduce DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE

On 9/15/25 12:43, Nícolas F. R. A. Prado wrote: On Thu, 2025-08-14 at 21:50 -0600, Alex Hung wrote: From: Harry Wentland With the introduction of the pre-blending color pipeline we can no longer have color operations that don't have a clear position in the color pipeline. We deprecate all e

Re: [PATCH V11 13/47] drm/colorop: Add destroy functions for color pipeline

On 9/5/25 11:12, Louis Chauvet wrote: Le 15/08/2025 à 05:50, Alex Hung a écrit : The functions are to clean up color pipeline when a device driver fails to create its color pipeline. Signed-off-by: Alex Hung Reviewed-by: Daniel Stone Reviewed-by: Simon Ser Reviewed-by: Melissa Wen ---

RE: [PATCH 2/2] drm/amdgpu: Check VF critical region before RAS poison injection

[AMD Official Use Only - AMD Internal Distribution Only] The series looks good. Reviewed-by: Shravan Kumar Gande mailto:shravankumar.ga...@amd.com>> Thanks, Shravan _ From: Zhang, Hawking Sent: Tuesday, August 19, 2025 1:50 AM To: Liu, Xiang(Dean)

RE: [PATCH 1/2] drm/amdgpu: Introduce VF critical region check for RAS poison injection

[AMD Official Use Only - AMD Internal Distribution Only] The series looks good. Reviewed-by: Shravan Kumar Gande Thanks, Shravan -Original Message- From: Yang, Stanley Sent: Tuesday, September 16, 2025 2:50 AM To: Liu, Xiang(Dean) ; amd-gfx@lists.freedesktop.org; Skvortsov, Victor ;

[PATCH 12/20] drm/amd/display: Refactor SMU tracing

From: Dillon Varone [WHY&HOW] Add new tracing and performance measurements for SMU messaging. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 4 ++-- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.

[PATCH] drm/amdkfd: Fix mmap write lock not release

If mmap write lock is taken while draining retry fault, mmap write lock is not released because svm_range_restore_pages calls mmap_read_unlock then returns. This causes deadlock and systen hang later because mmap read or write lock cannot be taken. Downgrade mmap write lock to read lock if drainin

[PATCH 16/20] drm/amd/display: Correct sw cache timing to ensure dispclk ramping

From: Charlene Liu [why] Current driver will cache the dispclk right after send cmd to pmfw, but actual clock not reached yet. Change to only cache the dispclk setting after HW reached to the real clock. Also give some range as it might be in bypass clock setting. Reviewed-by: Yihan Zhu Signed

[PATCH 09/20] drm/amd/display: Use mpc.preblend flag to indicate preblend

From: Alvin Lee [Description] Modifications in per asic capability means mpc.preblend flag should be used to indicate preblend. Update relevant paths to use this flag. Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Ivan Lipski --- drivers/gpu/drm/amd/display/amdgpu_dm/amd

[PATCH v2] drm/amd: Run KFD/userq suspend and resume routines for s0ix

KFD suspend and resume routines have been disabled since commit 5d3a2d95224da ("drm/amdgpu: skip kfd suspend/resume for S0ix") which made sense at that time. However there is a problem that if there is any compute work running there may still be active fences. Running suspend without draining the

[PATCH 10/20] drm/amd/display: Add fast sync field in ultra sleep more for DMUB

From: Allen Li [Why&How] We need to inform DMUB whether fast sync in ultra sleep mode is supported, so that it can disable desync error detection when the it is not enabled. This helps prevent unexpected desync errors when transitioning out of ultra sleep mode. Add fast sync in ultra sleep mode

[PATCH 06/20] drm/amd/display: Init dispclk from bootup clock for DCN314

From: Lo-an Chen [Why] Driver does not pick up and save vbios's clocks during init clocks, the dispclk in clk_mgr will keep 0 until the first update clocks. In some cases, OS changes the timing in the second set mode (lower the pixel clock), causing the driver to lower the dispclk in prepare band

Re: [PATCH] drm/amd: Only restore cached manual clock settings in restore if OD enabled

On Mon, Sep 15, 2025 at 10:39 PM Mario Limonciello wrote: > > If OD is not enabled then restoring cached clock settings doesn't make > sense and actually leads to errors in resume. > > Check if enabled before restoring settings. > > Fixes: 796ff8a7e01bd ("drm/amd: Restore cached manual clock setti

Re: [PATCH v2] drm/amd: Run KFD/userq suspend and resume routines for s0ix

On Tue, Sep 16, 2025 at 9:39 AM Mario Limonciello wrote: > > KFD suspend and resume routines have been disabled since commit > 5d3a2d95224da ("drm/amdgpu: skip kfd suspend/resume for S0ix") which > made sense at that time. However there is a problem that if there is > any compute work running the

[PATCH 00/20] DC Patches September 15, 2025

From: Ivan Lipski This DC patchset brings improvements in multiple areas. In summary, we highlight: - Disable stutter when programming watermarks on dcn32 - Improve brightness calculations - Fix saving vbios clocks during init for DCN314 - Enable DTM 3 on DCN3.1+ dGPUs - Add

[PATCH 17/20] drm/amd/display: Revert "correct sw cache timing to ensure dispclk ramping"

From: Charlene Liu [why] Need consider SSC enabled case This reverts commit b0552a6de4727ffe9604b662d90bcdbc866af16f. Reviewed-by: Ovidiu (Ovi) Bunea Reviewed-by: Chris Park Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski --- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 30 ++

[PATCH 18/20] drm/amd/display: Init DCN35 clocks from pre-os HW values

From: Leo Li [Why] We did not initialize dc clocks with boot-time hw values during init. This lead to incorrect clock values in dc, causing `dcn35_update_clocks` to make incorrect updates. [How] Correctly initialize DC with pre-os clk values from HW. s/dump/save/ as that accurately reflects the

[PATCH 19/20] drm/amd/display: [FW Promotion] Release 0.1.28.0

From: Taimur Hassan Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/

[PATCH 13/20] drm/amd/display: Set wm_pending when disable stutter w/a used

From: Dillon Varone [WHY&HOW] When stutter is disabled prior to watermark programming due to a w/a, wm_pending should be returned as true. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aurabindo Pillai Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski --- drivers/gpu/drm/amd/display/d

[PATCH 01/20] drm/amd/display: Disable stutter when programming watermarks on dcn32

From: Dillon Varone [WHY&HOW] Reprogramming watermarks with stutter allowed can cause instability on some ASICs. Disable it prior to raising watermarks (prepare bandwidth), then re-enable after lowering (optimize bandwidth). Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Iv

[PATCH 07/20] drm/amd/display: Enable DTM v3 on dGPUs with DCN 3.1+

From: Ivan Lipski [Why&How] Right now, only selected APUs have enabled DTM v3, which allows to use newer firmware for content protection. We want to enable it on the dGPUs starting with DCN 3.2 Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski --- .../gpu/drm/amd/display/amdgpu_dm/amd

[PATCH 02/20] drm/amd/display: Add missing post flip calls

From: Dillon Varone [WHY&HOW] dc_post_update_surfaces_to_stream needs to be called after a full update completes in order to optimize clocks and watermarks for power. Add missing calls before idle entry is requested to ensure optimal power. Reviewed-by: Aurabindo Pillai Signed-off-by: Dillon Va

[PATCH 03/20] drm/amd/display: Add AVI infoframe copy in copy_stream_update_to_stream

From: Karthi Kandasamy [WHY] Ensure AVI infoframe updates from stream updates are applied to the active stream so OS overrides are not lost. [HOW] Copy avi_infopacket to stream when valid flag is set. Follow existing infopacket copy pattern and perform a basic validity check before assignment.

Re: [PATCH v2 00/11] PCI: Resizable BAR improvements

On Mon, Sep 15, 2025 at 08:24:06PM +0300, Ilpo Järvinen wrote: On Mon, 15 Sep 2025, Lucas De Marchi wrote: On Mon, Sep 15, 2025 at 12:13:47PM +0300, Ilpo Järvinen wrote: > pci.c has been used as catch everything that doesn't fits elsewhere > within PCI core and thus resizable BAR code has been

Re: [PATCH v3 3/6] drm/amd/pm: Allow system metrics table in 1vf mode

[AMD Official Use Only - AMD Internal Distribution Only] Series is Reviewed-by: Yang Wang 获取 Outlook for iOS 发件人: Kamal, Asad 发送时间: Tuesday, September 16, 2025 5:05:24 PM 收件人: amd-gfx@lists.freedesktop.org ; Lazar, Lijo 抄送: Zhang, Hawkin

Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits

On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote: > On Thu, Sep 11, 2025 at 2:18 PM Alex Deucher > wrote: > > > > On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher > > wrote: > > > > > > SDMA 5.2.x has increased transfer limits. > > > > > > v2: fix harder, use shifts to make it more obvious >

[PATCH v3 3/6] drm/amd/pm: Allow system metrics table in 1vf mode

Allow fetching system metrics table in 1VF mode Signed-off-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu

Re: [RFC v8 04/12] drm/sched: Consolidate entity run queue management

On Thu, 2025-09-11 at 15:55 +0100, Tvrtko Ursulin wrote: > > On 11/09/2025 15:20, Philipp Stanner wrote: > > On Wed, 2025-09-03 at 11:18 +0100, Tvrtko Ursulin wrote: > > > Move the code dealing with entities entering and exiting run queues to > > > helpers to logically separate it from jobs enteri

[PATCH AUTOSEL 6.16] amd/amdkfd: correct mem limit calculation for small APUs

From: Yifan Zhang [ Upstream commit 53503556273a5ead8b75534085e2dcb46e96f883 ] Current mem limit check leaks some GTT memory (reserved_for_pt reserved_for_ras + adev->vram_pin_size) for small APUs. Since carveout VRAM is tunable on APUs, there are three case regarding the carveout VRAM size rel

[PATCH AUTOSEL 6.16] drm/amdkfd: fix p2p links bug in topology

From: Eric Huang [ Upstream commit ce42a3b581a9db10765eb835840b04dbe7972135 ] When creating p2p links, KFD needs to check XGMI link with two conditions, hive_id and is_sharing_enabled, but it is missing to check is_sharing_enabled, so add it to fix the error. Signed-off-by: Eric Huang Acked-by

Re: [PATCH] drm/amd: Run KFD suspend and resume routines for s0ix

On Mon, Sep 15, 2025 at 9:20 PM Mario Limonciello wrote: > > KFD suspend and resume routines have been disabled since commit > 5d3a2d95224da ("drm/amdgpu: skip kfd suspend/resume for S0ix") which > made sense at that time. However there is a problem that if there is > any compute work running the

[PATCH] drm/amdgpu: Use kmalloc_array() instead of kmalloc()

Documentation/process/deprecated.rst recommends against the use of kmalloc with dynamic size calculations due to the risk of overflow and smaller allocation being made than the caller was expecting. Replace kmalloc() with kmalloc_array() in amdgpu_amdkfd_gfx_v10.c to make the intended allocation s

Re: [PATCH v1 1/2] drm/amdgpu: make non-NULL out fence mandatory

On 16.09.25 13:58, Pierre-Eric Pelloux-Prayer wrote: > > > Le 16/09/2025 à 12:52, Christian König a écrit : >> On 16.09.25 11:46, Pierre-Eric Pelloux-Prayer wrote: >>> >>> >>> Le 16/09/2025 à 11:25, Christian König a écrit : On 16.09.25 09:08, Pierre-Eric Pelloux-Prayer wrote: > amdgpu_t

Re: [PATCH v1 1/2] drm/amdgpu: make non-NULL out fence mandatory

Le 16/09/2025 à 12:52, Christian König a écrit : On 16.09.25 11:46, Pierre-Eric Pelloux-Prayer wrote: Le 16/09/2025 à 11:25, Christian König a écrit : On 16.09.25 09:08, Pierre-Eric Pelloux-Prayer wrote: amdgpu_ttm_copy_mem_to_mem has a single caller, make sure the out fence is non-NULL t

Re: [PATCH v1 1/2] drm/amdgpu: make non-NULL out fence mandatory

On 16.09.25 11:46, Pierre-Eric Pelloux-Prayer wrote: > > > Le 16/09/2025 à 11:25, Christian König a écrit : >> On 16.09.25 09:08, Pierre-Eric Pelloux-Prayer wrote: >>> amdgpu_ttm_copy_mem_to_mem has a single caller, make sure the out >>> fence is non-NULL to simplify the code. >>> Since none of t

Re: [PATCH v1 1/2] drm/amdgpu: make non-NULL out fence mandatory

On 16.09.25 09:08, Pierre-Eric Pelloux-Prayer wrote: > amdgpu_ttm_copy_mem_to_mem has a single caller, make sure the out > fence is non-NULL to simplify the code. > Since none of the pointers should be NULL, we can enable > __attribute__((nonnull))__. > > While at it make the function static since

Re: [PATCH v2 06/11] drm/i915/gt: Use pci_rebar_size_supported()

On 16.09.25 10:12, Jani Nikula wrote: > On Mon, 15 Sep 2025, Rodrigo Vivi wrote: >> On Mon, Sep 15, 2025 at 07:24:10PM +0200, Andi Shyti wrote: >>> Hi, >>> >>> On Mon, Sep 15, 2025 at 03:42:23PM +0300, Jani Nikula wrote: On Mon, 15 Sep 2025, Ilpo Järvinen wrote: > PCI core provides pci_r

Re: [PATCH v1 1/2] drm/amdgpu: make non-NULL out fence mandatory

Le 16/09/2025 à 11:25, Christian König a écrit : On 16.09.25 09:08, Pierre-Eric Pelloux-Prayer wrote: amdgpu_ttm_copy_mem_to_mem has a single caller, make sure the out fence is non-NULL to simplify the code. Since none of the pointers should be NULL, we can enable __attribute__((nonnull))__.

RE: [PATCH v3 6/6] drm/amd/pm: Enable npm metrics data

[AMD Official Use Only - AMD Internal Distribution Only] -Original Message- From: Kamal, Asad Sent: Tuesday, September 16, 2025 2:35 PM To: amd-gfx@lists.freedesktop.org; Lazar, Lijo Cc: Zhang, Hawking ; Ma, Le ; Zhang, Morris ; Kamal, Asad ; Deucher, Alexander ; Wang, Yang(Kevin) Su

RE: [PATCH v3 5/6] drm/amd/pm: Fetch npm data from system metrics table

[Public] -Original Message- From: Kamal, Asad Sent: Tuesday, September 16, 2025 2:35 PM To: amd-gfx@lists.freedesktop.org; Lazar, Lijo Cc: Zhang, Hawking ; Ma, Le ; Zhang, Morris ; Kamal, Asad ; Deucher, Alexander ; Wang, Yang(Kevin) Subject: [PATCH v3 5/6] drm/amd/pm: Fetch npm data

[PATCH V3] drm/amdgpu: Convert amdgpu userqueue management from IDR to XArray

This commit refactors the AMDGPU userqueue management subsystem to replace IDR (ID Allocation) with XArray for improved performance, scalability, and maintainability. The changes address several issues with the previous IDR implementation and provide better locking semantics. Key changes: 1. **Gl

Re: [PATCH v1 2/2] drm/amdgpu: remove gart_window_lock usage from gmc v12

On 16.09.25 09:08, Pierre-Eric Pelloux-Prayer wrote: > This lock was part of the SDMA workaround originally implemented in > gmc_v10_0_flush_gpu_tlb (a70cb2176f7ef6f moved it to > amdgpu_gmc_flush_gpu_tlb). > > This means this lock is useless and be safely dropped. > > Signed-off-by: Pierre-Er

[PATCH v3 1/6] drm/amd/pm: Rename amdgpu_hwmon_get_sensor_generic

Rename amdgpu_hwmon_get_sensor_generic to use for generic pm interfaces Signed-off-by: Asad Kamal --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 76 +++--- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/

[PATCH v3 6/6] drm/amd/pm: Enable npm metrics data

Enable npm metrics data for smu_v13_0_12 v3: Add node id check for setting NPM_CAPS (Lijo) Signed-off-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_pp

[PATCH v3 4/6] drm/amd/pm: Add sysfs node for node power

Add sysfs node to expose node power limit for smu_v13_0_12 v2: Remove support check from visible function (Kevin) v3: Update comments (Kevin) Remove sysfs remove file, change format specifier for sysfs_emit, use attribute_group.name (Lijo) Signed-off-by: Asad Kamal --- .../gpu/drm/amd/

[PATCH v3 5/6] drm/amd/pm: Fetch npm data from system metrics table

Fetch npm data from system metrics table for smu_v13_0_12 v3: Remove intermittent type for npm data, remove node id check, move npm caps check to npm_get_data function (Lijo) Signed-off-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 48 +++ .../drm/amd/pm/sws

[PATCH v3 2/6] drm/amd/pm: Update pmfw headers for smu_v13_0_12

Update pmfw headers for smu_v13_0_12 to include node power limit Signed-off-by: Asad Kamal --- .../drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h b/dr

Re: [RFC v8 04/12] drm/sched: Consolidate entity run queue management

On 16/09/2025 08:41, Philipp Stanner wrote: On Thu, 2025-09-11 at 15:55 +0100, Tvrtko Ursulin wrote: On 11/09/2025 15:20, Philipp Stanner wrote: On Wed, 2025-09-03 at 11:18 +0100, Tvrtko Ursulin wrote: Move the code dealing with entities entering and exiting run queues to helpers to logical

[PATCH v3] drm/amdgpu: Add fallback to pipe reset if KCQ ring reset fails

From: Lijo Lazar Add a fallback mechanism to attempt pipe reset when KCQ reset fails to recover the ring. After performing the KCQ reset and queue remapping, test the ring functionality. If the ring test fails, initiate a pipe reset as an additional recovery step. v2: fix the typo (Lijo) v3: try

RE: [PATCH 1/2] drm/amdgpu: Introduce VF critical region check for RAS poison injection

[AMD Official Use Only - AMD Internal Distribution Only] The series looks good to me, but still need @Skvortsov, Victor or @Gande, Shravan kumar to review. Regards, Stanley > -Original Message- > From: Liu, Xiang(Dean) > Sent: Tuesday, August 19, 2025 1:26 PM > To: amd-gfx@lists.freedes

Re: [PATCH v2 05/11] PCI: Add pci_rebar_size_supported() helper

On Mon, 15 Sep 2025, Andi Shyti wrote: > Hi Ilpo, > >> +/** >> + * pci_rebar_size_supported - check if size is supported for BAR >> + * @pdev: PCI device >> + * @bar: BAR to check >> + * @size: size as defined in the PCIe spec (0=1MB, 31=128TB) >> + * >> + * Return: %true if @bar is resizable and

Re: [PATCH v2 06/11] drm/i915/gt: Use pci_rebar_size_supported()

On Mon, 15 Sep 2025, Rodrigo Vivi wrote: > On Mon, Sep 15, 2025 at 07:24:10PM +0200, Andi Shyti wrote: >> Hi, >> >> On Mon, Sep 15, 2025 at 03:42:23PM +0300, Jani Nikula wrote: >> > On Mon, 15 Sep 2025, Ilpo Järvinen wrote: >> > > PCI core provides pci_rebar_size_supported() that helps in checki

Re: [PATCH v2 00/11] PCI: Resizable BAR improvements

On Mon, 15 Sep 2025, Lucas De Marchi wrote: > On Mon, Sep 15, 2025 at 12:13:47PM +0300, Ilpo Järvinen wrote: > > pci.c has been used as catch everything that doesn't fits elsewhere > > within PCI core and thus resizable BAR code has been placed there as > > well. Move Resizable BAR related code to

Re: [REGRESSION] AMD GPU not detected since 6.16.4 commit c97636cc83d4

On 2025-09-15 15:04, Mario Limonciello wrote: It makes sense.  Can you send out a properly formatted patch to the M/L with all the tags (Fixes/Closes/S-o-b)?  Or if you want me to use yours to write one and send one out (and give you a Suggested-by) I can do that too. Please send it, I'll l

Re: [PATCH V11 11/47] drm/colorop: Introduce DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE

On Thu, 2025-08-14 at 21:50 -0600, Alex Hung wrote: > From: Harry Wentland > > With the introduction of the pre-blending color pipeline we > can no longer have color operations that don't have a clear > position in the color pipeline. We deprecate all existing > plane properties. For upstream dri

[PATCH v1 1/2] drm/amdgpu: make non-NULL out fence mandatory

amdgpu_ttm_copy_mem_to_mem has a single caller, make sure the out fence is non-NULL to simplify the code. Since none of the pointers should be NULL, we can enable __attribute__((nonnull))__. While at it make the function static since it's only used from amdgpuu_ttm.c. Signed-off-by: Pierre-Eric P

RE: [PATCH V2] drm/amdgpu: Add fallback to pipe reset if KCQ ring reset fails

[Public] -Original Message- From: Jesse.Zhang Sent: Tuesday, September 16, 2025 11:54 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian ; Lazar, Lijo ; Zhang, Jesse(Jie) Subject: [PATCH V2] drm/amdgpu: Add fallback to pipe reset if KCQ ring reset fails F

[PATCH v1 2/2] drm/amdgpu: remove gart_window_lock usage from gmc v12

This lock was part of the SDMA workaround originally implemented in gmc_v10_0_flush_gpu_tlb (a70cb2176f7ef6f moved it to amdgpu_gmc_flush_gpu_tlb). This means this lock is useless and be safely dropped. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 --