during LT fixes
- Null point filters
- [FW Promotion] Release 0.0.108.0
Acked-by: Agustin Gutierrez
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
From: Charlene Liu
[why]
DCN31 has this in zstate save/restore sequence.
need for non_zstate supported ASIC
[how]
add this PANEL_PWRSEQ_REF_DIV2 to existing panel_cntl_hw_init structure.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Agustin Gutierrez
Signed-off-by: Charlene Liu
---
.../amd
-by: Agustin Gutierrez
Signed-off-by: Becle Lee
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 15 +++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 4
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 15 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
From: Jing Zhou
[Why & How]
Add null pointer filter for logical integrity.
Reviewed-by: Charlene Liu
Acked-by: Agustin Gutierrez
Signed-off-by: Jing Zhou
---
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/dri
treat lanes status as previous one and repeat LT steps again.
Reviewed-by: Wenjing Liu
Acked-by: Agustin Gutierrez
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 30 ---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm
From: Dale Zhao
[Why]
We must support a new type of partial edid return in the future
[How]
Add interface and case hander for partial edid
Reviewed-by: Charlene Liu
Acked-by: Agustin Gutierrez
Signed-off-by: Dale Zhao
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
drivers/gpu
, so we disable both.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Nevenko Stupar
Acked-by: Agustin Gutierrez
Signed-off-by: Eric Yang
---
.../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Jing Zhou
[Why]
Crash caused by a ddc update failure
[How]
Update engine ddc before release engine.
Reviewed-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez
Signed-off-by: Jing Zhou
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
1 file changed, 1 insertion
ewed-by: Rodrigo Siqueira
Acked-by: Agustin Gutierrez
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/dis
From: "Leo (Hanghong) Ma"
[Why]
We need a helper function in dc to grab the pipe from the stream
context.
[How]
Add it.
Reviewed-by: Martin Leung
Acked-by: Agustin Gutierrez
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 +
From: "JinZe.Xu"
[How]
1. Search OEM I2C info from BIOS and compare with input parameter.
2. If BIOS doesn't record it, just try to read one byte.
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez
Signed-off-by: JinZe.Xu
---
drivers/gpu/drm/amd/display/dc/core/dc.
This DC patchset brings improvements in multiple areas. In summary:
* Fixes on lane status, zstate, engine ddc, debugfx entry.
* Enhancements for Pollock, EDID status.
* Amongst other.
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.108.0
Aric Cyr (1):
drm/amd/display:
[Why]
There is underflow / visual corruption DCN301, for high
bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60.
[How]
Use up-to-date watermark values for DCN301.
Signed-off-by: Agustin Gutierrez
---
.../amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 16
From: Anthony Koo
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 30 +--
.../amd/display/dc/dcn10
missing PSR state patch.
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 254b760ae91f
-by: Agustin Gutierrez
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 ---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 -
.../display/dc/dce110/dce110_hw_sequencer.c | 24 --
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 +++--
.../drm/amd/display
This reverts commit 4e605d4b6a510f751b22df4d13829aefb8a0ccec.
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index
From: Anthony Koo
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc
From: Nikola Cornij
[why]
The original latencies were causing underflow in some modes
[how]
Replace with the up-to-date watermark values based on new measurments
Reviewed-by: Ahmad Othman
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nikola Cornij
---
.../amd/display/dc/clk_mgr/dcn31
From: Jake Wang
[Why]
bios_golden_init will override dccg_init during init_hw.
[How]
Move dccg_init to after bios_golden_init.
Reviewed-by: Aric Cyr
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
From: Nevenko Stupar
[Why]
V3_4 is latest in use.
[How]
Add bios parser support for firmware_info_v3_4 along
with some relevant fields it is also retrieving from dce_info
and smu_info.
Reviewed-by: Jun Lei
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nevenko Stupar
---
.../drm/amd
From: Jake Wang
[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h| 9 +++--
drivers/gpu/drm/amd/display/dc/d
From: Jake Wang
[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.
Reviewed-by: Ariel Bernstein
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 15 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dc
From: Jake Wang
[Why & How]
Z10 save is done during PSR and bootup.
DSC disable does not need to save for Z10.
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4
1 file changed, 4 delet
From: Eric Yang
[Why]
Z9 latency is higher than when we originally tuned the watermark
parameters, causing underflow. Increasing the value until the latency
issues is resolved.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Eric Yang
---
drivers/gpu/drm
From: Jake Wang
[Why & How]
Disable root clock for dsc when not being used.
Reviewed-by: Nikola Cornij
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 16 -
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
it as part of DML input
parameters.
This can't be enabled unconditionally on older ASIC because it blocks
some expected modes so only target DCN3.1 for now.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display
-by: Wyatt Wood
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu
From: Hansen
Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused
Reviewed-by: Nicholas Kazlauskas
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Hansen
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 17 +
1 file changed, 17 insertions(+)
diff --git
as the rest of the pixel data during vactive.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
From: "Lai, Derek"
[Why]
Error message on Linux when booting.
[How]
Removed power down on boot from DCN31 HW init
to match DCN10 HW init.
Reviewed-by: Anthony Koo
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Derek Lai
---
.../drm/amd/display/dc/dcn31/dcn31_hwseq
From: Nikola Cornij
[why]
The requirement is that image width up to 4096 shall be supported
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nikola Cornij
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Aric Cyr
[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.
[How]
Validate that src and dst rects are valid before using for scaling
calculations.
Reviewed-by: Josip Pavic
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+
From: Wenjing Liu
Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control. However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.
Reviewed-by: Ariel Bernstein
Acked-by: Agustin Gutierrez Sanchez
From: Wenjing Liu
[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.
Reviewed-by: George Shen
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd
Somasundaram
Reviewed-by: Jun Lei
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 9 ++---
drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 2 +-
3 files
Reviewed-by: Jun Lei
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index
From: Michael Strauss
[WHAT]
One of the current VPG power on calls is unnecessary
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 10 --
drivers/gpu/drm/amd/display/dc/dcn31
From: Jake Wang
[Why & How]
Disable root clock for dpp when not being used.
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 5 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
patch.
Cc: Daniel Wheeler
Cc: Mark Broadworth
Agustin Gutierrez (2):
Revert "drm/amd/display: Fix error in dmesg at boot"
Revert "drm/amd/display: Add helper for blanking all dp displays"
Anthony Koo (2):
drm/amd/display: Change initializer to single brace
From: Wenjing Liu
Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control. However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.
Reviewed-by: Ariel Bernstein
Acked-by: Agustin Gutierrez Sanchez
From: Aric Cyr
[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.
[How]
Validate that src and dst rects are valid before using for scaling
calculations.
Reviewed-by: Josip Pavic
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
From: Wenjing Liu
[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.
Reviewed-by: George Shen
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+
From: Michael Strauss
[WHAT]
One of the current VPG power on calls is unnecessary
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 10 --
drivers/gpu/drm/amd/display/dc/dcn31
Somasundaram
Reviewed-by: Jun Lei
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 9 ++---
drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 2 +-
3 files
Reviewed-by: Jun Lei
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index
From: Jake Wang
[Why & How]
Disable root clock for dpp when not being used.
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 5 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
patch.
Cc: Daniel Wheeler
Cc: Mark Broadworth
Agustin Gutierrez (2):
Revert "drm/amd/display: Fix error in dmesg at boot"
Revert "drm/amd/display: Add helper for blanking all dp displays"
Anthony Koo (2):
drm/amd/display: Change initializer to single brace
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