This reverts commit 44069f0f9b1fe577c5d4f05fa9eb02db8c618adc since
the code path is called from FPU context, and triggers error like:
[ 26.924055] BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:306
[ 26.924060] in_atomic(): 1, irqs_disabled(): 0, non_block: 0,
line 922)
Cc: Tom Chung
Cc: Nicholas Kazlauskas
Cc: Bhawanpreet Lakha
Cc: Rodrigo Siqueira
Cc: Roman Li
Cc: Hersen Wu
Cc: Alex Hung
Cc: Aurabindo Pillai
Cc: Harry Wentland
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 3 +++
1 file
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../include/asic_reg/dcn/dcn_4_1_0_offset.h | 51 ++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h
Move creation of CGS device node and the DAL allocation list from
amdgpu_dm_init() to dm_sw_init() which runs before dmub's sw init hook.
This is required for communicating with the VBIOS DMUB image from the
VBIOS that was loaded for early pre-os boot.
Signed-off-by: Aurabindo Pillai
Allocate some memory, send the address in chunks to dmub, and finally
ask it to copy the bounding box data into the newly allocated memory.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 121 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
New commands for enabling copy of DC bounding box values from VBIOS DMUB
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm
All the DC_FP_START/END should be used before call anything from DML2,
for this reason, the use of those guards inside DML it is not correct.
This commit removes two unnecessary DC_FP_START/END from a dml2
function.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu
When ODM slice happens on DCN401, there is a null pointer exception
caused by that. This commit address this issue by checking if the
required data structures are initialized.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
DCN401 is using DCN 320 headers, which does not have all the right
registers for DCN401. This commit just replace DCN320 includes with the
one from DCN410.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c| 4
Drop the extra HPD irq entry for DCN401.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
b
From: Pinninti
[why]
cleaning up the code refactor requires hubp to be in its own component.
[how]
move all files under newly created hubp folder and fixing the makefiles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Pinninti
---
drivers/gpu/drm/amd/display/dc/dcn401/Makefile | 1
From: Rodrigo Siqueira
This commit removes some unused code with the required adjustments.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h | 2 +-
From: Samson Tam
[Why]
Enable sharpener support for DCN401
[How]
- Removed memcmp check that was preventing ISHARP from being enabled.
- Add missing ISHARP register defines, masks, and writes.
- Add programming of Blur and Scale coefficients.
- Program FMT_MODE and NLDELTA registers based on
From: "Arvindekar, Sridevi"
[Why]
Incorrect cursor position calculation in some scenarios. Also for
mirror and rotation cases.
[How]
Fix for incorrect cursor position. Added new test scenarios for diags
cursor test. Updated CRC for few of the diags cursor test scenarios.
Reviewed-by:
Reviewed-by: Aurabindo Pillai
On 5/16/24 3:26 PM, roman...@amd.com wrote:
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP gua
Reviewed-by: Aurabindo Pillai
On 4/23/24 9:29 PM, Srinivasan Shanmugam wrote:
This commit removes a redundant NULL check in the
`dce110_set_input_transfer_func` function in the `dce110_hwseq.c` file.
The variable `tf` is assigned the address of
`plane_state->in_transfer_func` unconditiona
Enable initializing Display Manager for DCN410 IP
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index
Override DCN IP version to 4.0.1 from 4.1.0 temporarily until change is
made in DC codebase to use 4.1.0
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b
Override DCN IP version to 4.0.1 from 4.1.0 temporarily until change is
made in DC codebase to use 4.1.0
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b
Patch has been merged to amd-staging-drm-next.
On 4/28/24 12:09 PM, Aurabindo Pillai wrote:
Thanks for the fix!
Reviewed-by: Aurabindo Pillai
On 4/28/24 8:42 AM, Dan Carpenter wrote:
Smatch complains because some lines are indented more than they should
be. I went a bit crazy re-indenting
Thanks for the fix!
Reviewed-by: Aurabindo Pillai
On 4/28/24 8:42 AM, Dan Carpenter wrote:
Smatch complains because some lines are indented more than they should
be. I went a bit crazy re-indenting this. ;)
The comments were not useful except as a marker of things which are left
From: Aric Cyr
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd
From: Anthony Koo
- Adjust the dmub_fw_boot_options reserved bits to be correct
Acked-by: Aurabindo Pillai
Signed-off-by: Anthony Koo
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
From: Rodrigo Siqueira
The string dp_hdmi_dongle_signature_str already uses u8 but the string
dp_hdmi_dongle_signature_str does not. Just replace uint8_t with u8 for
dp_hdmi_dongle_signature_str.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested
mode set.
Reviewed-by: Jun Lei
Acked-by: Aurabindo Pillai
Signed-off-by: yi-lchen
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 12 ++---
.../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 13 +++---
.../
From: Sung Joon Kim
[why & how]
There are potential issues with Z8 and IPS
that need to be addressed and need to add
in missing function pointers.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
drivers/gpu/drm
From: Cruise
[Why]
Error correction was enabled in a monitor which doesn't support.
[How]
Disable error correction if it's not supported
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Cruise
Tested-by: Daniel Wheeler
---
.../display/dc/link/protocols/link_dp_phy.c
From: Sung Joon Kim
[why & how]
The recout x offset was incorrect which led to
wrong viewport calculation. For stereo
side-by-side case, the slice index should be
0 for both split pipes.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Da
to ensure hubp has the right attributes to be programmed.
Reviewed-by: Agustin Gutierrez
Acked-by: Aurabindo Pillai
Signed-off-by: Harry Wentland
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2
-by: Agustin Gutierrez
Acked-by: Aurabindo Pillai
Signed-off-by: Harry Wentland
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 87 +--
drivers/gpu
-by: Chaitanya Dhere
Acked-by: Aurabindo Pillai
Signed-off-by: Joshua Aberback
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers
From: Ilya Bakoulin
Not every ASIC implements dp_set_dsc_config. Add condition to prevent
calls to unimplemented function.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Ilya Bakoulin
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 16
, this causes bw allocation failure
when allocation greater than estimated bw.
[How]
Do zero alloc to make the CM to release preallocation and
update estimated BW correctly for all DPIAs per host router.
Reviewed-by: PeiChen Huang
Acked-by: Aurabindo Pillai
Signed-off-by: Meenakshikumar
tor->sink check to find pipe_ctx.
CC: sta...@vger.kernel.org
Reviewed-by: Aurabindo Pillai
Signed-off-by: Hersen Wu
Tested-by: Daniel Wheeler
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 48 ++-
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/g
From: Nicholas Kazlauskas
[Why]
It's possible that the write hasn't fully completed by the time we
send (and flush) a command to DMCUB to notify idle to request IPS2
exit.
[How]
Perform a readback of the volatile structure into dc_dmub_srv state.
Reviewed-by: Charlene Liu
Acked-by: Aurabindo
will flicker.
- Generalized increase/reduce dependent functions to reduce code clutter
and allow for easier use.
- Added a debug option to enable the feature. Disabled by default.
Co-authored-by: Ethan Bitnun
Reviewed-by: Dillon Varone
Acked-by: Aurabindo Pillai
Signed-off-by: Ethan Bitnun
uld be skipped when clearing the payload allocation table.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/
w BIOS
version 2.3.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Gabe Teeger
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/d
From: Michael Strauss
[WHY]
Avoid race condition which puts LTTPR into bad state during UHBR LT.
[HOW]
Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
Tested-by: Daniel Wheeler
-by: Aurabindo Pillai
Signed-off-by: Sung-huai Wang
Tested-by: Daniel Wheeler
---
.../dc/link/protocols/link_dp_irq_handler.c | 25 ---
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
b/drivers/gpu
From: Sung Joon Kim
[why & how]
Need to update the function pointers that
perform the power up and down sequence
to reuse the modified sequence as a requirement.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
dri
wed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Signed-off-by: Swapnil Patel
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
b/drive
eck in dc_resource.c/resource_log_pipe_topology_update.
CC: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Natanel Roizenman
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers
From: Dennis Chan
When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.
Reviewed-by: ChunTao Tso
Acked-by: Aurabindo Pillai
Signed-off-by: Dennis Chan
Tested
From: Rodrigo Siqueira
Drop unnecessary semicolon that can create a problem of double semicolon
in some compilers.
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h | 3
From: Rodrigo Siqueira
This commit add some DPCX IRQ types.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc
From: Rodrigo Siqueira
This commit adds, updates, and removes some of the comments used in the
DC code.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h| 2 +-
.../gpu/drm/amd/display/dc/dpp/dcn201
From: Rodrigo Siqueira
In the DCN20 resource initialization, ensure that DMCUB support starts
configured as true.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
1 file changed, 1
From: Rodrigo Siqueira
Add some missing HDCP registers to be used in DCN35.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn35/dcn35_dio_link_encoder.h| 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff
From: Rodrigo Siqueira
This commit address some small code style issues in DC.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c| 3 +--
drivers/gpu/drm/amd/display/dc/dm_helpers.h
From: Rodrigo Siqueira
This commit reorganizes the order in which some control registers are
presented to make it easier to identify the operations based on the
hardware doc.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc
From: George Shen
Theoretically rare corner case where ceil(Y) results in rounding up to
an integer. If this happens, the 1 should be carried over to the X
value.
CC: sta...@vger.kernel.org
Reviewed-by: Rodrigo Siqueira
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
From: Rodrigo Siqueira
This commit removes some unnecessary code and makes the required
adjustments to replace other parts of the code with a short option.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce
From: Dmytro Laktyushkin
Headless dp 2.0 will take longer to update.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Rodrigo Siqueira
This commit add some missing HDMI control registers to DCN3x.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 3 +++
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
From: Rodrigo Siqueira
Add TMDS balancer control to the list of available encoder registers for
DCN 30.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h | 3 ++-
1 file changed, 2
From: Rodrigo Siqueira
DCN3.0 supports some specific DWB debug registers that are not exposed
yet. This commit just adds the missing registers.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h | 14
From: Rodrigo Siqueira
This commit add some missing debug registers for DPCS and RDPC debug.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 5 +++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 2
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
==
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.214.0
Aric Cyr (1):
Add new firmware header definitions reqiured for DCN401
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/include/atomfirmware.h | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include
From: Nicholas Kazlauskas
[Why]
New worst-case measurement observed at 1897us.
[How]
Increase to 2000us to cover the new worst case + margin.
Reviewed-by: Ovidiu Bunea
Acked-by: Aurabindo Pillai
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/resource/dcn35
.
* HDMI compliance test fixes and other improvements
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
-by: Charlene Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 83 +++--
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 +-
.../gpu/drm/amd/display/dmub/inc
From: Charlene Liu
[why]
allow psr-su/replay for z8
Reviewed-by: Muhammad Ahmed
Reviewed-by: Sung joon Kim
Acked-by: Aurabindo Pillai
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 12 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
From: Charlene Liu
[why]
sw has most of the fgcg enabled which is the same as HW default.
but driver disabled some due to enable flag not initialized.
comparing HW state, we still need to enable dpp and dio.
Reviewed-by: Muhammad Ahmed
Acked-by: Aurabindo Pillai
Signed-off-by: Charlene Liu
From: George Shen
[Why/How]
A regression was identified with the change to add left edge pixel for
YCbCr422/420 + ODM combine cases.
This reverts commit 8d09500a33f6a0e0df9cf17822fe51520d0df002
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: George Shen
---
drivers/gpu
From: Roman Li
[Why]
There is a potential memory access violation while
iterating through array of dcn35 clks.
[How]
Limit iteration per array size.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Roman Li
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
-by: Aurabindo Pillai
Signed-off-by: Martin Tsai
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index ba1fec3016d5
From: Sohaib Nadeem
[why]:
issues fixed:
- comparison with wider integer type in loop condition which can cause
infinite loops
- pointer dereference before null check
Reviewed-by: Josip Pavic
Acked-by: Aurabindo Pillai
Signed-off-by: Sohaib Nadeem
---
.../gpu/drm/amd/display/dc/bios
From: Gabe Teeger
This reverts commit 3fda240dc2f6a4a9a3965b80cfb83d0ddfbf489c.
System hang observed, this commit is thought to be the
regression point.
Reviewed-by: Ovidiu Bunea
Acked-by: Aurabindo Pillai
Signed-off-by: Gabe Teeger
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35
when performing test pattern overrides.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dc.h | 12 +
.../display/dc/link/accessories/link_dp_cts.c | 27 +++---
.../hwss/link_hwss_dio_fixed_vs_pe_retimer.c
during create the
stream.
Reviewed-by: Aurabindo Pillai
Acked-by: Aurabindo Pillai
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display
params in next program pipe.
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 7 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/hwss/dcn20
From: Sohaib Nadeem
[why]:
This reverts commit 5abbfa320b88da6034fd4121fa68c2b0e15e97ac.
The commit caused corruption when running some applications in fullscreen
Reviewed-by: Alvin Lee
Acked-by: Aurabindo Pillai
Signed-off-by: Sohaib Nadeem
---
drivers/gpu/drm/amd/display/dc/dml/dcn32
From: Zhikai Zhai
[WHY]
We Double-check link status if training successful,
but miss the lane align status.
[HOW]
Add the lane align status check
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Zhikai Zhai
---
.../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
Summary:
* Revert some changes related to pixel encoding and clocks that cause
corruption
* IPS hang fix and FGCG enable by default for DCN35
* PSR-SU/Replay fixes
* Plane clip size change treated as medium update
* Fix for checking link alignment done during link
.c:905
link_set_dsc_pps_packet() warn: variable dereferenced before check 'dsc' (see
line 903)
Cc: sta...@vger.kernel.org
Cc: Aurabindo Pillai
Cc: Rodrigo Siqueira
Cc: Hamza Mahfooz
Cc: Wenjing Liu
Cc: Qingqing Zhuo
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Corrected the logic when !pi
ol.c:947
edp_setup_replay() warn: variable dereferenced before check 'link' (see line
933)
Cc: Bhawanpreet Lakha
Cc: Harry Wentland
Cc: Rodrigo Siqueira
Cc: Aurabindo Pillai
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
.../dc/link/protocols/link_edp_panel_control.c
Lei
Cc: Hamza Mahfooz
Cc: Aurabindo Pillai
Cc: Rodrigo Siqueira
Cc: Alex Deucher
Cc: Srinath Rao
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 ++-
2 files changed, 3 insertions(+), 2
From: Aric Cyr
Summary:
Bug fixes for:
* DCN35 power gating
* P-state change, & prefetch logic
* ABM
* DP 2.1
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
-by: Jun Lei
Acked-by: Aurabindo Pillai
Signed-off-by: Alvin Lee
---
.../dc/dml/dcn32/display_mode_vba_32.c| 3 ++
.../dc/dml/dcn32/display_mode_vba_util_32.c | 33 +++
.../dc/dml/dcn32/display_mode_vba_util_32.h | 1 +
3 files changed, 31 insertions(+), 6 deletions
From: Allen
[Why]
To match the hardware sequence
Reviewed-by: Charlene Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Allen
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35
From: Taimur Hassan
[Why & How]
HostVMMinPageSize is expected to be in KB according to spec,
the checks later down the line reflect this as well.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Taimur Hassan
---
.../drm/amd/display/dc/dml2/display_mode_co
From: Charlene Liu
[why]
Power up and power down has reverted programming order.
also make sure disable root clock last.
Reviewed-by: Muhammad Ahmed
Acked-by: Aurabindo Pillai
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/dcn35/dcn35_init.c | 3 +-
.../amd/display/dc/hwss
From: Fangzhi Zuo
dtbclk is unavaliable from pmfw. Try to grab the value from bounding box
Reviewed-by: Charlene Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 14 +-
.../amd/display/dc/dml2
in
underflow
- To fix this issue, force p-state disallow and unforce after
the transition from no planes case -> one or more planes active
Reviewed-by: Samson Tam
Acked-by: Aurabindo Pillai
Signed-off-by: Alvin Lee
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 20 +++
From: Michael Strauss
[WHY]
Introduces regression with DP2 native displays
[HOW]
Revert commit 311ba210d
Reviewed-by: Charlene Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c | 7 ---
1 file changed, 7 deletions
From: Sung Joon Kim
[why & how]
User interface cannot guarantee system is in
idle state, so need to ensure we exit idle state
before accessing any HW data.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc
From: Joshua Aberback
Reviewed-by: Dillon Varone
Acked-by: Aurabindo Pillai
Signed-off-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd
FP guard is valid for all recent asics, not just RV, so fix the comment.
Reviewed-by: Chaitanya Dhere
Acked-by: Aurabindo Pillai
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Ran Shi
why:
With DP2.1a expansion we are allowing DP40 cables to do UHBR13.5
how:
Assume UHBR10 means UHBR13.5 also for unknown cable type and
passive cable type.
Reviewed-by: George Shen
Acked-by: Aurabindo Pillai
Signed-off-by: Ran Shi
---
.../display/dc/link/protocols
/amd/display: For prefetch mode > 0, extend prefetch if possible
drm/amd/display: Force p-state disallow if leaving no plane config
Aric Cyr (1):
drm/amd/display: 3.2.264
Aurabindo Pillai (2):
drm/amd/display: Use explicit size for types in DCCG's struct
dp_dto_params
drm/amd/display:
Reviewed-by: Alvin Lee
Acked-by: Aurabindo Pillai
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
b/drivers/gpu/drm/amd/display/dc/inc/hw
[Why]
To enable testing/development of DML2, expose a new debug mask for future use.
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include
T__GET_TRACE_BUFFER_MASK_WORD2 = 118,
+
+ /**
+* DESC: Updates the trace buffer mask bit32~bit63.
+ */
+ DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
};
/**
Reviewed-by: Aurabindo Pillai
On 2023-11-10 12:18, Hamza Mahfooz wrote:
For features that are implemented primarily in DMUB (e.g. PSR), it is
useful to be able to trace them at a DMUB level from the kernel,
especially when debugging issues. So, introduce a debugfs interface that
is able to read and set the DMUB trace mask
On 2023-10-29 05:39, José Pekkarinen wrote:
Spotted by coccicheck, there is a redundant check for
v->SourcePixelFormat[k] != dm_444_16. This patch will
remove it. The corresponding output follows.
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c:5130:86-122: duplicated
: "Pan, Xinhui"
Cc: Rodrigo Siqueira
Cc: Aurabindo Pillai
Signed-off-by: Srinivasan Shanmugam
---
.../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 69 +++
1 file changed, 42 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b
On 2023-10-30 12:26, José Pekkarinen wrote:
On 2023-10-30 15:52, Aurabindo Pillai wrote:
On 10/29/2023 8:44 AM, José Pekkarinen wrote:
This patch addresses the following warning spotted by
using coccinelle where the case checked does the same
than the else case.
drivers/gpu/drm/amd/display
wportWidthChroma[k] > v->SurfaceWidthC[k] ||
v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
ViewportExceedsSurface = true;
}
Thanks for catching.
Reviewed-by: Aurabindo Pillai
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