[PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency

As for other clock domains. Change-Id: I0a78c133f00cd11133bc755bf0443505088f024c Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h| 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/inc

[PATCH] drm/amd/pm: increase mclk switch threshold to 200 us

To avoid underflow seen on Polaris10 with some 3440x1440 144Hz displays. As the threshold of 190 us cuts too close to minVBlankTime of 192 us. Change-Id: Ieca0dc900f0b5764dc661e397e41e8c277ff13de Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 2 +- 1 file

[PATCH] drm/amd/pm: setup APU dpm clock table in SMU HW initialization

. Change-Id: I2bb1f9ba26f9c8820c08241da62f7be64ab75840 Signed-off-by: Evan Quan Reported-by: Dirk Gouders --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b

[PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors

Revert the guilty change introduced by the commit below: drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++- 1 file

[PATCH 1/2] drm/amd/pm: decouple the watermark table setting from socclk/uclk dpms

As they have no real dependence. And for Navi1x, the socclk/uclk dpms are enabled after DAL initialization. Change-Id: Ia66a92155aadff40e4e2e46edbedce840cfb57ca Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 +++ 1 file changed, 7 insertions(+), 8

[PATCH 2/2] drm/amd/pm: drop redundant watermarks bitmap setting

As this is already set inside the implementation of smu_set_watermarks_table(). Change-Id: I4d4d40855f0aad43f6d21d471b64f1c7e696f0e7 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu

[PATCH] drm/amd/pm: correct the pmfw version check for Navi14

Otherwise, that will be always true for Navi14. Change-Id: Ief94150d10e4987e405d97674d9ae4efe89246fb Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11

[PATCH] drm/amd/pm: apply dummy reads workaround for CDR enabled only

For CDR disabled case, the dummy reads workaround is not needed. Change-Id: I474619b3d82792151870811c289ab311028de211 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm

[PATCH 4/4] drm/amd/pm: add Raven2 watermak WmType setting

Which tells it's a nomral pstate change or memory retraining. Change-Id: If55d6c3f1dfc28005c6d767154664feddcda6f5b Signed-off-by: Evan Quan Tested-by: Changfeng Zhu --- drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h | 3 ++- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 11

[PATCH 3/4] drm/amd/pm: add Renoir watermak WmType setting

Which tells it's a nomral pstate change or memory retraining. Change-Id: I8619115486021537b52c067c4d0b9bfc1417fc35 Signed-off-by: Evan Quan Tested-by: Changfeng Zhu --- drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd

[PATCH 1/4] drm/amd/pm: drop dead code

Raven never goes to swsmu path. So "adev->smu.ppt_funcs" will be always false. Change-Id: Ia55ad97bcf9ecf135a9bd795f36a5b521d718b20 Signed-off-by: Evan Quan Tested-by: Changfeng Zhu --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 3 --- 1 file changed, 3 deletions(-

[PATCH 2/4] drm/amd/pm: drop unnecessary wrappers around watermark setting

The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15" is totally unnecessary and can be dropped. Change-Id: Ieaa1d1f1cc12b29a8ec26d330fd209662940417d Signed-off-by: Evan Quan Tested-by: Changfeng Zhu --- .../amd/display/amdgpu_dm/amdgpu_dm_pp_s

[PATCH 2/3] drm/amd/pm: apply no power source workaround if dc reported by gpio

If dc reported by gpio is supported, the power source switching will be performed by pmfw automatically. Thus the power source setting workaround for Navi1x will be not needed. Change-Id: Idd6231ce1e33a4e292e7eff3b0f8b779911944f1 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu

[PATCH 3/3] drm/amd/pm: move NAVI1X power mode switching workaround to post_init

Since that should be the correct place to put ASIC specific workarounds. Change-Id: Ia7cf4bfabf85a4409e57542926238c7e196af719 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 14 - .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 20 ++- 2

[PATCH 1/3] drm/amd/pm: process pending AC/DC switch interrupt

Process any pending interrupt that occured before driver register for interrupt from GPIO/SMU. Change-Id: Ie846304408df27c7a7f2b29cec8f7dcb9d08905e Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 40 ++- 1 file changed, 30 insertions(+), 10 deletions

[PATCH 2/2] drm/amd/pm: correct Renoir UMD Stable Pstate settings

Update the UMD stable Pstate settings with correct clocks. Change-Id: Ia14eb8e23c513cad0bd633fbeb99ed694c7e3f7e Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 52 ++- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.h | 1 + 2 files changed, 52

[PATCH 1/2] drm/amd/pm: lower Raven UMD Stable Pstate VCN values

SMU FCLK,SOCCLK have dependency on VCN CLKs. Lower VCN values so that FCLK, SOCCLK reflect values set by UMD Stable Pstate. Change-Id: Iddf2757be18aacc0bb66122dd2b690e58503223b Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 4 ++-- drivers/gpu/drm/amd/pm

[PATCH 1/9] drm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2)

So that ASIC specific actions can be added. V2: better namings Change-Id: Iabc9241d3e10ece9cd54d8cdb3ae8c8b831c7bce Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++ drivers/gpu/drm/amd/pm/swsmu

[PATCH 8/9] drm/amd/pm: correct the requirement for umc cdr workaround

The workaround can be applied only with UCLK DPM enabled. And expand the workaround to more Navi10 SKUs and also Navi14. Change-Id: I8be4256079f81e292b39bcf43b4a84db82aa069b Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 19 +-- 1 file changed, 9

[PATCH 3/9] drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init

That's where the uclk dpm get enabled and then the uclk cdr workaround can be applied. Change-Id: I520ae0fbc1c3be68324377c7d8c6dc4a346d3a57 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h| 1 - drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 -- .../gpu/drm

[PATCH 2/9] drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2)

This is needed for Navi1X only. And it may help for display missing or hang issue seen on some high resolution monitors. V2: no UCLK DPM enablement for Navi10 A0 secure SKU Change-Id: Id3965a638c2a238d52cf074f2111dc4bf2244a3e Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11

[PATCH 5/9] drm/amd/pm: allocate a new buffer for pstate dummy reading

This dummy reading buffer will be used for the new Navi1x UMC CDR workaround. Change-Id: Ida41374c0ea156527a1bf1104c7b2b909e562f7a Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 45 +++ 2 files

[PATCH 6/9] drm/amd/pm: implement a new umc cdr workaround

By uploading dummy pstate tables. Change-Id: I9f52f965d23cae46b4a4eeab7790183e5d09bf27 Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/inc/smu_11_0_cdr_table.h | 194 ++ drivers/gpu/drm/amd/pm/inc/smu_types.h| 2 + drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h | 5

[PATCH 9/9] drm/amd/pm: make namings and comments more readable

And to fit more accurately what the cod does. Change-Id: I2d917e66b55925c3a14aa96ac8e0c8c2110848c0 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11

[PATCH 4/9] drm/amd/pm: revise the umc hybrid cdr workaround

Drop the unused message(SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE). And do not apply this workaround when the max uclk frequency is greater than 750Mhz. Change-Id: I862e80cc96424c82f34aff0fa85b3d37f4dbcb2b Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 61

[PATCH 7/9] drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares

And different workaround will be applied based on hybrid cdr bit. Change-Id: I828dc3605dbe0bb5a5e1a0db409658608ff21888 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/smu_types.h| 1 + drivers/gpu/drm/amd/pm/inc/smu_v11_0_ppsmc.h | 4 ++- .../gpu/drm/amd/pm/swsmu/smu11

[PATCH] drm/amd/pm: avoid false alarm due to confusing softwareshutdowntemp setting

Normally softwareshutdowntemp should be greater than Thotspotlimit. However, on some VEGA10 ASIC, the softwareshutdowntemp is 91C while Thotspotlimit is 105C. This seems not right and may trigger some false alarms. Change-Id: I940cc6e450eebccd93ccdc3428187f6b7c09dcda Signed-off-by: Evan Quan

[PATCH] drm/amd/pm: suppress static checker warning

Suppress the warning below: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.c:274 phm_check_smc_update_required_for_display_configuration() warn: signedness bug returning '(-22)' Change-Id: If50e39fe401c16d981d917ef7d8d5ea81d6538df Reported-by: Dan Carpenter Signed-off-by: Evan

[PATCH 1/4] drm/amd/pm: drop unnecessary feature->mutex lock protections(V2)

description Change-Id: I096d7ab0855ff59b0ecb56fd9d6d9946b3605fc8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 -- 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers

[PATCH 4/4] drm/amd/pm: minor cleanups

Drop unneeded "ret". Change-Id: If5eabb1e96153133a833d0e5b1dca9c0f0928891 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 22 +-- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/am

[PATCH 3/4] drm/amd/pm: drop unnecessary table existence and dpm enablement check

Either this was already performed in parent API. Or the table is confirmed to exist. Change-Id: Ie6778a5035749221e0f9d5ad977a0e56392771dd Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 - drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

[PATCH 2/4] drm/amd/pm: drop unnecessary smu_baco->mutex lock protections(V2)

description Change-Id: I7078ac26ae71eb6c7cbf918a127adfc2f56acf7d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 -- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 -- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 -- drivers/gpu/drm/amd

[PATCH] drm/amd/pm: correct the thermal alert temperature limit settings

-by: Evan Quan --- .../drm/amd/pm/powerplay/hwmgr/vega10_thermal.c | 15 +++ .../drm/amd/pm/powerplay/hwmgr/vega12_thermal.c | 15 +++ .../drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 15 +++ 3 files changed, 21 insertions(+), 24 deletions(-) diff --git

[PATCH 4/4] drm/amd/pm: minor cleanups

Drop unneeded "ret". Change-Id: If5eabb1e96153133a833d0e5b1dca9c0f0928891 Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 22 +-- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

[PATCH 3/4] drm/amd/pm: drop unnecessary table existence and dpm enablement check

Either this was already performed in parent API. Or the table is confirmed to exist. Change-Id: Ie6778a5035749221e0f9d5ad977a0e56392771dd Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 - drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 16

[PATCH 2/4] drm/amd/pm: drop unnecessary smu_baco->mutex lock protections

As it is confirmed to have no race condition during hw setup and baco support checking. Change-Id: I7078ac26ae71eb6c7cbf918a127adfc2f56acf7d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 -- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2

[PATCH 1/4] drm/amd/pm: drop unnecessary feature->mutex lock protections

As it is confirmed to have no race condition during hw setup. Change-Id: I096d7ab0855ff59b0ecb56fd9d6d9946b3605fc8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 -- 2 files changed, 6 deletions(-) diff

[PATCH 3/3] drm/amd/pm: correct Vega20 swctf limit setting

Correct the Vega20 thermal swctf limit. Change-Id: I6cec41152b5ac377177b1a9fda92d7b6cd982e9e Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr

[PATCH 1/3] drm/amd/pm: correct Vega10 swctf limit setting

Correct the Vega10 thermal swctf limit. Change-Id: I220c18bcb0772bfb8cb674337bac6dccafbd7698 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr

[PATCH 2/3] drm/amd/pm: correct Vega12 swctf limit setting

Correct the Vega12 thermal swctf limit. Change-Id: I369e1adf9f177a8d9558282db9aa908b5a25bbb3 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr

[PATCH 3/4] drm/amdgpu: add interface for setting MGCG perfmon

Enable Navi1X MGCG perfmon setting. Change-Id: Ifc860a798becbe372f974f7eb537a4a57ac4943f Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm

[PATCH 1/4] drm/amd/pm: correct gfx and pcie settings on umd pstate switching

For entering UMD stable Pstate, the operations to enter rlc_safe mode, disable mgcg_perfmon and disable PCIE aspm are needed. And the opposite operations should be performed on UMD stable Pstate exiting. Change-Id: Iff4aa465fd16f55a4f4de8ee0503997b204f8f9d Signed-off-by: Evan Quan --- drivers

[PATCH 4/4] drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)

Fulfill Navi gfx and pcie settings on umd pstate switching. V2: temporarily skip the pcie ASPM setting considering the ASPM function is not fully enabled yet Change-Id: I8d746d4c25f890665feeffddf64164ed2b1f5ccc Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/nv.c | 17

[PATCH 2/4] drm/amdgpu: add interface for setting ASPM

Support NAVI10 ASPM setting. Change-Id: I0c9410951e23b1d4a30bf8e373431dcb16a4573b Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 39 2 files changed, 41 insertions(+) diff --git a/drivers/gpu

[PATCH 5/5] drm/amd/pm: widely share the logic for deep sleep control

Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Change-Id: I9b80956fee5b094ea0e102601add6c02e3429719 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 3 ++ .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 35

[PATCH 3/5] drm/amd/pm: add Arcturus deep sleep control interface

This is needed for UMD pstate switch. Change-Id: I8e753c682c29fe420167b14b23f526ea9b0db42b Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 34 +++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b

[PATCH 1/5] drm/amd/pm: disable/enable deep sleep features on UMD pstate enter/exit

Add deep sleep disablement/enablement on UMD pstate entering/exiting. Change-Id: I4fbc02bb4a390ab82293a5ff9c91f2a8beb0a3c9 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu

[PATCH 2/5] drm/amd/pm: add Navi1x deep sleep control interface

This is needed for UMD pstate switch. Change-Id: Icd5d207359b7b83c1dd689a41fd9b48f537cde9a Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 34 +++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b

[PATCH 4/5] drm/amd/pm: add Sienna Cichlid deep sleep control interface

This is needed for UMD pstate switch. Change-Id: I97ee3af60f4a3e4c2f575ce8c8e1a2866ed37f02 Signed-off-by: Evan Quan --- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 34 +++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

[PATCH 5/5] drm/amd/pm: widely share the logic for gfx ulv control

Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Change-Id: I16958d114afbb2433789ca350019fea9b50e1218 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 +++ drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 13

[PATCH 3/5] drm/amd/pm: add Arcturus gfx ulv control interface

This is needed for UMD pstate switch. Change-Id: I40e235add95d6abbf99186112673a411edf2bb39 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b

[PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit

Add gfx ulv disablement/enablement on UMD pstate entering/exiting. Change-Id: Ieb38fdb5975b563f24c0b172fedd01acf99afb10 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h

[PATCH 2/5] drm/amd/pm: add Navi1x gfx ulv control interface

This is needed for UMD pstate switch. Change-Id: Id14399d3a5e4b24bb8a72a298ec4e96717444741 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers

[PATCH 4/5] drm/amd/pm: add Sienna Cichlid gfx ulv control interface

This is needed for UMD pstate switch. Change-Id: I23d68bc291960118c799366cbb3fc89ccb42f98c Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

[PATCH] drm/amd/pm: drop redundant MEM_TYPE_* macros

As these are already defined in amdgpu_atombios.h. Otherwise, we may hit "redefined" compile warning. Change-Id: Ia2a9e10b35173fedcbbd8e0abb8ad38dd231baf4 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h | 9 - 1 file changed, 9 deletions(-)

[PATCH] drm/amd/powerplay: suppress the kernel test robot warning

return ret; ^ drivers/gpu/drm/amd/powerplay/smu_cmn.c:477:6: note: first condition if (ret) ^ drivers/gpu/drm/amd/powerplay/smu_cmn.c:485:9: note: second condition return ret; ^ Change-Id: I4b512008b8fe410fc7974e0483c39206ebec08ca Signed-off-by: Evan Quan Reported-by: kerne

[PATCH] drm/amd/pm: optimize the power related source code layout

The target is to provide a clear entry point(for power routines). Also this can help to maintain a clear view about the frameworks used on different ASICs. Hopefully all these can make power part more friendly to play with. Change-Id: I2baaa98f3c1078816bd44e14153d8bfbbddd141b Signed-off-by: Evan

[PATCH 2/4] drm/amd/powerplay: drop unnecessary pp_funcs checker

It's redundant. Also, the callers should not care about the implementation details. Change-Id: I5ae2e334a5657a077747e6bd1428573baad89e33 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 11 +++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++--- drivers/gpu/drm/amd

[PATCH 4/4] drm/amd/powerplay: put those exposed power interfaces in amdgpu_dpm.c

As other power interfaces. Change-Id: I5e3b85ae21c4b1d0239f54fa75247b33cfdb7ddc Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 425 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 14 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 423

[PATCH 1/4] drm/amd/powerplay: optimize amdgpu_dpm_set_clockgating_by_smu() implementation

Cover the implementation details from outside(of power part). Change-Id: I8220c0c220b5dffa1024cffe35d79d721ba3ab2b Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 15 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 7 +++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0

[PATCH 3/4] drm/amd/powerplay: optimize i2c bus access implementation

The caller needs not care about the internal details how the powerplay API implemented. Change-Id: I942de0c9f78b2e2c0dfb7c67b82be2527c6825d3 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 15 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 3 +++ drivers

[PATCH 1/4] drm/amd/powerplay: optimize the interface for mgpu fan boost enablement

Cover the implementation details from outside(of power). Also preparing for expanding this to swSMU. Change-Id: I60072318d18926d196095123638d263bd4534b52 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 13

[PATCH 2/4] drm/amd/powerplay: enable swSMU mgpu fan boost support

Enable mgpu fan boost feature on swSMU routines. Change-Id: I2a48af3ed8b63cc1e601c8d6981e4d6bb3a0b7b8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 5 - drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 17 + drivers/gpu/drm/amd/powerplay/inc

[PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature

Support Navi1X mgpu fan boost enablement. Change-Id: Iafbf07c56462120d2db578b6af45dd7f985a4cc1 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 4 +++- drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 21 +++ 2 files changed, 24 insertions(+), 1

[PATCH 4/4] drm/amd/powerplay: enable Sienna Cichlid mgpu fan boost feature

Support Sienna Cichlid mgpu fan boost enablement. Change-Id: Ibcaeeff7c0accb490402a1714d23adbe1bb7804e Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay

[PATCH] drm/amd/powerplay: minor cleanups

Drop unnecessary lock protections during hw setup which was confirmed to have no race condition. Drop also unnecessary null pointer checker. Change-Id: Ida301ae7bad1abae15285c4e019eda4f7dc6e297 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 20 drivers/gpu

[PATCH] drm/amd/powerplay: bump NAVI12 driver if version

To fit the latest SMU firmware. Change-Id: Ic9d02de54d20b6b90d18bac8b3fbb356d8fdf3ad Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm

[PATCH 2/2] drm/amd/powerplay: maximum the code sharing around metrics table retrieving

Instead of having one copy in each ASIC. Change-Id: I5e2a72382700cdb0e4847e5d9e2143f4b5508cdb Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 55 ++- drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 41 +++--- drivers/gpu/drm/amd/powerplay

[PATCH 1/2] drm/amd/powerplay: update the metrics table cache interval as 1ms

To make the setting same as Arcturus/Navi1x/Sienna_Cichlid. Change-Id: I7ea721bf5872023f1ab39c3827fb9c6fd05877cc Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 2 +- drivers/gpu/drm/amd/powerplay

[PATCH] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading

The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to assume the bootup state in SMU based on the dpm status. Change-Id: Ib88298ab9812d7d242592bcd55eea140bef6696a Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 6 -- 1 file changed, 6

[PATCH] drm/amd/powerplay: correct Vega20 cached smu feature state

Correct the cached smu feature state on pp_features sysfs setting. Change-Id: Icc4c3ce764876a0ffdc86ad4c8a8b9c9f0ed0e97 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 38 +-- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers

[PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup(V3)

As VCN related dpm table setup needs VCN be in PG ungate state. Same logics applies to JPEG. V2: fix paste typo V3: code cosmetic Change-Id: I0e4d97ebedc132b7d793dc3f36275066ff999eac Signed-off-by: Evan Quan Tested-by: Matt Coffin Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay

[PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics

Add lock protections and avoid unnecessary actions if the PG state is already the same as required. Change-Id: I01400b84151d3ac6e3c8b0d7e264f9a68a9c2092 Signed-off-by: Evan Quan Tested-by: Matt Coffin Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 57

[PATCH] drm/amd/powerplay: grant Arcturus softmin/max setting on latest PM firmware

For Arcturus, the softmin/max settings from driver are permitted on the latest(54.26 later) SMU firmware. Thus enabling them in driver. Change-Id: Iff9ac326610075aa7f61cb89c64d2c4128678755 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 10 ++ 1 file changed

[PATCH 1/2] drm/amd/powerplay: update swSMU VCN/JPEG PG logics

Add lock protections and avoid unnecessary actions if the PG state is already the same as required. Change-Id: I01400b84151d3ac6e3c8b0d7e264f9a68a9c2092 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 57 ++- drivers/gpu/drm/amd/powerplay

[PATCH 2/2] drm/amd/powerplay: put VCN/JPEG into PG ungate state before dpm table setup

As VCN related dpm table setup needs VCN be in PG ungate state. Same logics applies to JPEG. Change-Id: I94335efc4e0424cfe0991e984c938998fd8f1287 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 38 +- 1 file changed, 30 insertions(+), 8 deletions

[PATCH 17/17] drm/amd/powerplay: add control method to bypass metrics cache on Vega12

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: Ic2a27ebc90f0a7cf581d0697c121b6d7df030f3b Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 29 --- 1 file

[PATCH 16/17] drm/amd/powerplay: add control method to bypass metrics cache on Vega20

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: I8836f7f096dceb08a90dd3c899d2e9ccea1ef1f3 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 31 --- 1 file

[PATCH 15/17] drm/amd/powerplay: add control method to bypass metrics cache on Renoir

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: I780aba0be35a35bd9c9727118b33625e7cc9bf1f Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++ 1 file

[PATCH 13/17] drm/amd/powerplay: add control method to bypass metrics cache on Navi10

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: I281b4de9262b98f0c52131feb39ba9e101b548b7 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 60 ++ 1 file

[PATCH 09/17] drm/amd/powerplay: enable gpu_metrics export on legacy powerplay routines

Enable gpu_metrics support on legacy powerplay routines. Change-Id: Ic2f09babe7e6bead9a838b7ce3c94bf8d4110991 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + 2 files changed, 20 insertions

[PATCH 02/17] drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)

A new interface for UMD to retrieve gpu metrics data. V2: rich the documentation Change-Id: If7f3523915505c0ece0a56dfd476d2b8473440d4 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- Documentation/gpu/amdgpu.rst | 6 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

[PATCH 14/17] drm/amd/powerplay: add control method to bypass metrics cache on Sienna Cichlid

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: Ic9d5f10b470584c82d4ca9035ab27fed44f0ac20 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/sienna_cichlid_ppt.c| 73 +-- 1 file

[PATCH 12/17] drm/amd/powerplay: add control method to bypass metrics cache on Arcturus

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: Ie6e9377f5984c3c09737b323c52249f9189bcaf5 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 74 +--- 1 file

[PATCH 08/17] drm/amd/powerplay: add Renoir support for gpu metrics export(V2)

Add Renoir gpu metrics export interface. V2: use memcpy to make code more compact Change-Id: Ic83265536eeaa9e458dc395b2be18ea49da4c68a Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + drivers/gpu/drm/amd/powerplay/renoir_ppt.c

[PATCH 06/17] drm/amd/powerplay: add Navi1x support for gpu metrics export

Add Navi1x gpu metrics export interface. Change-Id: I9028fb925e70c36fb2a0b00968c462c0bbc822db Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 93 +- 1 file changed, 91 insertions(+), 2 deletions(-) diff --git a/drivers

[PATCH 10/17] drm/amd/powerplay: add Vega20 support for gpu metrics export

Add Vega20 gpu metrics export interface. Change-Id: I7b4ab850358cc6d7455889d9031a7111cba35ebd Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 123 +- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.h| 1 + 2 files changed, 117 insertions(+), 7

[PATCH 11/17] drm/amd/powerplay: add Vega12 support for gpu metrics export

Add Vega12 gpu metrics export interface. Change-Id: I2c910f523049f0f90eecb8d74cb73ebb39a22bd9 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 111 ++ .../drm/amd/powerplay/hwmgr/vega12_hwmgr.h| 1 + 2 files changed, 112 insertions(+) diff

[PATCH 03/17] drm/amd/powerplay: implement SMU V11 common APIs for retrieving link speed/width

This will be shared around all SMU V11 asics. Change-Id: Iaa4554fb0e011b9f565d89375ac7b6a7eb525420 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +++ drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 9 +--- drivers/gpu/drm/amd

[PATCH 07/17] drm/amd/powerplay: add Sienna Cichlid support for gpu metrics export

Add Sienna Cichlid gpu metrics export interface. Change-Id: I89e6a4415fe467e7e4aaabe07d9e8cee379caa25 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- .../drm/amd/powerplay/sienna_cichlid_ppt.c| 91 ++- 1 file changed, 89 insertions(+), 2 deletions(-) diff --git

[PATCH 05/17] drm/amd/powerplay: update the data structure for NV12 SmuMetrics

Although it does not bring any problem for now, the coming gpu metrics interface needs to handle them differently based on the asic type. Change-Id: I88ee78c26795267588f944d4f1983e4dbf23ba85 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- .../powerplay/inc/smu11_driver_if_navi10.h

[PATCH 04/17] drm/amd/powerplay: add Arcturus support for gpu metrics export

Add Arcturus gpu metrics export interface. Change-Id: I372337f31e2b7174d41fb4e3af180deb94b5ec06 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 92 +++ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + drivers/gpu/drm

[PATCH 01/17] drm/amd/powerplay: define an universal data structure for gpu metrics (V4)

Thus we can provide an interface for UMD to retrieve gpu metrics data. V2: better naming and comments V3: two structures created for dGPU and APU separately V4: add driver attached timestamp Change-Id: Ibc2d5c642eff732c082f8447348749a44dc35be3 Signed-off-by: Evan Quan Reviewed-by: Alex Deucher

[PATCH 4/9] drm/amd/powerplay: add control method to bypass metrics cache on Arcturus

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: Ie6e9377f5984c3c09737b323c52249f9189bcaf5 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 74 +--- 1 file

[PATCH 8/9] drm/amd/powerplay: add control method to bypass metrics cache on Vega20

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: I8836f7f096dceb08a90dd3c899d2e9ccea1ef1f3 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 31 --- 1 file

[PATCH 7/9] drm/amd/powerplay: add control method to bypass metrics cache on Renoir

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: I780aba0be35a35bd9c9727118b33625e7cc9bf1f Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++ 1 file

[PATCH 6/9] drm/amd/powerplay: add control method to bypass metrics cache on Sienna Cichlid

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: Ic9d5f10b470584c82d4ca9035ab27fed44f0ac20 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/sienna_cichlid_ppt.c| 73 +-- 1 file

[PATCH 9/9] drm/amd/powerplay: add control method to bypass metrics cache on Vega12

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: Ic2a27ebc90f0a7cf581d0697c121b6d7df030f3b Signed-off-by: Evan Quan --- .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 29 --- 1 file

[PATCH 5/9] drm/amd/powerplay: add control method to bypass metrics cache on Navi10

As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Change-Id: I281b4de9262b98f0c52131feb39ba9e101b548b7 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 60 ++ 1 file

[PATCH 1/9] drm/amd/powerplay: enable gpu_metrics export on legacy powerplay routines

Enable gpu_metrics support on legacy powerplay routines. Change-Id: Ic2f09babe7e6bead9a838b7ce3c94bf8d4110991 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + 2 files changed, 20 insertions

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