Provided an unified entry point. And fixed the confusing that the API
usage is conflict with what the naming implies.
Change-Id: If068980ca6a7b223d0b4d087cd99cdeb729b0e77
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 23 ++--
drivers/gpu/drm/amd/amdgpu
: Ifb74d9cd89790b301e88d472b29cdb9b0365b65a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 98 ---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 10 ++
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +
drivers/gpu/drm/amd/powerplay
This is to fit the latest SMC firmware and it's backward compatible.
Change-Id: Ic561f83fa5d9d15a226b9f134da7e7ae90d9c6f9
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h | 8 +++-
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2
So that we do not need to allocate a piece of VRAM for it. This
is a preparation for coming change which unifies the VRAM address
for all driver tables interaction with SMU.
Change-Id: I967f960a10a19957ea7301aa40a8ced0c036ad68
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay
By this, we can avoid to pass in the VRAM address on every table
transferring. That puts extra unnecessary traffics on SMU on
some cases(e.g. polling the amdgpu_pm_info sysfs interface).
Change-Id: Ifb74d9cd89790b301e88d472b29cdb9b0365b65a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd
Simplify the table transferring between driver and SMU and use less
VRAM.
Change-Id: I3f9b54fd9b8c0bcaeb533fc1a07bb06050fefbd8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 101 ++
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
.../gpu/drm
By this, we can avoid to pass in the vram address on every table
transferring.
Change-Id: Ia8a3dbe923bc562286ab102a5830392a95dcf28c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 42 ---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 +
.../gpu
This is why those feature mask members designed for. And this
can reduce the SMU workload.
Change-Id: I2c6e12e945508f7b2fd79bc172efa68bc6150d05
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 61
The lock required was already hold by its parent API.
Change-Id: I2ffe63d2016a2e274d54634cd8f8c51cca8b3a1c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm
E.g. During non-RAS baco reset, the SMC is still alive.
Thus there is no need to reload the SMC firmware.
Change-Id: I73f6284541d0ca0e82761380a27e32484fb0061c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 14 ++
1 file changed, 14 insertions(+)
diff --git
Set mp1 state properly for non gpu reset cases.
Change-Id: I2a007910da6b5e2d1f8915d17827621ebd2e8c59
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 16 ++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
, we correct the firmware loading sequence to load
RLC save restore list related firmwares before RLCG
ucode. That will help to get around this issue.
Change-Id: I4f5cad5e6bb2e5fd632957163516d9be9498234b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu
This is used to determine whether runtime pm can be
supported or not.
Change-Id: I0b6452ae56094d768ece23ba62476f410f19e57b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm
Support custom power profile mode settings on Arcturus.
Change-Id: Id14f9a1cced41433b7487f447c452f8852964891
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 132 +-
.../powerplay/inc/smu11_driver_if_arcturus.h | 6 +-
2 files changed, 128
Knowing whether gpu recovery was performed successfully or not
is important for our BACO development.
Change-Id: I0e3ca4dcb65a053eb26bc55ad7431e4a42e160de
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
For non-RAS baco reset, there is no need to reset the SMC. Thus
the firmware reloading should be avoided.
Change-Id: I73f6284541d0ca0e82761380a27e32484fb0061c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 14
This is needed for coming asic init on performing gpu reset.
V2: use non-asic specific programing way
Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers
This is needed for coming asic init on performing gpu reset.
Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers
Abort the message issuing if the SMU was not in the right state.
Change-Id: Ida9f911e051f6e78de4f475956c78637e56e6ea3
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 16
2 files changed
Some minor cosmetic fixes.
Change-Id: I3ec217289f4cb491720430f2d0b0b4efe5e2b9aa
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 12 ++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 +-
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
drivers/gpu/drm
As the check may be done with purpose and the warning
output will be confusing.
Change-Id: Ie0928c324a8161d44068f8ce648d56f6d9e8cd3d
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
: error:
dereferencing pointer to incomplete type ‘struct amdgpu_ras’
if (!ras || !ras->supported) {
Change-Id: I1242e64e82715774b8e2931530749782b9107e32
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/
Enable baco reset support on Arcturus.
Change-Id: I7b69016ee0d238e0fcb323aa10215e29924a6ca6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c| 14
Added bif doorbell interrupt setting and applied different
settings for BACO reset for RAS recovery.
Change-Id: I823b2d478699d469ecc7746e2a8fb1110a4a146f
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 30 ---
1 file changed, 27 insertions(+), 3
-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c4f84627cfd9..0bbe3412d9b5 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
Otherwise, the error message prompted will confuse user.
Change-Id: I44b9f870a8663714d715a1d5bf2aa24abe75bb8e
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd
RunBTC is added for Navi ASIC on hardware setup.
Change-Id: I1c04b481ed14d5f12c20b7b0d592b62a65889e4a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers
Otherwise, without RLC reinitialization, the DPM reenablement
will fail. That affects the custom pptable uploading.
V2: setting/clearing uploading_custom_pp_table in
smu_sys_set_pp_table()
Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Reported-by: Matt Coffin
Signed-off-by: Evan Quan
Otherwise, without RLC reinitialization, the DPM reenablement
will fail. That affects the custom pptable uploading.
Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 32 +++
.../gpu/drm/amd/powerplay
Force clock level is for dpm manual mode only.
Change-Id: I3b4caf3fafc72197d65e2b9255c68e40e673e25e
Reported-by: Candice Li
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 ++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++--
drivers
: I90e29b0d839df26825d5993212f6097c7ad4bebf
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 101 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 1 -
2 files changed, 49 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b
-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 104 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 1 -
2 files changed, 52 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay
Need to update in cache feature enablement status after pp_feature
settings. Another fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu
Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay
Fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu
Change-Id: Id9a373f8d8866b97450be0aef0ba19d0835d40d8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 ++
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
2 files changed
Correct the settings for auto mode and skip the unnecessary
settings for dcefclk and fclk.
Change-Id: I7e6ca75ce86b4d5cd44920a9fbc71b6f36ea3c49
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 60 +--
1 file changed, 54 insertions(+), 6 deletions
"COMPUTE" was wrongly spelled as "CUSTOM".
Change-Id: I11693c0e55c2ce5c889d57bb7411fdf9795a8739
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arctu
d "*1000" in smu_v11_0_start_thermal_control
makes the output wrongly.
Change-Id: I2f1866edd1baf264f521310343f492eaede26c33
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 10
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 6 +++
drivers/gpu/drm/amd/powerplay/na
This is available with firmwareinfo table v3.2 or later.
Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 +++
2 files changed, 24
On fclk dpm disabled, the default dpm table will be setup with only one
level and clock frequency as bootup value.
Change-Id: Iecf74aa5bd10c9aa7839bc32877cfa99bcbef4b3
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Update smc fw and driver interface header.
Change-Id: If4ac09c41b1309f746b757f78880fffb491d50f8
Signed-off-by: Evan Quan
---
.../powerplay/inc/smu11_driver_if_arcturus.h| 17 +++--
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2 files changed, 12 insertions(+), 7
Do not expose those unsupported clock domains through sysfs on
Arcturus.
Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git
Those messages are not supported on Arcturus and should not be
issued.
Affected ASIC: Arcturus
Change-Id: I391099fc28e00356234fd2ae7b68f5861fd4c147
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd
This is not supported on Arcturus.
Affected ASIC: Arcturus
Change-Id: I62a8bce17a070ce4eda5fa22f4b12a7ffa1201cd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay
vcn dpm on is a prerequisite for vcn power gate control.
Change-Id: If89a81bc0709f1c26569e378507a873cfaf6e0ef
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 4 +++-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
Hook up the SW SMU power profile switch in KFD routine.
Change-Id: I41e53762cdc7504285de89f30e3e6e2bb396b953
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 8 +++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 36 +++
.../gpu/drm/amd/powerplay
Enable arcturus power profile retrieval and setting.
Change-Id: I85447ba9ca7de8e197840f76ce3745363c4133a6
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 69
1 file changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay
This can prevent CPU to use the out-dated copy.
Change-Id: Ia18e89a923e3522e01717aa4d5ba35f8f4f20763
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 4
drivers/gpu/drm/amd/powerplay/smumgr
DPM state relates are not supported on the new SW SMU ASICs. But still
it's not OK to trigger null pointer dereference on accessing them.
Change-Id: I368d108fbea438ed5d9e3b849d006ddd5308052b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 18 +-
drivers
Add checking for possible invalid input and null pointer. And
drop redundant code.
Change-Id: I6ebd6acd944e821fb19af77ed1eaa8c4b1d407ce
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 22 ++---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 24
Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.
Change-Id: Ibd3e48ae9a90ab57f42b3f2ddbb736deeebc8715
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 +---
1 file changed, 9
Drop redundant check, duplicate check, duplicate setting
and fix the return value.
Change-Id: I04171bcac82f17152371d05e6958d4fc072c0f6b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 33 +++---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 30
Honor the 'dpm' module parameter setting on SW SMU routine as what
we did on previous ASICs. SMU FW loading is still proceeded even
with "dpm=0".
Change-Id: I4e2bd434035c315391d0c0cbabb6ac8c6f23f239
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
1 fi
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
V2: a better naming
Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm
: I758e4461be34c0fcbdf19448e34180a5251926c4
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 29 +--
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 4 +--
4 files changed
No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.
Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26
VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.
Change-Id: Icc53d6fa176c48f0fc5348e79b8a5010357867eb
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +-
1 file changed, 36 insertions(+), 20 deletions(-)
diff
Enable VCN powergate status report on Raven.
Change-Id: I60c793f8185ce6799b40a0cabd97d9c9fe5483fd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b
VCN should be used for Vega20 later ASICs.
Evan Quan (5):
drm/amd/powerplay: add new sensor type for VCN powergate status
drm/amd/powerplay: support VCN powergate status retrieval on Raven
drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
drm/amd/powerplay: correct
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include
Commonly used for VCN powergate status retrieval for SW SMU.
Change-Id: Ibc2f498848f728eb7727cd3fa889e91a2b09d07b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers
For Navi10 or later ASICs, a different bit mask is used for checking
VCN power status.
Change-Id: Iaa49e5a339c38f46e3e7124d21aeb65f6633325e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers
With gfxclk or uclk dpm disabled, it's reasonable to report bootup clock
as the max supported.
Change-Id: If8aa7a912e8a34414b0e9c2b46de9b6e316fd9d7
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 27 ++-
1 file changed, 26 insertions(+), 1
Do not halt driver loading on if_version mismatch. As our
driver and FWs are backward compatible.
Change-Id: I01271202d08a62e775efabfb66310f6cc742b9dd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff
The interface was used in a confusing way. In profile mode scenario,
the 2nd parameter of the interface was used in a different way from
other scenarios.
Change-Id: Iabcebb47db8fdf242580c1059393132ee10b93e4
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 4
This can avoid them to be handled in a wrong way without notice.
Since not all SMU messages/clocks are supported on every SMU11 ASIC.
Change-Id: I440b80833c81066cd36613beae555f2fa068199f
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18
drivers/gpu/drm
Current implementation is not actually able to detect
invalid message/table/workload mapping.
Change-Id: I66588f20dc2c39dfeb8aefb66757812589eab812
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 ++--
drivers
As the lock was already held on the entrance to smu_handle_task.
- V2: lock in small granularity
Change-Id: I5388aa917ef0e330974e26c59db42d1354b6a865
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
As the lock was already held on the entrance to smu_handle_task.
Change-Id: I5388aa917ef0e330974e26c59db42d1354b6a865
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers
Fix memory allocation failure check.
- V2: fix one more similar error
Change-Id: I012b082a7a2b92973a76db8029897fb4a3441694
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
To match latest SMU firmware.
Change-Id: Icc8a687357ba46ae1d199d89cb2000c61b4de703
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
b
No access before allocation.
Change-Id: Ia1d78786f2400cd1cd227d1ab6ea4c6a71619e4c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm
Fix memory allocation failure check.
Change-Id: I012b082a7a2b92973a76db8029897fb4a3441694
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd
Increase the waiting time to 1s from 200ms. This is expected
to fix some mode1 reset failures.
Change-Id: I4c11996628cd40d559c6edea97d092f397122d78
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
MGPU fan boost feature should not be enabled until all the
devices from the same hive are all back from reset.
Change-Id: I03a69434ff28f4eac209bd91320dde8a238a33cf
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13
Use SMC default fan table if no external powerplay fan table.
Change-Id: Icd7467a7fc5287a92945ba0fcc19699192b1683a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c | 4 +++-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
drivers/gpu
This seems a merge error.
Change-Id: I67389739512c8297da1187428682cc59f560ab03
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
Implement Navi10 backend for runtime ppfeatures status retrieving
and setting support.
Change-Id: Ib498b934c260e351c6cafedcd865fd931319e7a3
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 165 +
1 file changed, 165 insertions(+)
diff --git
Make mem_busy_percent sysfs interface invisible on Vega10.
Change-Id: Ie39c3217b497a110b0b16e1b08033029bdcf2fc8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b
The UVD/VCE bits are set wrongly. This causes the UVD/VCE clocks
are not brought back correctly on needed.
Change-Id: I6eda67ea3be45fd5f422cdb78356915bf06ff41e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions
Support hotspot and memory temperature retrieval on sw smu routine.
Change-Id: If2ed1e2835f4b158a4a6d93aee8b358af18b9bfc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 74 ---
2 files changed, 66
Support realtime uclk activity report.
Change-Id: I89cf7c95233060ee106e9fcef3b8e6707cd60466
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b
Request too frequently may get corrupt data.
Change-Id: Ided23ab7dd0143575479644c5030cea71bdc53fd
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 33 +--
2 files changed, 34 insertions(+), 2
Support ppfeatures sysfs interface on Vega20 sw smu routine.
Change-Id: If67f2d87e7d5aa09cfd61e86df88d5f2f4dd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 10 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 7 +-
drivers/gpu/drm/amd/powerplay
There is already sw smu check on IP block adding.
Change-Id: I070290f4fd7acb2c425e8fded5696d4ac9e80ed8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b
smu_get_clk_info_from_vbios() was called repeatedly. It
seems a merge error.
Change-Id: Ice22a171cbb976d0aebd6609344a10b008d18f14
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay
On OD reset, the clock tables in SMU need to be reset to default.
Change-Id: Ibefc6636a436404839d9db6fb52e738f102c413f
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr
Update Vega10 ACG Avfs GB parameters.
Change-Id: Ic3d5b170b93a7a92949262323ca710dbf9ac49b4
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS
will be disabled. However, the buggy code makes this actually not
working as expected.
- V2: clear all OD flags excpet DPMTABLE_OD_UPDATE_VDDC
Change-Id: Ifa83a6255bb3f6fa4bdb4de616521cb7bab6830a
Signed-off-by: Evan Quan
This may affects the Vega10 MCLK OD functionality.
Change-Id: Icd685187501b4ec8867fb3c5077ea2664edbd114
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 35 +--
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd
No need to enable or disable AVFS if it's already in wanted
state.
Change-Id: I862c0c3d642e6a0dc7bb34e04c5a59f17b6b8deb
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr
With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS
will be disabled. However, the buggy code makes this actually not
working as expected.
Change-Id: Ifa83a6255bb3f6fa4bdb4de616521cb7bab6830a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7
Update Vega10 top performance level power state accordingly
on OD.
Change-Id: Iaadeefb2904222bf5f4d54b39d7179ce53f92ac0
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 59 +++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd
Negative lockup timeout is valid and will be treated as
'infinite timeout'.
- V2: use msecs_to_jiffies for negative values
Change-Id: I0d8387956a9c744073c0281ef2e1a547d4f16dec
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20
1 file changed, 12
Negative lockup timeout is valid and will be treated as
'infinite timeout'.
Change-Id: I0d8387956a9c744073c0281ef2e1a547d4f16dec
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
profile_exit performance level setting is valid only
when current mode is in profile mode.
Change-Id: I6940102d38dbb7a4b0233fce5277e1704672d8f4
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd
Every ring type can have its own timeout setting.
- V2: update lockup_timeout parameter format and cosmetic fixes
- V3: invalidate 0 and negative values
- V4: update lockup_timeout parameter format
Change-Id: I992f224f36bb33acd560162bffd2c3e987840a7e
Signed-off-by: Evan Quan
---
drivers/gpu
Every ring type can have its own timeout setting.
- V2: update lockup_timeout parameter format and cosmetic fixes
- V3: invalidate 0 and negative values
Change-Id: I992f224f36bb33acd560162bffd2c3e987840a7e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7
Every ring type can have its own timeout setting.
Change-Id: I992f224f36bb33acd560162bffd2c3e987840a7e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 82
Support DPM/DS/ULV related bitmasks of ppfeaturemask module parameter.
Change-Id: I6b75becf8d39105189b30be41b58ec7d4425f356
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 21 +++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd
A new module parameter is added for determining
whether or not to enforce timeout on compute jobs.
Change-Id: If14b75977312e42dac0431072456e5b69cf1bc2f
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
drivers
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